95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/time.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/fs.h>
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#include "bus.h"
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#define REG_CSPR3 (0xFFB00105)
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#define REG_CSOR3_OFFSET (0)
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#define REG_AMASK3 (0xFFFF0000)
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#define REG_CCR (0x03000000)
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#define REG_FTIM0 (0xE00E000E)
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#define REG_FTIM1 (0x0E001F00)
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#define REG_FTIM2 (0x0E00001F)
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static unsigned int g_bIsFPGAInited = 0;
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static unsigned int* g_pFPGAReg = NULL;
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static unsigned short* g_pRegBase = NULL;
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unsigned short read_fpga16(unsigned short offset)
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{
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return *((unsigned short*)(g_pRegBase + offset));
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}
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void write_fpga16(unsigned short offset, unsigned short value)
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{
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*((unsigned short*)(g_pRegBase + offset)) = value;
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}
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int fpga_bus_init(void)
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{
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unsigned int* pReg = NULL;
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unsigned short* pCs3 = NULL;
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if(g_bIsFPGAInited == 0)
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{
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pReg = (unsigned int*)ioremap((CSBAR + FPGA_BUS_REG_OFFSET),
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FPGA_BUS_REG_MAP_SIZE);
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//reg_cspr3
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pReg[FPGA_BUS_CSPR3_OFFSET] = REG_CSPR3;
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// //reg_amask3
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pReg[FPGA_BUS_AMASK3_OFFSET] = REG_AMASK3;
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// //csor 3
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pReg[FPGA_BUS_CSOR3_OFFSET] = REG_CSOR3_OFFSET;
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// // IFC_CCR //IFC_CLK= 50M ptr[(0x44C>>2)] = 0x07000000;
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// // IFC_CCR //IFC_CLK= 100M ptr[(0x44C>>2)] = 0x03000000;
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// // IFC_CCR //IFC_CLK= 200M ptr[(0x44C>>2)] = 0x01000000;
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// default for 100M
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pReg[FPGA_BUS_CCR_OFFSET] = REG_CCR;
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// // FTIM0_CS3_GPCM
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pReg[FPGA_BUS_FTIM0_OFFSET] = REG_FTIM0;
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// // FTIM1_CS3_GPCM
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pReg[FPGA_BUS_FTIM1_OFFSET] = REG_FTIM1;
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// // FTIM2_CS3_GPCM
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pReg[FPGA_BUS_FTIM2_OFFSET] = REG_FTIM2;
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g_pFPGAReg = pReg;
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pCs3 = (unsigned short*)ioremap(FPGA_BUS_BASE, FPGA_BUS_MAP_SIZE);
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g_pRegBase = pCs3;
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// Set GPIO Config
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write_fpga16(FPGA_GPIO_CFG_OFFSET, GPIO_DEFAULT_CFG);
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read_fpga16(FPGA_GPIO_CFG_OFFSET);
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// Set Global Reg
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write_fpga16(FPGA_GLOBAL_REG_OFFSET, GLOBAL_DEFAULT_CFG);
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}
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g_bIsFPGAInited = 1;
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return 0;
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}
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void fpga_bus_exit(void)
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{
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if(g_bIsFPGAInited == 1)
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{
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iounmap(g_pFPGAReg);
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iounmap(g_pRegBase);
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}
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g_bIsFPGAInited = 0;
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}
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#endif
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