511 lines
12 KiB
Plaintext
511 lines
12 KiB
Plaintext
/*
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* MPC8309SOM Device Tree Source
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*
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* Copyright (C) 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,mpc8309som";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8309@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <16384>;
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i-cache-size = <16384>;
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; // 256MB at 0
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <77 0x8>;
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interrupt-parent = <&ipic>;
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// CS0 and CS1 are swapped when booting from nand,
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// but the addresses are the same.
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ranges = <0x0 0x0 0xfe000000 0x00800000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x800000>;
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bank-width = <2>;
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device-width = <1>;
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u-boot@0 {
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reg = <0x0 0xa0000>;
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};
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kernel@0xa0000 {
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reg = <0xa0000 0x200000>;
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};
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fs@2a0000 {
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reg = <0x2a0000 0x500000>;
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};
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dtb@7a0000 {
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reg = <0x7a0000 0x40000>;
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};
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iram@7e0000 {
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reg = <0x7e0000 0xffff>;
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read-only;
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};
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};
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fpga1@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,bus";
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reg = <0x1 0x0 0x2000000>;
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interrupts = <48 8>;
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interrupt-parent = <&ipic>;
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};
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irq1@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,irq1";
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reg = <0x1 0x0 0x2000000>;
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interrupts = <17 8>;
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interrupt-parent = <&ipic>;
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};
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irq3@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,irq3";
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reg = <0x1 0x0 0x2000000>;
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interrupts = <19 8>;
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interrupt-parent = <&ipic>;
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};
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// CS2 for T1/E1 framer
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framer@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "framer";
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reg = <0x2 0x0 0x2000>;
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};
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};
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immr@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8309-immr", "simple-bus";
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ranges = <0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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cell-index = <3>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <15 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <38 0x8>;
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phy_type = "ulpi";
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};
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spi@7000 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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};
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/*
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proslic {
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device_type="slic";
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compatible = "proslic";
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clock-frequency = <0>;
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interrupts = <0x17 0x8>;
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interrupt-parent = < &ipic >;
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};
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*/
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ptp_timer: ptimer@24e00 {
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compatible = "fsl,gianfar-ptp-timer";
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reg = <0x24e00 0xb0>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <133333333>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <133333333>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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/*
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gpio@c00 {
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device_type = "gpio";
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compatible = "fsl,mpc8315-gpio";
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reg = <0xc00 0x18>;
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interrupt-parent = < &ipic >;
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};
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*/
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sdhci@2e000 {
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compatible = "fsl,esdhc", "fsl,mpc8309-esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <42 0x8>;
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interrupt-parent = <&ipic>;
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sdhci,clock-enable;
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/* Filled in by U-Boot */
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clock-frequency = <111111111>;
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};
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/*
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can0@1c000 {
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compatible = "fsl,mpc830x-flexcan";
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cell-index = <0>;
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reg = <0x1c000 0x1000>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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*/
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: interrupt-controller@700 {
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compatible = "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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device_type = "ipic";
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};
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/* ipic-msi@7c0 {
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compatible = "fsl,ipic-msi";
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reg = <0x7c0 0x40>;
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msi-available-ranges = <0x0 0x100>;
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interrupts = < 0x43 0x8
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0x4 0x8
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0x51 0x8
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0x52 0x8
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0x56 0x8
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0x57 0x8
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0x58 0x8
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0x59 0x8 >;
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interrupt-parent = < &ipic >;
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};
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*/
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/* pmc: power@b00 {
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compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 8>;
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interrupt-parent = <&ipic>;
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fsl,mpc8313-wakeup-timer = <>m1>;
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};
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*/
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gtm1: timer@500 {
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compatible = "fsl,mpc8313-gtm", "fsl,gtm";
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reg = <0x500 0x100>;
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clock-frequency = <133000000>;
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interrupts = <90 8 78 8 84 8 72 8>;
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interrupt-parent = <&ipic>;
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0100000 0x00100000>;
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reg = <0xe0100000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <125000000>;
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fsl,qe-num-riscs = <1>;
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fsl,qe-num-snums = <28>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x00010000 0x00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x4000>;
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};
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};
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enet0: ethernet@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "none";
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fixed-link = <1 1 100 0 0>;
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/* phy-handle = <&phy0>;
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phy-connection-type = "mii";*/
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};
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enet2: ethernet@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <3>;
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reg = <0x2200 0x200>;
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interrupts = <33>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "none";
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fixed-link = <3 3 100 2 2>;
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};
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enet1: ethernet@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <2>;
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reg = <0x3000 0x200>;
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interrupts = <34>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "none";
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fixed-link = <2 2 100 1 1>;
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/* phy-handle = <&phy0>;
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phy-connection-type = "mii";
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*/
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};
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/*
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mdio@2120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2120 0x18>;
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compatible = "fsl,ucc-mdio";
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phy0: ethernet-phy@00 {
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interrupt-parent = <&ipic>;
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interrupts = <48 0x8>;
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reg = <0x11>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@01 {
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interrupt-parent = <&ipic>;
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interrupts = <48 0x8>;
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reg = <0x12>;
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device_type = "ethernet-phy";
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};
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};
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*/
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ucc@2400 {
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device_type = "tdm";
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compatible = "ucc-tdm0";
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cell-index = <5>;
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tdm-num = <1>;
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si-num = <1>;
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tdm-rx-clock = "clk3";
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tdm-tx-clock = "clk4";
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tdm-rx-sync = "RSYNC";
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tdm-tx-sync = "TSYNC";
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reg = <0x2400 0x200>;
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interrupts = <40>;
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interrupt-parent = <&qeic>;
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};
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ucc@2600 {
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device_type = "tdm";
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compatible = "ucc-tdm1";
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cell-index = <7>;
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tdm-num = <2>;
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si-num = <2>;
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tdm-rx-clock = "clk5";
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tdm-tx-clock = "clk6";
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tdm-rx-sync = "RSYNC";
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tdm-tx-sync = "TSYNC";
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reg = <0x2600 0x200>;
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interrupts = <42>;
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interrupt-parent = <&qeic>;
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <32 0x8 33 0x8>; // high:32 low:33
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interrupt-parent = <&ipic>;
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};
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};
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pci0: pci@e0008500 {
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cell-index = <1>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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// IDSEL 0x11 AD17 (Mini1)
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0x8800 0x0 0x0 0x1 &ipic 18 0x8
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0x8800 0x0 0x0 0x2 &ipic 18 0x8
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0x8800 0x0 0x0 0x3 &ipic 18 0x8
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0x8800 0x0 0x0 0x4 &ipic 18 0x8
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// IDSEL 0x12 AD18 (PCI/Mini2)
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0x9000 0x0 0x0 0x1 &ipic 18 0x8
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0x9000 0x0 0x0 0x2 &ipic 18 0x8
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0x9000 0x0 0x0 0x3 &ipic 18 0x8
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0x9000 0x0 0x0 0x4 &ipic 18 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 // internal registers
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0xe0008300 0x8>; // config space access registers
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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