/*
 * MPC8309SOM Device Tree Source
 *
 * Copyright (C) 2011 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	compatible = "fsl,mpc8309som";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8309@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <16384>;
			i-cache-size = <16384>;
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	// 256MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// CS0 and CS1 are swapped when booting from nand,
		// but the addresses are the same.
		ranges = <0x0 0x0 0xfe000000 0x00800000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <2>;
			device-width = <1>;

			u-boot@0 {
				reg = <0x0 0xa0000>;
				};

			kernel@0xa0000 {
				reg = <0xa0000 0x200000>;
			};

			fs@2a0000 {
				reg = <0x2a0000 0x500000>;
			};
            
			dtb@7a0000 {
				reg = <0x7a0000 0x40000>;
			};

			iram@7e0000 {
				reg = <0x7e0000 0xffff>;
				read-only;
			};
		};

               fpga1@1,0 {
		  #address-cells = <1>;
	          #size-cells = <1>;
		  compatible = "fsl,bus";
	          reg = <0x1 0x0 0x2000000>;
		  interrupts = <48 8>;
		  interrupt-parent = <&ipic>;
		  
                };   
                    
     irq1@1,0 {
		  #address-cells = <1>;
	          #size-cells = <1>;
		  compatible = "fsl,irq1";
	          reg = <0x1 0x0 0x2000000>;
		  interrupts = <17 8>;
		  interrupt-parent = <&ipic>;
		  
                }; 

     irq3@1,0 {
		  #address-cells = <1>;
	          #size-cells = <1>;
		  compatible = "fsl,irq3";
	          reg = <0x1 0x0 0x2000000>;
		  interrupts = <19 8>;
		  interrupt-parent = <&ipic>;
		  
                }; 
		// CS2 for T1/E1 framer
		framer@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "framer";
			reg = <0x2 0x0 0x2000>;
		};
                
	};

	immr@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,mpc8309-immr", "simple-bus";
		ranges = <0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

   dma@82a8 {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
                        reg = <0x82a8 4>;
                        ranges = <0 0x8100 0x1a8>;
                        interrupt-parent = <&ipic>;
                        interrupts = <71 8>;
                        cell-index = <0>;
                  dma-channel@0 {
                        compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
                        reg = <0 0x80>;
                        cell-index = <0>;
                        interrupt-parent = <&ipic>;
                        interrupts = <71 8>;
                     };
                   dma-channel@80 {
                       compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
                        reg = <0x80 0x80>;
                        cell-index = <1>;
                        interrupt-parent = <&ipic>;
                        interrupts = <71 8>;
                     };
                dma-channel@100 {
                      compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
                       reg = <0x100 0x80>;
                       cell-index = <2>;
                       interrupt-parent = <&ipic>;
                       interrupts = <71 8>;
                     };
                dma-channel@180 {
                        compatible = "fsl,mpc8309-dma-channel", "fsl,elo-dma-channel";
                        reg = <0x180 0x28>;
                        cell-index = <3>;
                        interrupt-parent = <&ipic>;
                        interrupts = <71 8>;
                     };
                };


		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};


		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			phy_type = "ulpi";
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};
/*
		proslic {
			device_type="slic";
			compatible = "proslic";
			clock-frequency = <0>;
			interrupts = <0x17 0x8>;
			interrupt-parent = < &ipic >;
		};
		*/

		ptp_timer: ptimer@24e00 {
			compatible = "fsl,gianfar-ptp-timer";
			reg = <0x24e00 0xb0>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <133333333>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <133333333>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};


/*
		gpio@c00 {
			device_type = "gpio";
			compatible = "fsl,mpc8315-gpio";
			reg = <0xc00 0x18>;
			interrupt-parent = < &ipic >;
		};
*/

		sdhci@2e000 {
			compatible = "fsl,esdhc", "fsl,mpc8309-esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <42 0x8>;
			interrupt-parent = <&ipic>;
			sdhci,clock-enable;
			/* Filled in by U-Boot */
			clock-frequency = <111111111>;
		};
/*
		can0@1c000 {
			compatible = "fsl,mpc830x-flexcan";
			cell-index = <0>;
			reg = <0x1c000 0x1000>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};
		*/

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: interrupt-controller@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

/*		ipic-msi@7c0 {
			compatible = "fsl,ipic-msi";
			reg = <0x7c0 0x40>;
			msi-available-ranges = <0x0 0x100>;
			interrupts = < 0x43 0x8
					0x4  0x8
					0x51 0x8
					0x52 0x8
					0x56 0x8
					0x57 0x8
					0x58 0x8
					0x59 0x8 >;
			interrupt-parent = < &ipic >;
		};
*/
/*		pmc: power@b00 {
			compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 8>;
			interrupt-parent = <&ipic>;
			fsl,mpc8313-wakeup-timer = <&gtm1>;
		};
*/
		gtm1: timer@500 {
			compatible = "fsl,mpc8313-gtm", "fsl,gtm";
			reg = <0x500 0x100>;
			clock-frequency = <133000000>;
			interrupts = <90 8 78 8 84 8 72 8>;
			interrupt-parent = <&ipic>;
		};

	};

	qe@e0100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0100000 0x00100000>;
		reg = <0xe0100000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <125000000>;
		fsl,qe-num-riscs = <1>;
		fsl,qe-num-snums = <28>;

		muram@10000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x00010000 0x00004000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0x4000>;
			};
		};

		enet0: ethernet@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <1>;
			reg = <0x2000 0x200>;
			interrupts = <32>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "none";
			fixed-link = <1 1 100 0 0>;
		/*	phy-handle = <&phy0>;
			phy-connection-type = "mii";*/
		};

		enet2: ethernet@3000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <3>;			
			reg = <0x2200 0x200>;
			interrupts = <33>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "none";
			fixed-link = <3 3 100 2 2>;
		};

		enet1: ethernet@2200 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <2>;
			reg = <0x3000 0x200>;
			interrupts = <34>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "none";			
			fixed-link = <2 2 100 1 1>;
	/*		phy-handle = <&phy0>;
			phy-connection-type = "mii";
			*/
		};
/*
		mdio@2120 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2120 0x18>;
			compatible = "fsl,ucc-mdio";

			phy0: ethernet-phy@00 {
				interrupt-parent = <&ipic>;
				interrupts = <48 0x8>;
				reg = <0x11>;
				device_type = "ethernet-phy";
			};
		
			phy1: ethernet-phy@01 {
				interrupt-parent = <&ipic>;
				interrupts = <48 0x8>;
				reg = <0x12>;
				device_type = "ethernet-phy";
			};
		  
		};
	
			*/

		ucc@2400 {
			device_type = "tdm";
			compatible = "ucc-tdm0";
			cell-index = <5>;
			tdm-num = <1>;
			si-num = <1>;

			tdm-rx-clock = "clk3";
			tdm-tx-clock = "clk4";
			tdm-rx-sync = "RSYNC";
			tdm-tx-sync = "TSYNC";

			reg = <0x2400 0x200>;
			interrupts = <40>;
			interrupt-parent = <&qeic>;
		};

		ucc@2600 {
			device_type = "tdm";
			compatible = "ucc-tdm1";
			cell-index = <7>;
			tdm-num = <2>;
			si-num = <2>;

			tdm-rx-clock = "clk5";
			tdm-tx-clock = "clk6";
			tdm-rx-sync = "RSYNC";
			tdm-tx-sync = "TSYNC";

			reg = <0x2600 0x200>;
			interrupts = <42>;
			interrupt-parent = <&qeic>;
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <32 0x8 33 0x8>; // high:32 low:33
			interrupt-parent = <&ipic>;
		};
	};
 
	pci0: pci@e0008500 {
		cell-index = <1>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
				// IDSEL 0x11 AD17 (Mini1)
				 0x8800 0x0 0x0 0x1 &ipic 18 0x8
				 0x8800 0x0 0x0 0x2 &ipic 18 0x8
				 0x8800 0x0 0x0 0x3 &ipic 18 0x8
				 0x8800 0x0 0x0 0x4 &ipic 18 0x8

				// IDSEL 0x12 AD18 (PCI/Mini2) 
				 0x9000 0x0 0x0 0x1 &ipic 18 0x8
				 0x9000 0x0 0x0 0x2 &ipic 18 0x8
				 0x9000 0x0 0x0 0x3 &ipic 18 0x8
				 0x9000 0x0 0x0 0x4 &ipic 18 0x8>;

		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		// internal registers 
		       0xe0008300 0x8>;		// config space access registers 
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
   
};