/* * drivers/net/gianfar.c * * Gianfar Ethernet Driver * This driver is designed for the non-CPM ethernet controllers * on the 85xx and 83xx family of integrated processors * Based on 8260_io/fcc_enet.c * * Author: Andy Fleming * Maintainer: Kumar Gala * Modifier: Sandeep Gopalpet * * Copyright 2002-2011 Freescale Semiconductor, Inc. * Copyright 2007 MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * Gianfar: AKA Lambda Draconis, "Dragon" * RA 11 31 24.2 * Dec +69 19 52 * V 3.84 * B-V +1.62 * * Theory of operation * * The driver is initialized through of_device. Configuration information * is therefore conveyed through an OF-style device tree. * * The Gianfar Ethernet Controller uses a ring of buffer * descriptors. The beginning is indicated by a register * pointing to the physical address of the start of the ring. * The end is determined by a "wrap" bit being set in the * last descriptor of the ring. * * When a packet is received, the RXF bit in the * IEVENT register is set, triggering an interrupt when the * corresponding bit in the IMASK register is also set (if * interrupt coalescing is active, then the interrupt may not * happen immediately, but will wait until either a set number * of frames or amount of time have passed). In NAPI, the * interrupt handler will signal there is work to be done, and * exit. This method will start at the last known empty * descriptor, and process every subsequent descriptor until there * are none left with data (NAPI will stop after a set number of * packets to give time to other tasks, but will eventually * process all the packets). The data arrives inside a * pre-allocated skb, and so after the skb is passed up to the * stack, a new skb must be allocated, and the address field in * the buffer descriptor must be updated to indicate this new * skb. * * When the kernel requests that a packet be transmitted, the * driver starts where it left off last time, and points the * descriptor at the buffer which was passed in. The driver * then informs the DMA engine that there are packets ready to * be transmitted. Once the controller is finished transmitting * the packet, an interrupt may be triggered (under the same * conditions as for reception, but depending on the TXF bit). * The driver then cleans up the buffer. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef CONFIG_GFAR_SW_PKT_STEERING #include #endif #ifdef CONFIG_NET_GIANFAR_FP #include #include #include #include #include #endif #include #include "gianfar.h" #ifdef CONFIG_AS_FASTPATH #include devfp_hook_t devfp_rx_hook; EXPORT_SYMBOL(devfp_rx_hook); devfp_hook_t devfp_tx_hook; EXPORT_SYMBOL(devfp_tx_hook); #endif #ifdef CONFIG_RX_TX_BD_XNGE #define RT_PKT_ID 0xff #endif #ifdef CONFIG_RX_TX_BD_XNGE #define TX_TIMEOUT (5*HZ) #else #define TX_TIMEOUT (1*HZ) #endif #undef BRIEF_GFAR_ERRORS #undef VERBOSE_GFAR_ERRORS extern void tcp_v4_send_reset(struct sock* sk, struct sk_buff* skb); const char gfar_driver_name[] = "Gianfar Ethernet"; const char gfar_driver_version[] = "1.4-skbr1.1.5"; static int gfar_enet_open(struct net_device* dev); static int gfar_start_xmit(struct sk_buff* skb, struct net_device* dev); static void gfar_reset_task(struct work_struct* work); static void gfar_timeout(struct net_device* dev); static int gfar_close(struct net_device* dev); struct sk_buff* gfar_new_skb(struct net_device* dev); static void gfar_new_rxbdp(struct gfar_priv_rx_q* rx_queue, struct rxbd8* bdp, struct sk_buff* skb); static int gfar_set_mac_address(struct net_device* dev); static int gfar_change_mtu(struct net_device* dev, int new_mtu); static irqreturn_t gfar_error(int irq, void* dev_id); static irqreturn_t gfar_transmit(int irq, void* dev_id); static irqreturn_t gfar_interrupt(int irq, void* dev_id); static void adjust_link(struct net_device* dev); static void init_registers(struct net_device* dev); static int init_phy(struct net_device* dev); static int gfar_probe(struct of_device* ofdev, const struct of_device_id* match); static int gfar_remove(struct of_device* ofdev); static void free_skb_resources(struct gfar_private* priv); static void gfar_set_multi(struct net_device* dev); static void gfar_set_hash_for_addr(struct net_device* dev, u8* addr); static void gfar_configure_serdes(struct net_device* dev); #ifdef CONFIG_GIANFAR_TXNAPI static int gfar_poll_tx(struct napi_struct* napi, int budget); static int gfar_poll_rx(struct napi_struct* napi, int budget); #else static int gfar_poll(struct napi_struct* napi, int budget); #endif #ifdef CONFIG_NET_POLL_CONTROLLER static void gfar_netpoll(struct net_device* dev); #endif #ifdef CONFIG_NET_GIANFAR_FP static int gfar_accept_fastpath(struct net_device* dev, struct dst_entry* dst); DECLARE_PER_CPU(struct netif_rx_stats, netdev_rx_stat); #endif int gfar_clean_rx_ring(struct gfar_priv_rx_q* rx_queue, int rx_work_limit); #ifdef CONFIG_GIANFAR_TXNAPI static int gfar_clean_tx_ring(struct gfar_priv_tx_q* tx_queue, int tx_work_limit); #else static int gfar_clean_tx_ring(struct gfar_priv_tx_q* tx_queue); #endif static int gfar_process_frame(struct net_device* dev, struct sk_buff* skb, int amount_pull); static void gfar_vlan_rx_register(struct net_device* netdev, struct vlan_group* grp); void gfar_halt(struct net_device* dev); static void gfar_halt_nodisable(struct net_device* dev); void gfar_start(struct net_device* dev); static void gfar_clear_exact_match(struct net_device* dev); static void gfar_set_mac_for_addr(struct net_device* dev, int num, u8* addr); static int gfar_ioctl(struct net_device* dev, struct ifreq* rq, int cmd); #ifdef CONFIG_PM static void gfar_halt_rx(struct net_device* dev); static void gfar_halt_tx_nodisable(struct net_device* dev); static void gfar_rx_start(struct net_device* dev); static void gfar_tx_start(struct net_device* dev); static void gfar_enable_filer(struct net_device* dev); static int gfar_get_ip(struct net_device* dev); static void gfar_config_filer_table(struct net_device* dev); #endif #ifdef CONFIG_GFAR_SKBUFF_RECYCLING static unsigned int skbuff_truesize(unsigned int buffer_size); static void gfar_skbr_register_truesize(struct gfar_private* priv); static int gfar_kfree_skb(struct sk_buff* skb, int qindex); static void gfar_reset_skb_handler(struct gfar_skb_handler* sh); static inline void gfar_clean_reclaim_skb(struct sk_buff* skb); #endif MODULE_AUTHOR("Freescale Semiconductor, Inc"); MODULE_DESCRIPTION("Gianfar Ethernet Driver"); MODULE_LICENSE("GPL"); static void gfar_init_rxbdp(struct gfar_priv_rx_q* rx_queue, struct rxbd8* bdp, dma_addr_t buf) { u32 lstatus; bdp->bufPtr = buf; lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); if(bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) { lstatus |= BD_LFLAG(RXBD_WRAP); } eieio(); bdp->lstatus = lstatus; } static int gfar_init_bds(struct net_device* ndev) { struct gfar_private* priv = netdev_priv(ndev); struct gfar_priv_tx_q* tx_queue = NULL; struct gfar_priv_rx_q* rx_queue = NULL; struct txbd8* txbdp; struct rxbd8* rxbdp; int i, j, num; for(i = 0; i < priv->num_tx_queues; i++) { tx_queue = priv->tx_queue[i]; /* Initialize some variables in our dev structure */ tx_queue->num_txbdfree = tx_queue->tx_ring_size; tx_queue->dirty_tx = tx_queue->tx_bd_base; tx_queue->cur_tx = tx_queue->tx_bd_base; tx_queue->skb_curtx = 0; tx_queue->skb_dirtytx = 0; /* Initialize Transmit Descriptor Ring */ txbdp = tx_queue->tx_bd_base; for(j = 0; j < tx_queue->tx_ring_size; j++) { txbdp->lstatus = 0; txbdp->bufPtr = 0; txbdp++; } /* Set the last descriptor in the ring to indicate wrap */ txbdp--; txbdp->status |= TXBD_WRAP; } if((priv->device_flags & FSL_GIANFAR_DEV_HAS_ARP_PACKET)) { num = priv->num_rx_queues - 1; } else { num = priv->num_rx_queues; } for(i = 0; i < num; i++) { rx_queue = priv->rx_queue[i]; rx_queue->cur_rx = rx_queue->rx_bd_base; rx_queue->skb_currx = 0; rxbdp = rx_queue->rx_bd_base; for(j = 0; j < rx_queue->rx_ring_size; j++) { struct sk_buff* skb = rx_queue->rx_skbuff[j]; if(skb) { gfar_init_rxbdp(rx_queue, rxbdp, rxbdp->bufPtr); } else { skb = gfar_new_skb(ndev); if(!skb) { pr_err("%s: Can't allocate RX buffers\n", ndev->name); goto err_rxalloc_fail; } rx_queue->rx_skbuff[j] = skb; gfar_new_rxbdp(rx_queue, rxbdp, skb); } rxbdp++; } } return 0; err_rxalloc_fail: free_skb_resources(priv); return -ENOMEM; } unsigned long alloc_bds(struct gfar_private* priv, dma_addr_t* addr) { unsigned long vaddr; unsigned long region_size; region_size = (sizeof(struct txbd8) + sizeof(struct sk_buff*)) * priv->total_tx_ring_size + (sizeof(struct rxbd8) + sizeof(struct sk_buff*)) * priv->total_rx_ring_size; #ifdef CONFIG_GIANFAR_L2SRAM vaddr = (unsigned long) mpc85xx_cache_sram_alloc(region_size, (phys_addr_t*)addr, ALIGNMENT); if(vaddr == NULL) { /* fallback to normal memory rather than stop working */ vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev, region_size, addr, GFP_KERNEL); priv->bd_in_ram = 1; } else { priv->bd_in_ram = 0; } #else vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev, region_size, addr, GFP_KERNEL); #endif return vaddr; } static inline void gfar_rx_checksum(struct sk_buff* skb, struct rxfcb* fcb) { /* If valid headers were found, and valid sums * were verified, then we tell the kernel that no * checksumming is necessary. Otherwise, it is */ if((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) { skb->ip_summed = CHECKSUM_UNNECESSARY; } else { skb->ip_summed = CHECKSUM_NONE; } } static int gfar_alloc_skb_resources(struct net_device* ndev) { void* vaddr; dma_addr_t addr; int i, j, k; struct gfar_private* priv = netdev_priv(ndev); struct gfar_priv_tx_q* tx_queue = NULL; struct gfar_priv_rx_q* rx_queue = NULL; struct rxbd8* wkbdp; unsigned long wk_buf_paddr; unsigned long wk_buf_vaddr; int err = 0; priv->total_tx_ring_size = 0; for(i = 0; i < priv->num_tx_queues; i++) { priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; } priv->total_rx_ring_size = 0; for(i = 0; i < priv->num_rx_queues; i++) { priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; } /* Allocate memory for the buffer descriptors */ vaddr = alloc_bds(priv, &addr); if(!vaddr) { if(netif_msg_ifup(priv)) pr_err("%s: Could not allocate buffer descriptors!\n", ndev->name); return -ENOMEM; } for(i = 0; i < priv->num_tx_queues; i++) { tx_queue = priv->tx_queue[i]; tx_queue->tx_bd_base = (struct txbd8*) vaddr; tx_queue->tx_bd_dma_base = addr; tx_queue->dev = ndev; /* enet DMA only understands physical addresses */ addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; } /* Start the rx descriptor ring where the tx ring leaves off */ for(i = 0; i < priv->num_rx_queues; i++) { rx_queue = priv->rx_queue[i]; rx_queue->rx_bd_base = (struct rxbd8*) vaddr; rx_queue->rx_bd_dma_base = addr; rx_queue->dev = ndev; addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; } /* Setup the skbuff rings */ for(i = 0; i < priv->num_tx_queues; i++) { tx_queue = priv->tx_queue[i]; #ifdef CONFIG_GIANFAR_L2SRAM tx_queue->tx_skbuff = (struct sk_buff**) vaddr; vaddr += sizeof(struct sk_buff**) * tx_queue->tx_ring_size; #else tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * tx_queue->tx_ring_size, GFP_KERNEL); #endif if(!tx_queue->tx_skbuff) { if(netif_msg_ifup(priv)) pr_err("%s: Could not allocate tx_skbuff\n", ndev->name); goto cleanup; } for(k = 0; k < tx_queue->tx_ring_size; k++) { tx_queue->tx_skbuff[k] = NULL; } } for(i = 0; i < priv->num_rx_queues; i++) { rx_queue = priv->rx_queue[i]; #ifdef CONFIG_GIANFAR_L2SRAM rx_queue->rx_skbuff = (struct sk_buff**) vaddr; vaddr += sizeof(struct sk_buff**) * rx_queue->rx_ring_size; #else rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * rx_queue->rx_ring_size, GFP_KERNEL); #endif if(!rx_queue->rx_skbuff) { if(netif_msg_ifup(priv)) pr_err("%s: Could not allocate rx_skbuff\n", ndev->name); goto cleanup; } for(j = 0; j < rx_queue->rx_ring_size; j++) { rx_queue->rx_skbuff[j] = NULL; } } if(gfar_init_bds(ndev)) { goto cleanup; } if((priv->device_flags & FSL_GIANFAR_DEV_HAS_ARP_PACKET)) { /* Alloc wake up rx buffer, wake up buffer need 64 bytes aligned */ rx_queue = priv->rx_queue[priv->num_rx_queues - 1]; rx_queue->cur_rx = rx_queue->rx_bd_base; vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev, priv->wk_buffer_size * rx_queue->rx_ring_size \ + RXBUF_ALIGNMENT, &addr, GFP_KERNEL); if(vaddr == 0) { if(netif_msg_ifup(priv)) printk(KERN_ERR "%s:Could not allocate wakeup buffer!\n" , ndev->name); err = -ENOMEM; goto wk_buf_fail; } priv->wk_buf_vaddr = vaddr; priv->wk_buf_paddr = addr; wk_buf_vaddr = (unsigned long)(vaddr + RXBUF_ALIGNMENT) \ & ~(RXBUF_ALIGNMENT - 1); wk_buf_paddr = (unsigned long)(addr + RXBUF_ALIGNMENT) \ & ~(RXBUF_ALIGNMENT - 1); priv->wk_buf_align_vaddr = wk_buf_vaddr; priv->wk_buf_align_paddr = wk_buf_paddr; /* Setup wake up rx ring and buffer */ wkbdp = rx_queue->rx_bd_base; for(i = 0; i < rx_queue->rx_ring_size; i++) { wkbdp->status = RXBD_EMPTY | RXBD_INTERRUPT; wkbdp->length = 0; wkbdp->bufPtr = wk_buf_paddr + priv->wk_buffer_size * i; wkbdp++; } /* Set the last descriptor in the ring to wrap */ wkbdp--; wkbdp->status |= RXBD_WRAP; } return 0; wk_buf_fail: dma_free_coherent(&priv->ofdev->dev, priv->wk_buffer_size * rx_queue->rx_ring_size \ + RXBUF_ALIGNMENT, (void*)priv->wk_buf_vaddr, priv->wk_buf_paddr); cleanup: free_skb_resources(priv); return -ENOMEM; } static void gfar_init_tx_rx_base(struct gfar_private* priv) { struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 __iomem* baddr; int i; #ifdef CONFIG_PHYS_64BIT dma_addr_t addr; addr = priv->tx_queue[0]->tx_bd_dma_base; gfar_write(®s->tbaseh, ((addr >> 32) & GFAR_TX_BASE_H)); addr = priv->rx_queue[0]->rx_bd_dma_base; gfar_write(®s->rbaseh, ((addr >> 32) & GFAR_RX_BASE_H)); #endif baddr = ®s->tbase0; for(i = 0; i < priv->num_tx_queues; i++) { gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); baddr += 2; } baddr = ®s->rbase0; for(i = 0; i < priv->num_rx_queues; i++) { gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); baddr += 2; } } static void gfar_init_mac(struct net_device* ndev) { struct gfar_private* priv = netdev_priv(ndev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 rctrl = 0; u32 tctrl = 0; u32 attrs = 0; /* write the tx/rx base registers */ gfar_init_tx_rx_base(priv); /* Configure the coalescing support */ gfar_configure_tx_coalescing(priv, 0xFF); gfar_configure_rx_coalescing(priv, 0xFF); if(priv->rx_filer_enable) { rctrl |= RCTRL_FILREN; /* Program the RIR0 reg with the required distribution */ gfar_write(®s->rir0, DEFAULT_RIR0); } if(priv->rx_csum_enable) { rctrl |= RCTRL_CHECKSUMMING; } if(priv->extended_hash) { rctrl |= RCTRL_EXTHASH; gfar_clear_exact_match(ndev); rctrl |= RCTRL_EMEN; } if(priv->padding) { rctrl &= ~RCTRL_PAL_MASK; rctrl |= RCTRL_PADDING(priv->padding); } if(priv->ptimer_present) { /* Enable Filer and Rx Packet Parsing capability of eTSEC */ /* Set Filer Table */ gfar_1588_start(ndev); if(priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) { rctrl &= ~RCTRL_PAL_MASK; } /* Enable Filer for Rx Queue */ rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8); priv->padding = 0x8; } /* keep vlan related bits if it's enabled */ if(priv->vlgrp) { rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; tctrl |= TCTRL_VLINS; } /* Init rctrl based on our settings */ gfar_write(®s->rctrl, rctrl); if(ndev->features & NETIF_F_IP_CSUM) { tctrl |= TCTRL_INIT_CSUM; } tctrl |= TCTRL_TXSCHED_WRRS; gfar_write(®s->tr03wt, WRRS_TR03WT); gfar_write(®s->tr47wt, WRRS_TR47WT); gfar_write(®s->tctrl, tctrl); /* Set the extraction length and index */ attrs = ATTRELI_EL(priv->rx_stash_size) | ATTRELI_EI(priv->rx_stash_index); gfar_write(®s->attreli, attrs); /* Start with defaults, and add stashing or locking * depending on the approprate variables */ attrs = ATTR_INIT_SETTINGS; if(priv->bd_stash_en) { attrs |= ATTR_BDSTASH; } if(priv->rx_stash_size != 0) { attrs |= ATTR_BUFSTASH; } gfar_write(®s->attr, attrs); } #ifdef CONFIG_GFAR_SW_PKT_STEERING DEFINE_PER_CPU(struct gfar_cpu_dev, gfar_cpu_dev); #endif static struct net_device_stats* gfar_get_stats(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct netdev_queue* txq; unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; unsigned long tx_packets = 0, tx_bytes = 0; int i = 0; for(i = 0; i < priv->num_rx_queues; i++) { rx_packets += priv->rx_queue[i]->stats.rx_packets; rx_bytes += priv->rx_queue[i]->stats.rx_bytes; rx_dropped += priv->rx_queue[i]->stats.rx_dropped; } dev->stats.rx_packets = rx_packets; dev->stats.rx_bytes = rx_bytes; dev->stats.rx_dropped = rx_dropped; for(i = 0; i < priv->num_tx_queues; i++) { txq = netdev_get_tx_queue(dev, i); tx_bytes += txq->tx_bytes; tx_packets += txq->tx_packets; } dev->stats.tx_bytes = tx_bytes; dev->stats.tx_packets = tx_packets; return &dev->stats; } static const struct net_device_ops gfar_netdev_ops = { .ndo_open = gfar_enet_open, .ndo_start_xmit = gfar_start_xmit, .ndo_stop = gfar_close, .ndo_change_mtu = gfar_change_mtu, .ndo_set_multicast_list = gfar_set_multi, .ndo_tx_timeout = gfar_timeout, .ndo_do_ioctl = gfar_ioctl, .ndo_get_stats = gfar_get_stats, .ndo_vlan_rx_register = gfar_vlan_rx_register, .ndo_set_mac_address = eth_mac_addr, .ndo_validate_addr = eth_validate_addr, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = gfar_netpoll, #endif #ifdef CONFIG_NET_GIANFAR_FP .ndo_accept_fastpath = gfar_accept_fastpath, #endif }; void lock_rx_qs(struct gfar_private* priv) { int i = 0x0; for(i = 0; i < priv->num_rx_queues; i++) { spin_lock(&priv->rx_queue[i]->rxlock); } } void lock_tx_qs(struct gfar_private* priv) { int i = 0x0; for(i = 0; i < priv->num_tx_queues; i++) { spin_lock(&priv->tx_queue[i]->txlock); } } void unlock_rx_qs(struct gfar_private* priv) { int i = 0x0; for(i = 0; i < priv->num_rx_queues; i++) { spin_unlock(&priv->rx_queue[i]->rxlock); } } void unlock_tx_qs(struct gfar_private* priv) { int i = 0x0; for(i = 0; i < priv->num_tx_queues; i++) { spin_unlock(&priv->tx_queue[i]->txlock); } } /* Returns 1 if incoming frames use an FCB */ static inline int gfar_uses_fcb(struct gfar_private* priv) { return priv->vlgrp || priv->rx_csum_enable; } static void free_tx_pointers(struct gfar_private* priv) { int i = 0; for(i = 0; i < priv->num_tx_queues; i++) { kfree(priv->tx_queue[i]); } } static void free_rx_pointers(struct gfar_private* priv) { int i = 0; for(i = 0; i < priv->num_rx_queues; i++) { kfree(priv->rx_queue[i]); } } static void unmap_group_regs(struct gfar_private* priv) { int i = 0; for(i = 0; i < MAXGROUPS; i++) if(priv->gfargrp[i].regs) { iounmap(priv->gfargrp[i].regs); } } static void disable_napi(struct gfar_private* priv) { int i = 0; #ifdef CONFIG_GIANFAR_TXNAPI #ifdef CONFIG_GFAR_SW_PKT_STEERING int j; int cpus = num_online_cpus(); #endif for(i = 0; i < priv->num_grps; i++) { #ifdef CONFIG_GFAR_SW_PKT_STEERING for(j = 0; j < cpus; j++) { napi_disable(&priv->gfargrp[i].napi_tx[j]); } #else napi_disable(&priv->gfargrp[i].napi_tx); #endif napi_disable(&priv->gfargrp[i].napi_rx); } #else for(i = 0; i < priv->num_grps; i++) { napi_disable(&priv->gfargrp[i].napi); } #endif } static void enable_napi(struct gfar_private* priv) { int i = 0; #ifdef CONFIG_GIANFAR_TXNAPI #ifdef CONFIG_GFAR_SW_PKT_STEERING int j; int cpus = num_online_cpus(); #endif for(i = 0; i < priv->num_grps; i++) { #ifdef CONFIG_GFAR_SW_PKT_STEERING for(j = 0; j < cpus; j++) { napi_enable(&priv->gfargrp[i].napi_tx[j]); } #else napi_enable(&priv->gfargrp[i].napi_tx); #endif napi_enable(&priv->gfargrp[i].napi_rx); } #else for(i = 0; i < priv->num_grps; i++) { napi_enable(&priv->gfargrp[i].napi); } #endif } static int gfar_parse_group(struct device_node* np, struct gfar_private* priv, const char* model) { u32* queue_mask; #ifdef CONFIG_GFAR_SW_PKT_STEERING int i; int cpus = num_online_cpus(); #endif priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0); if(!priv->gfargrp[priv->num_grps].regs) { return -ENOMEM; } priv->gfargrp[priv->num_grps].interruptTransmit = irq_of_parse_and_map(np, 0); /* If we aren't the FEC we have multiple interrupts */ if(model && strcasecmp(model, "FEC")) { priv->gfargrp[priv->num_grps].interruptReceive = irq_of_parse_and_map(np, 1); priv->gfargrp[priv->num_grps].interruptError = irq_of_parse_and_map(np, 2); if(priv->gfargrp[priv->num_grps].interruptTransmit < 0 || priv->gfargrp[priv->num_grps].interruptReceive < 0 || priv->gfargrp[priv->num_grps].interruptError < 0) { return -EINVAL; } } priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; priv->gfargrp[priv->num_grps].priv = priv; spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); if(priv->mode == MQ_MG_MODE) { queue_mask = (u32*)of_get_property(np, "rx-bit-map", NULL); priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); queue_mask = (u32*)of_get_property(np, "tx-bit-map", NULL); priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); } else { priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; } #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { /* register msg unit for virtual tx interrupt for each cpu */ for(i = 0; i < cpus; i++) /* for each cpu */ { priv->gfargrp[priv->num_grps].msg_virtual_tx[i] = fsl_get_msg_unit(); if(IS_ERR (priv->gfargrp[priv->num_grps].msg_virtual_tx[i])) { priv->sps = 0; printk(KERN_WARNING "%s: unable to allocate msg interrupt for pkt" "steering, error = %ld!\n", __func__, PTR_ERR(priv->gfargrp[priv->num_grps]. msg_virtual_tx[i])); } } } #endif priv->num_grps++; return 0; } static int gfar_of_init(struct of_device* ofdev, struct net_device** pdev) { const char* model; const char* ctype; const void* mac_addr; int err = 0, i, ret = 0; struct net_device* dev = NULL; struct gfar_private* priv = NULL; struct device_node* np = ofdev->dev.of_node; struct device_node* child = NULL; struct device_node* timer_node; const phandle* timer_handle; const u32* stash; const u32* stash_len; const u32* stash_idx; unsigned int num_tx_qs, num_rx_qs; u32* tx_queues, *rx_queues; u32* busFreq; u32 etsec_clk; u32 max_filer_rules; #ifdef CONFIG_GFAR_SW_PKT_STEERING int sps; #endif if(!np || !of_device_is_available(np)) { return -ENODEV; } /* parse the num of tx and rx queues */ tx_queues = (u32*)of_get_property(np, "fsl,num_tx_queues", NULL); num_tx_qs = tx_queues ? *tx_queues : 1; if(num_tx_qs > MAX_TX_QS) { printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", num_tx_qs, MAX_TX_QS); printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n"); return -EINVAL; } #ifdef CONFIG_GFAR_SW_PKT_STEERING if((num_online_cpus() == 2) && (!of_device_is_compatible(np, "fsl,etsec2"))) { printk(KERN_INFO "ETSEC: IPS Enabled\n"); num_tx_qs = num_online_cpus(); sps = 1; } #endif #ifdef CONFIG_RX_TX_BD_XNGE /* Creating multilple queues for avoiding lock in xmit function.*/ num_tx_qs = (num_tx_qs < 3) ? 3 : num_tx_qs; #endif rx_queues = (u32*)of_get_property(np, "fsl,num_rx_queues", NULL); num_rx_qs = rx_queues ? *rx_queues : 1; if(num_rx_qs > MAX_RX_QS) { printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", num_tx_qs, MAX_TX_QS); printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n"); return -EINVAL; } *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); dev = *pdev; if(NULL == dev) { return -ENOMEM; } priv = netdev_priv(dev); priv->node = ofdev->dev.of_node; priv->ndev = dev; #ifdef CONFIG_GFAR_SW_PKT_STEERING priv->sps = sps; #endif busFreq = (u32*)of_get_property (of_get_parent(np), "bus-frequency", NULL); if(busFreq) { /* etsec_clk is CCB/2 */ etsec_clk = *busFreq / 2; /* Divide by 1000000 to get freq in MHz */ etsec_clk /= 1000000; /* * eTSEC searches the table at a rate of two entries every * eTSEC clock cycle, so for the worst case all 256 entries * can be searched in the time taken to receive a 64-byte * Ethernet frame which comes out to be 672 ns at 1Gbps rate * including inter frame gap and preamble. * Hence max_filer_rules = etsec_clk * reception time for one * packet * 2. Divide by 1000 to match the units. */ max_filer_rules = etsec_clk * 672 * 2 / 1000; if(max_filer_rules > MAX_FILER_IDX) { priv->max_filer_rules = MAX_FILER_IDX; } else { priv->max_filer_rules = max_filer_rules; } } else { printk(KERN_INFO "Bus Frequency not found in DTS, " "setting max_filer_rules to %d\n", MAX_FILER_IDX); priv->max_filer_rules = MAX_FILER_IDX; } dev->num_tx_queues = num_tx_qs; dev->real_num_tx_queues = num_tx_qs; priv->num_tx_queues = num_tx_qs; priv->num_rx_queues = num_rx_qs; priv->num_grps = 0x0; model = of_get_property(np, "model", NULL); for(i = 0; i < MAXGROUPS; i++) { priv->gfargrp[i].regs = NULL; } /* Parse and initialize group specific information */ if(of_device_is_compatible(np, "fsl,etsec2")) { priv->mode = MQ_MG_MODE; for_each_child_of_node(np, child) { if(of_device_is_compatible (child, "fsl,etsec2-mdio") || of_device_is_compatible (child, "fsl,etsec2-tbi")) { continue; } err = gfar_parse_group(child, priv, model); if(err) { goto err_grp_init; } } } else { priv->mode = SQ_SG_MODE; err = gfar_parse_group(np, priv, model); if(err) { goto err_grp_init; } } for(i = 0; i < priv->num_tx_queues; i++) { priv->tx_queue[i] = NULL; } for(i = 0; i < priv->num_rx_queues; i++) { priv->rx_queue[i] = NULL; } for(i = 0; i < priv->num_tx_queues; i++) { priv->tx_queue[i] = (struct gfar_priv_tx_q*)kzalloc( sizeof(struct gfar_priv_tx_q), GFP_KERNEL); if(!priv->tx_queue[i]) { err = -ENOMEM; goto tx_alloc_failed; } priv->tx_queue[i]->tx_skbuff = NULL; priv->tx_queue[i]->qindex = i; priv->tx_queue[i]->dev = dev; spin_lock_init(&(priv->tx_queue[i]->txlock)); } for(i = 0; i < priv->num_rx_queues; i++) { priv->rx_queue[i] = (struct gfar_priv_rx_q*)kzalloc( sizeof(struct gfar_priv_rx_q), GFP_KERNEL); if(!priv->rx_queue[i]) { err = -ENOMEM; goto rx_alloc_failed; } priv->rx_queue[i]->rx_skbuff = NULL; priv->rx_queue[i]->qindex = i; priv->rx_queue[i]->dev = dev; spin_lock_init(&(priv->rx_queue[i]->rxlock)); } stash = of_get_property(np, "bd-stash", NULL); if(stash) { priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; priv->bd_stash_en = 1; } stash_len = of_get_property(np, "rx-stash-len", NULL); if(stash_len) { priv->rx_stash_size = *stash_len; } stash_idx = of_get_property(np, "rx-stash-idx", NULL); if(stash_idx) { priv->rx_stash_index = *stash_idx; } if(stash_len || stash_idx) { priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; } /* Handle IEEE1588 node */ timer_handle = of_get_property(np, "ptimer-handle", NULL); if(timer_handle) { timer_node = of_find_node_by_phandle(*timer_handle); if(timer_node) { ret = of_address_to_resource(timer_node, 0, &priv->timer_resource); if(!ret) { priv->ptimer_present = 1; printk(KERN_INFO "IEEE1588: ptp-timer device" "present in the system\n"); } } } else { printk(KERN_INFO "IEEE1588: disable on the system.\n"); } mac_addr = of_get_mac_address(np); if(mac_addr) { memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); } if(model && !strcasecmp(model, "TSEC")) priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | FSL_GIANFAR_DEV_HAS_MULTI_INTR; if(model && !strcasecmp(model, "eTSEC")) { priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | FSL_GIANFAR_DEV_HAS_MULTI_INTR | FSL_GIANFAR_DEV_HAS_PADDING | FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; #ifndef CONFIG_GFAR_SW_VLAN priv->device_flags |= FSL_GIANFAR_DEV_HAS_VLAN; #endif } ctype = of_get_property(np, "phy-connection-type", NULL); /* We only care about rgmii-id. The rest are autodetected */ if(ctype && !strcmp(ctype, "rgmii-id")) { priv->interface = PHY_INTERFACE_MODE_RGMII_ID; } else { priv->interface = PHY_INTERFACE_MODE_MII; } if(of_get_property(np, "fsl,magic-packet", NULL)) { priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; } if(of_get_property(np, "fsl,wake-on-filer", NULL)) { priv->device_flags |= FSL_GIANFAR_DEV_HAS_ARP_PACKET; } priv->phy_node = of_parse_phandle(np, "phy-handle", 0); /* Find the TBI PHY. If it's not there, we don't support SGMII */ priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); return 0; rx_alloc_failed: free_rx_pointers(priv); tx_alloc_failed: free_tx_pointers(priv); err_grp_init: unmap_group_regs(priv); free_netdev(dev); return err; } /* Ioctl MII Interface */ static int gfar_ioctl(struct net_device* dev, struct ifreq* rq, int cmd) { struct gfar_private* priv = netdev_priv(dev); int retVal = 0; if(!netif_running(dev)) { return -EINVAL; } if(!priv->phydev) { return -ENODEV; } if((cmd >= PTP_GET_RX_TIMESTAMP_SYNC) && (cmd <= PTP_CLEANUP_TIMESTAMP_BUFFERS)) { if(priv->ptimer_present) { retVal = gfar_ioctl_1588(dev, rq, cmd); } else { retVal = -ENODEV; } } else { retVal = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); } return retVal; } static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) { unsigned int new_bit_map = 0x0; int mask = 0x1 << (max_qs - 1), i; for(i = 0; i < max_qs; i++) { if(bit_map & mask) { new_bit_map = new_bit_map + (1 << i); } mask = mask >> 0x1; } return new_bit_map; } static u32 cluster_entry_per_class(struct gfar_private* priv, u32 rqfar, u32 class) { u32 rqfpr = FPR_FILER_MASK; u32 rqfcr = 0x0; rqfar--; rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; priv->ftp_rqfpr[rqfar] = rqfpr; priv->ftp_rqfcr[rqfar] = rqfcr; gfar_write_filer(priv, rqfar, rqfcr, rqfpr); rqfar--; rqfcr = RQFCR_CMP_NOMATCH; priv->ftp_rqfpr[rqfar] = rqfpr; priv->ftp_rqfcr[rqfar] = rqfcr; gfar_write_filer(priv, rqfar, rqfcr, rqfpr); rqfar--; rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; rqfpr = class; priv->ftp_rqfcr[rqfar] = rqfcr; priv->ftp_rqfpr[rqfar] = rqfpr; gfar_write_filer(priv, rqfar, rqfcr, rqfpr); rqfar--; rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; rqfpr = class; priv->ftp_rqfcr[rqfar] = rqfcr; priv->ftp_rqfpr[rqfar] = rqfpr; gfar_write_filer(priv, rqfar, rqfcr, rqfpr); return rqfar; } #ifdef CONFIG_GFAR_HW_TCP_RECEIVE_OFFLOAD void gfar_setup_hwaccel_tcp4_receive(struct sock* sk, struct sk_buff* skb) { int i = 0; int j = 0; u32 rqfcr = 0x0; u32 rqfpr = 0; struct tcphdr* th; struct iphdr* iph; struct gfar_private* priv = netdev_priv(skb->skb_owner); if(priv->ptimer_present || !priv->rx_csum_enable || priv->num_rx_queues < (TCP_CHL_OFFSET + RESERVE_CHL_NUM)) { return; } th = tcp_hdr(skb); iph = ip_hdr(skb); /*select next empty TCP channel*/ for(i = (priv->empty_tcp_channel + 1) % (priv->num_rx_queues - TCP_CHL_OFFSET - 1); i != priv->empty_tcp_channel; i = (i + 1) % (priv->num_rx_queues - TCP_CHL_OFFSET - 1)) { if(priv->tcp_hw_channel[i] == NULL) { break; } } if(i == priv->empty_tcp_channel) { i = (i + 1) % (priv->num_rx_queues - TCP_CHL_OFFSET - 1); } priv->tcp_hw_channel[priv->empty_tcp_channel] = sk; sk->tcp_hw_channel = &(priv->tcp_hw_channel[priv->empty_tcp_channel]); j = priv->tcp_filer_idx + (priv->empty_tcp_channel << 2); /*setup IPv4 source address*/ rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_SIA | RQFCR_AND; rqfpr = ntohl(iph->saddr); priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); j++; /*setup IPv4 destination address*/ rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_DIA | RQFCR_AND; rqfpr = ntohl(iph->daddr); priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); j++; /*setup TCP source port*/ rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_SPT | RQFCR_AND; rqfpr = ntohs(th->source); priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); j++; /*setup TCP destination port*/ rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_DPT | ((priv->empty_tcp_channel + TCP_CHL_OFFSET) << 10); rqfpr = ntohs(th->dest); priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); priv->empty_tcp_channel = i; /*clean up tcp channel*/ if(priv->tcp_hw_channel[i] != NULL) { priv->tcp_hw_channel[i]->tcp_hw_channel = NULL; priv->tcp_hw_channel[i] = NULL; j = priv->tcp_filer_idx + (i << 2); rqfcr = RQFCR_CMP_NOMATCH; rqfpr = FPR_FILER_MASK; priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); j++; priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); j++; priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); j++; priv->ftp_rqfcr[j] = rqfcr; priv->ftp_rqfpr[j] = rqfpr; gfar_write_filer(priv, j, rqfcr, rqfpr); } } inline void gfar_hwaccel_tcp4_receive(struct gfar_private* priv, struct gfar_priv_rx_q* rx_queue, struct sk_buff* skb, int amount_pull) { const struct tcphdr* th; const struct iphdr* iph; int p_len; int ph_len; struct rxfcb* fcb; struct sock* gfar_sk; gfar_sk = priv->tcp_hw_channel[rx_queue->qindex - TCP_CHL_OFFSET]; fcb = (struct rxfcb*)skb->data; gfar_rx_checksum(skb, fcb); skb->pkt_type = PACKET_HOST; /*set IPv4 header*/ skb->network_header = skb->data + amount_pull + ETH_HLEN; iph = ip_hdr(skb); if(iph->ihl > 5 || (iph->frag_off & htons(IP_MF | IP_OFFSET)) || (gfar_sk->sk_state != TCP_ESTABLISHED)) { gfar_process_frame(priv->ndev, skb, amount_pull); return; } /*IPv4 header length*/ ph_len = iph->ihl << 2; p_len = ntohs(iph->tot_len); if(p_len < (skb->len - amount_pull - ETH_HLEN)) { skb->tail = skb->tail - ((skb->len - amount_pull - ETH_HLEN) - p_len); skb->len = p_len - ph_len; } else { skb->len = skb->len - (amount_pull + ETH_HLEN + ph_len); } /*set TCP header*/ skb->transport_header = skb->network_header + ph_len; skb->data = skb->transport_header; th = tcp_hdr(skb); TCP_SKB_CB(skb)->seq = ntohl(th->seq); TCP_SKB_CB(skb)->end_seq = (TCP_SKB_CB(skb)->seq + th->syn + th->fin + skb->len - (th->doff << 2)); TCP_SKB_CB(skb)->ack_seq = ntohl(th->ack_seq); TCP_SKB_CB(skb)->when = 0; TCP_SKB_CB(skb)->flags = iph->tos; TCP_SKB_CB(skb)->sacked = 0; bh_lock_sock(gfar_sk); if(!sock_owned_by_user(gfar_sk)) { if(tcp_rcv_established(gfar_sk, skb, tcp_hdr(skb), skb->len)) { tcp_v4_send_reset(gfar_sk, skb); kfree_skb(skb); } } else { sk_add_backlog(gfar_sk, skb); } bh_unlock_sock(gfar_sk); } void gfar_init_tcp_filer_rule(struct gfar_private* priv, int index) { int i; int j = 0; u32 rqfcr = 0x0; u32 rqfpr = FPR_FILER_MASK; i = index - 4 - (TCP_CHL_NUM << 2); if(i < 0) { return; } printk(KERN_INFO "%s: enabled hardware TCP receive offload\n", priv->ndev->name); rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; rqfpr = RQFPR_IPV4 | RQFPR_TCP; priv->ftp_rqfcr[i] = rqfcr; priv->ftp_rqfpr[i] = rqfpr; gfar_write_filer(priv, i, rqfcr, rqfpr); i++; rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_AND; rqfpr = RQFPR_IPV4 | RQFPR_TCP; priv->ftp_rqfcr[i] = rqfcr; priv->ftp_rqfpr[i] = rqfpr; gfar_write_filer(priv, i, rqfcr, rqfpr); i++; rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_CLE | RQFCR_AND; rqfpr = FPR_FILER_MASK; priv->ftp_rqfcr[i] = rqfcr; priv->ftp_rqfpr[i] = rqfpr; gfar_write_filer(priv, i, rqfcr, rqfpr); i++; rqfcr = RQFCR_CMP_NOMATCH; rqfpr = FPR_FILER_MASK; priv->tcp_filer_idx = i; priv->empty_tcp_channel = 1; for(j = 0; j < (TCP_CHL_NUM << 2); j++) { priv->ftp_rqfcr[i] = rqfcr; priv->ftp_rqfpr[i] = rqfpr; gfar_write_filer(priv, i, rqfcr, rqfpr); i++; } for(j = 0; j < TCP_CHL_NUM; j++) { priv->tcp_hw_channel[j] = 0; } rqfpr = FPR_FILER_MASK; rqfcr = RQFCR_CMP_NOMATCH | RQFCR_CLE; priv->ftp_rqfcr[i] = rqfcr; priv->ftp_rqfpr[i] = rqfpr; gfar_write_filer(priv, i, rqfcr, rqfpr); } #endif static void gfar_init_filer_table(struct gfar_private* priv) { int i = 0x0; u32 rqfar = priv->max_filer_rules; u32 rqfcr = 0x0; u32 rqfpr = FPR_FILER_MASK; if(!priv->ftp_rqfpr) { priv->ftp_rqfpr = kmalloc((priv->max_filer_rules + 1) * sizeof (u32), GFP_KERNEL); if(!priv->ftp_rqfpr) { pr_err("Could not allocate ftp_rqfpr\n"); goto out; } } if(!priv->ftp_rqfcr) { priv->ftp_rqfcr = kmalloc((priv->max_filer_rules + 1) * sizeof (u32), GFP_KERNEL); if(!priv->ftp_rqfcr) { pr_err("Could not allocate ftp_rqfcr\n"); goto out; } } /* Default rule */ rqfcr = RQFCR_CMP_MATCH; priv->ftp_rqfcr[rqfar] = rqfcr; priv->ftp_rqfpr[rqfar] = rqfpr; gfar_write_filer(priv, rqfar, rqfcr, rqfpr); rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); #ifdef CONFIG_GFAR_HW_TCP_RECEIVE_OFFLOAD /*init TCP filer rule table*/ gfar_init_tcp_filer_rule(priv, rqfar); /* cur_filer_idx indicated the fisrt non-masked rule */ priv->cur_filer_idx = priv->tcp_filer_idx - 3; /* Program the RIR0 reg with the required distribution */ priv->gfargrp[0].regs->rir0 = TWO_QUEUE_RIR0; #else /* cur_filer_idx indicated the fisrt non-masked rule */ priv->cur_filer_idx = rqfar; /* Program the RIR0 reg with the required distribution */ priv->gfargrp[0].regs->rir0 = DEFAULT_RIR0; #endif /* Rest are masked rules */ rqfcr = RQFCR_CMP_NOMATCH; for(i = 0; i < rqfar; i++) { priv->ftp_rqfcr[i] = rqfcr; priv->ftp_rqfpr[i] = rqfpr; gfar_write_filer(priv, i, rqfcr, rqfpr); } return; out: kfree(priv->ftp_rqfcr); kfree(priv->ftp_rqfpr); priv->ftp_rqfpr = priv->ftp_rqfcr = NULL; } static int get_cpu_number(unsigned char* eth_pkt, int len) { u32 addr1, addr2, ports; struct ipv6hdr* ip6; struct iphdr* ip; u32 hash, ihl; u8 ip_proto; int cpu; struct ethhdr* eth; static u32 simple_hashrnd; static int simple_hashrnd_initialized; if(len < ETH_HLEN) { return -1; } else { eth = eth_pkt; } if(unlikely(!simple_hashrnd_initialized)) { get_random_bytes(&simple_hashrnd, 4); simple_hashrnd_initialized = 1; } switch(eth->h_proto) { case __constant_htons(ETH_P_IP): if(len < (ETH_HLEN + sizeof(*ip))) { return -1; } ip = (struct iphdr*)(eth_pkt + ETH_HLEN); ip_proto = ip->protocol; addr1 = ip->saddr; addr2 = ip->daddr; ihl = ip->ihl; break; case __constant_htons(ETH_P_IPV6): if(len < (ETH_HLEN + sizeof(*ip6))) { return -1; } ip6 = (struct ipv6hdr*)(eth_pkt + ETH_HLEN); ip_proto = ip6->nexthdr; addr1 = ip6->saddr.s6_addr32[3]; addr2 = ip6->daddr.s6_addr32[3]; ihl = (40 >> 2); break; default: return -1; } ports = 0; switch(ip_proto) { case IPPROTO_TCP: case IPPROTO_UDP: case IPPROTO_DCCP: case IPPROTO_ESP: case IPPROTO_SCTP: case IPPROTO_UDPLITE: if(len >= (ETH_HLEN + (ihl * 4) + 4)) { ports = *((u32*)(eth_pkt + ETH_HLEN + (ihl * 4))); } break; case IPPROTO_AH: if(len >= (ETH_HLEN + (ihl * 4) + 4)) { ports = *((u32*)(eth_pkt + ETH_HLEN + (ihl * 4) + 4)); } break; default: break; } hash = jhash_3words(addr1, addr2, ports, simple_hashrnd); cpu = hash & 0x1; return cpu_online(cpu) ? cpu : -1; } #ifdef CONFIG_GFAR_SW_PKT_STEERING static int gfar_cpu_poll(struct napi_struct* napi, int budget) { struct gfar_cpu_dev* cpu_dev = &__get_cpu_var(gfar_cpu_dev); struct sk_buff* skb = NULL, *new_recycle_head = NULL; int cpu = smp_processor_id(); int rx_cleaned = 0; struct net_device* dev; struct gfar_private* priv; int amount_pull; struct shared_buffer* buf = &per_cpu(gfar_cpu_dev, !cpu).tx_queue; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING struct gfar_skb_handler* sh = &cpu_dev->sh; #endif while(budget--) { smp_rmb(); spin_lock_irq(&buf->lock); if(buf->buff_cnt == 0) { spin_unlock_irq(&buf->lock); break; } else { skb = buf->buffer[buf->out]; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING if(sh->recycle_count > 0) { new_recycle_head = sh->recycle_queue->next; buf->buffer[buf->out] = sh->recycle_queue; sh->recycle_queue->next = NULL; sh->recycle_queue = new_recycle_head; sh->recycle_count--; } else { buf->buffer[buf->out] = NULL; } #endif buf->out = (buf->out + 1) % GFAR_CPU_BUFF_SIZE; buf->buff_cnt--; spin_unlock_irq(&buf->lock); dev = skb->dev; priv = netdev_priv(dev); if(priv->ptimer_present) amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); else amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + priv->padding; gfar_process_frame(dev, skb, amount_pull); rx_cleaned++; } } if(budget > 0) { napi_complete(napi); } return rx_cleaned; } static irqreturn_t gfar_cpu_receive(int irq, void* dev_id) { unsigned long flags; struct gfar_cpu_dev* cpu_dev = &__get_cpu_var(gfar_cpu_dev); /* clear the interrupt by reading message */ fsl_clear_msg(cpu_dev->msg_virtual_rx); local_irq_save(flags); if(napi_schedule_prep(&cpu_dev->napi)) { __napi_schedule(&cpu_dev->napi); } local_irq_restore(flags); return IRQ_HANDLED; } void gfar_cpu_setup(struct net_device* dev) { return; } static enum hrtimer_restart gfar_cpu_timer_handle(struct hrtimer* timer) { struct gfar_cpu_dev* this_cpu_dev = &__get_cpu_var(gfar_cpu_dev); struct gfar_cpu_dev* other_cpu_dev = &per_cpu(gfar_cpu_dev, !smp_processor_id()); if(timer == &this_cpu_dev->intr_coalesce_timer) { fsl_send_msg(other_cpu_dev->msg_virtual_rx, 0x1); this_cpu_dev->intr_coalesce_cnt = 0; } else { fsl_send_msg(this_cpu_dev->msg_virtual_rx, 0x1); other_cpu_dev->intr_coalesce_cnt = 0; } return HRTIMER_NORESTART; } void gfar_cpu_dev_init(void) { int err = -1; int i = 0; int j; struct gfar_cpu_dev* cpu_dev; struct cpumask cpumask_msg_intrs; for_each_possible_cpu(i) { cpu_dev = &per_cpu(gfar_cpu_dev, i); cpu_dev->enabled = 0; init_dummy_netdev(&cpu_dev->dev); spin_lock_init(&cpu_dev->tx_queue.lock); netif_napi_add(&cpu_dev->dev, &cpu_dev->napi, gfar_cpu_poll, GFAR_DEV_WEIGHT); cpu_dev->msg_virtual_rx = fsl_get_msg_unit(); if(IS_ERR(cpu_dev->msg_virtual_rx)) { printk(KERN_WARNING "%s: fsl_get_msg_unit returned error %ld!\n", __func__, IS_ERR(cpu_dev->msg_virtual_rx)); goto msg_fail; } sprintf(cpu_dev->int_name, "cpu%d_vrx", i); err = request_irq(cpu_dev->msg_virtual_rx->irq, gfar_cpu_receive, 0, cpu_dev->int_name, NULL); if(err < 0) { printk(KERN_WARNING "Can't request msg IRQ %d\n", cpu_dev->msg_virtual_rx->irq); goto irq_fail; } cpumask_clear(&cpumask_msg_intrs); cpumask_set_cpu(i, &cpumask_msg_intrs); irq_set_affinity(cpu_dev->msg_virtual_rx->irq, &cpumask_msg_intrs); fsl_enable_msg(cpu_dev->msg_virtual_rx); for(j = 0; j < GFAR_CPU_BUFF_SIZE; j++) { cpu_dev->tx_queue.buffer[j] = NULL; } cpu_dev->tx_queue.in = 0; cpu_dev->tx_queue.out = 0; cpu_dev->tx_queue.buff_cnt = 0; napi_enable(&cpu_dev->napi); cpu_dev->intr_coalesce_cnt = 0; hrtimer_init(&cpu_dev->intr_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); cpu_dev->intr_coalesce_timer.function = gfar_cpu_timer_handle; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING gfar_reset_skb_handler(&cpu_dev->sh); #endif cpu_dev->enabled = 1; } return; irq_fail: fsl_release_msg_unit(cpu_dev->msg_virtual_rx); msg_fail: netif_napi_del(&cpu_dev->napi); for(j = 0; j < i; j++) { cpu_dev = &per_cpu(gfar_cpu_dev, j); cpu_dev->enabled = 0; napi_disable(&cpu_dev->napi); free_irq(cpu_dev->msg_virtual_rx->irq, NULL); fsl_release_msg_unit(cpu_dev->msg_virtual_rx); netif_napi_del(&cpu_dev->napi); } } void gfar_cpu_dev_exit(void) { int i = 0; struct gfar_cpu_dev* cpu_dev; for_each_possible_cpu(i) { cpu_dev = &per_cpu(gfar_cpu_dev, i); hrtimer_cancel(&cpu_dev->intr_coalesce_timer); napi_disable(&cpu_dev->napi); free_irq(cpu_dev->msg_virtual_rx->irq, NULL); fsl_release_msg_unit(cpu_dev->msg_virtual_rx); netif_napi_del(&cpu_dev->napi); } } int distribute_packet(struct net_device* dev, struct sk_buff* skb, int amount_pull) { struct gfar_private* priv = netdev_priv(dev); struct gfar_cpu_dev* cpu_dev; int target_cpu; int current_cpu = smp_processor_id(); unsigned char* skb_data; unsigned int skb_len; unsigned int eth_hdr_offset = 0; unsigned char* eth; struct shared_buffer* buf; ktime_t time; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING struct gfar_skb_handler* sh; struct sk_buff* new_skb; #endif skb_data = skb->data; skb_len = skb->len; if(amount_pull) { eth_hdr_offset += amount_pull; } if(priv->ptimer_present) { eth_hdr_offset += 8; } if(eth_hdr_offset > skb_len) { return -1; } eth = skb_data + eth_hdr_offset; target_cpu = get_cpu_number(eth, skb_len - eth_hdr_offset); if(-1 == target_cpu) { return -1; } if(target_cpu == current_cpu) { return -1; } cpu_dev = &__get_cpu_var(gfar_cpu_dev); if(!cpu_dev->enabled) { return -1; } buf = &cpu_dev->tx_queue; spin_lock_irq(&buf->lock); if(buf->buff_cnt == (GFAR_CPU_BUFF_SIZE - 1)) { dev_kfree_skb_any(skb); /* buffer full, drop packet */ spin_unlock_irq(&buf->lock); return 0; } #ifdef CONFIG_GFAR_SKBUFF_RECYCLING sh = &cpu_dev->sh; if(sh->recycle_count < sh->recycle_max) { if(buf->buffer[buf->in] != NULL) { new_skb = buf->buffer[buf->in]; } else { new_skb = gfar_new_skb(dev); } /* put the obtained/allocated skb into current cpu's recycle buffer */ if(new_skb) { new_skb->next = sh->recycle_queue; sh->recycle_queue = new_skb; sh->recycle_count++; } } #endif /* inform other cpu which dev this skb was received on */ skb->dev = dev; buf->buffer[buf->in] = skb; buf->in = (buf->in + 1) % GFAR_CPU_BUFF_SIZE; smp_wmb(); buf->buff_cnt++; spin_unlock_irq(&buf->lock); /* raise other core's msg intr */ if(0 == cpu_dev->intr_coalesce_cnt++) { time = ktime_set(0, 0); time = ktime_add_ns(time, INTR_COALESCE_TIMEOUT); hrtimer_start(&cpu_dev->intr_coalesce_timer, time, HRTIMER_MODE_ABS); } else { if(cpu_dev->intr_coalesce_cnt == INTR_COALESCE_CNT) { cpu_dev->intr_coalesce_cnt = 0; hrtimer_cancel(&cpu_dev->intr_coalesce_timer); fsl_send_msg(per_cpu (gfar_cpu_dev, target_cpu).msg_virtual_rx, 0x1); } } return 0; } static irqreturn_t gfar_virtual_transmit(int irq, void* grp_id) { unsigned long flags; int cpu = smp_processor_id(); struct gfar_priv_grp* grp = (struct gfar_priv_grp*)grp_id; int cpus = num_online_cpus(); int i; for(i = 0; i < cpus; i++) /* clear the interrupt */ /* although only one virtual tx intr is enabled at a time, * we are clearing virtual tx intr of all cpus, to ensure * this intr is cleared even if user sets wrong affinity */ { fsl_clear_msg(grp->msg_virtual_tx[i]); } local_irq_save(flags); if(napi_schedule_prep(&grp->napi_tx[cpu])) { __napi_schedule(&grp->napi_tx[cpu]); } local_irq_restore(flags); return IRQ_HANDLED; } #endif /* Set up the ethernet device structure, private data, * and anything else we need before we start */ static int gfar_probe(struct of_device* ofdev, const struct of_device_id* match) { u32 tempval; struct net_device* dev = NULL; struct gfar_private* priv = NULL; struct gfar __iomem* regs = NULL; int err = 0, i, grp_idx = 0; int len_devname; u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; u32 isrg = 0; u32 __iomem* baddr; #ifdef CONFIG_GFAR_SW_PKT_STEERING int j; int cpus = num_online_cpus(); #endif err = gfar_of_init(ofdev, &dev); if(err) { return err; } priv = netdev_priv(dev); priv->ndev = dev; priv->ofdev = ofdev; priv->node = ofdev->dev.of_node; SET_NETDEV_DEV(dev, &ofdev->dev); if(priv->ptimer_present) { err = gfar_ptp_init(priv); if(err) { priv->ptimer_present = 0; printk(KERN_ERR "IEEE1588: ptp-timer init failed\n"); } priv->rx_filer_enable = 1; pmuxcr_guts_write(); printk(KERN_INFO "IEEE1588: ptp-timer initialized\n"); } spin_lock_init(&priv->bflock); INIT_WORK(&priv->reset_task, gfar_reset_task); dev_set_drvdata(&ofdev->dev, priv); regs = priv->gfargrp[0].regs; /* Stop the DMA engine now, in case it was running before */ /* (The firmware could have used it, and left it running). */ gfar_halt(dev); /* Reset MAC layer */ gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); /* We need to delay at least 3 TX clocks */ udelay(2); tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); gfar_write(®s->maccfg1, tempval); /* Initialize MACCFG2. */ gfar_write(®s->maccfg2, MACCFG2_INIT_SETTINGS); /* Initialize ECNTRL */ gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); /* Set the dev->base_addr to the gfar reg region */ dev->base_addr = (unsigned long) regs; SET_NETDEV_DEV(dev, &ofdev->dev); /* Fill in the dev structure */ dev->watchdog_timeo = TX_TIMEOUT; dev->mtu = 1500; dev->netdev_ops = &gfar_netdev_ops; dev->ethtool_ops = &gfar_ethtool_ops; #ifdef CONFIG_GIANFAR_TXNAPI /* Seperate napi for tx and rx for each group */ for(i = 0; i < priv->num_grps; i++) { #ifdef CONFIG_GFAR_SW_PKT_STEERING for(j = 0; j < cpus; j++) netif_napi_add(dev, &priv->gfargrp[i].napi_tx[j], #else netif_napi_add(dev, &priv->gfargrp[i].napi_tx, #endif gfar_poll_tx, GFAR_DEV_WEIGHT); netif_napi_add(dev, &priv->gfargrp[i].napi_rx, gfar_poll_rx, GFAR_DEV_WEIGHT); } #else /* Register for napi ...We are registering NAPI for each grp */ for(i = 0; i < priv->num_grps; i++) { netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT); } #endif if(priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { priv->rx_csum_enable = 1; dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; } else { priv->rx_csum_enable = 0; } priv->vlgrp = NULL; if(priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; } if(priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { priv->extended_hash = 1; priv->hash_width = 9; priv->hash_regs[0] = ®s->igaddr0; priv->hash_regs[1] = ®s->igaddr1; priv->hash_regs[2] = ®s->igaddr2; priv->hash_regs[3] = ®s->igaddr3; priv->hash_regs[4] = ®s->igaddr4; priv->hash_regs[5] = ®s->igaddr5; priv->hash_regs[6] = ®s->igaddr6; priv->hash_regs[7] = ®s->igaddr7; priv->hash_regs[8] = ®s->gaddr0; priv->hash_regs[9] = ®s->gaddr1; priv->hash_regs[10] = ®s->gaddr2; priv->hash_regs[11] = ®s->gaddr3; priv->hash_regs[12] = ®s->gaddr4; priv->hash_regs[13] = ®s->gaddr5; priv->hash_regs[14] = ®s->gaddr6; priv->hash_regs[15] = ®s->gaddr7; } else { priv->extended_hash = 0; priv->hash_width = 8; priv->hash_regs[0] = ®s->gaddr0; priv->hash_regs[1] = ®s->gaddr1; priv->hash_regs[2] = ®s->gaddr2; priv->hash_regs[3] = ®s->gaddr3; priv->hash_regs[4] = ®s->gaddr4; priv->hash_regs[5] = ®s->gaddr5; priv->hash_regs[6] = ®s->gaddr6; priv->hash_regs[7] = ®s->gaddr7; } if(priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) { priv->padding = DEFAULT_PADDING; } else { priv->padding = 0; } if(dev->features & NETIF_F_IP_CSUM || priv->ptimer_present) { priv->padding = 0x8; dev->hard_header_len += GMAC_FCB_LEN; } /* Program the isrg regs only if number of grps > 1 */ if(priv->num_grps > 1) { baddr = ®s->isrg0; for(i = 0; i < priv->num_grps; i++) { isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); gfar_write(baddr, isrg); baddr++; isrg = 0x0; } } /* Need to reverse the bit maps as bit_map's MSB is q0 * but, for_each_set_bit parses from right to left, which * basically reverses the queue numbers */ for(i = 0; i < priv->num_grps; i++) { priv->gfargrp[i].tx_bit_map = reverse_bitmap( priv->gfargrp[i].tx_bit_map, MAX_TX_QS); priv->gfargrp[i].rx_bit_map = reverse_bitmap( priv->gfargrp[i].rx_bit_map, MAX_RX_QS); } /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, * also assign queues to groups */ for(grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { priv->gfargrp[grp_idx].num_rx_queues = 0x0; for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, priv->num_rx_queues) { priv->gfargrp[grp_idx].num_rx_queues++; priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; rstat = rstat | (RSTAT_CLEAR_RHALT >> i); rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); } priv->gfargrp[grp_idx].num_tx_queues = 0x0; for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, priv->num_tx_queues) { priv->gfargrp[grp_idx].num_tx_queues++; priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; tstat = tstat | (TSTAT_CLEAR_THALT >> i); tqueue = tqueue | (TQUEUE_EN0 >> i); } priv->gfargrp[grp_idx].rstat = rstat; priv->gfargrp[grp_idx].tstat = tstat; rstat = tstat = 0; } gfar_write(®s->rqueue, rqueue); gfar_write(®s->tqueue, tqueue); priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; priv->wk_buffer_size = DEFAULT_WK_BUFFER_SIZE; /* Initializing some of the rx/tx queue level parameters */ for(i = 0; i < priv->num_tx_queues; i++) { if(i == 0) { priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE * 16; } else { priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; } priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; priv->tx_queue[i]->txic = DEFAULT_TXIC; } priv->rx_queue[priv->num_rx_queues - 1]->rx_ring_size = DEFAULT_WK_RING_SIZE; /* enable filer if using multiple RX queues*/ if(priv->num_rx_queues > 1) { priv->rx_filer_enable = 1; } for(i = 0; i < priv->num_rx_queues; i++) { if(i == 0) { priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE * 16; } else { priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; } priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; priv->rx_queue[i]->rxic = DEFAULT_RXIC; } /* Enable most messages by default */ priv->msg_enable = (NETIF_MSG_IFUP << 1) - 1; /* Carrier starts down, phylib will bring it up */ netif_carrier_off(dev); err = register_netdev(dev); if(err) { printk(KERN_ERR "%s: Cannot register net device, aborting.\n", dev->name); goto register_fail; } if((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) || (priv->device_flags & FSL_GIANFAR_DEV_HAS_ARP_PACKET)) { device_set_wakeup_capable(&ofdev->dev, true); device_set_wakeup_enable(&ofdev->dev, false); } /* fill out IRQ number and name fields */ len_devname = strlen(dev->name); for(i = 0; i < priv->num_grps; i++) { strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name, len_devname); if(priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { strncpy(&priv->gfargrp[i].int_name_tx[len_devname], "_g", sizeof("_g")); priv->gfargrp[i].int_name_tx[ strlen(priv->gfargrp[i].int_name_tx)] = i + 48; strncpy(&priv->gfargrp[i].int_name_tx[strlen( priv->gfargrp[i].int_name_tx)], "_tx", sizeof("_tx") + 1); strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name, len_devname); strncpy(&priv->gfargrp[i].int_name_rx[len_devname], "_g", sizeof("_g")); priv->gfargrp[i].int_name_rx[ strlen(priv->gfargrp[i].int_name_rx)] = i + 48; strncpy(&priv->gfargrp[i].int_name_rx[strlen( priv->gfargrp[i].int_name_rx)], "_rx", sizeof("_rx") + 1); strncpy(&priv->gfargrp[i].int_name_er[0], dev->name, len_devname); strncpy(&priv->gfargrp[i].int_name_er[len_devname], "_g", sizeof("_g")); priv->gfargrp[i].int_name_er[strlen( priv->gfargrp[i].int_name_er)] = i + 48; strncpy(&priv->gfargrp[i].int_name_er[strlen(\ priv->gfargrp[i].int_name_er)], "_er", sizeof("_er") + 1); } else { priv->gfargrp[i].int_name_tx[len_devname] = '\0'; } } /* Initialize the filer table */ gfar_init_filer_table(priv); /* Create all the sysfs files */ gfar_init_sysfs(dev); /* Print out the device info */ printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); /* Even more device info helps when determining which kernel */ /* provided which set of benchmarks. */ printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); for(i = 0; i < priv->num_rx_queues; i++) printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n", dev->name, i, priv->rx_queue[i]->rx_ring_size); for(i = 0; i < priv->num_tx_queues; i++) printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n", dev->name, i, priv->tx_queue[i]->tx_ring_size); return 0; register_fail: if(priv->ptimer_present) { gfar_ptp_cleanup(priv); } unmap_group_regs(priv); free_tx_pointers(priv); free_rx_pointers(priv); if(priv->phy_node) { of_node_put(priv->phy_node); } if(priv->tbi_node) { of_node_put(priv->tbi_node); } free_netdev(dev); return err; } static int gfar_remove(struct of_device* ofdev) { struct gfar_private* priv = dev_get_drvdata(&ofdev->dev); if(priv->phy_node) { of_node_put(priv->phy_node); } if(priv->tbi_node) { of_node_put(priv->tbi_node); } dev_set_drvdata(&ofdev->dev, NULL); unregister_netdev(priv->ndev); unmap_group_regs(priv); kfree(priv->ftp_rqfpr); kfree(priv->ftp_rqfcr); free_netdev(priv->ndev); return 0; } #ifdef CONFIG_PM static void gfar_enable_filer(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 temp; lock_rx_qs(priv); temp = gfar_read(®s->rctrl); temp |= RCTRL_FILREN; temp &= ~RCTRL_FSQEN; temp &= ~RCTRL_PRSDEP_MASK; temp |= RCTRL_PRSDEP_L2L3; gfar_write(®s->rctrl, temp); unlock_rx_qs(priv); } static int gfar_get_ip(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct in_device* in_dev = (struct in_device*)dev->ip_ptr; struct in_ifaddr* ifa; if(in_dev != NULL) { ifa = (struct in_ifaddr*)in_dev->ifa_list; if(ifa != NULL) { memcpy(priv->ip_addr, &ifa->ifa_address, 4); return 0; } } return -ENOENT; } static void gfar_config_filer_table(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); u8* ip_addr; u32 wakeup_ip, dest_mac_addr_h, dest_mac_addr_l; u32 rqfpr = 0x0; u32 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH; u8 rqfcr_queue = priv->num_rx_queues - 1; int i; if(gfar_get_ip(dev)) { printk(KERN_ERR "WOL: get the ip address error\n"); } ip_addr = priv->ip_addr; wakeup_ip = (*ip_addr << 24) | (*(ip_addr + 1) << 16) | \ (*(ip_addr + 2) << 8) | (*(ip_addr + 3)); dest_mac_addr_h = (dev->dev_addr[0] << 16) | \ (dev->dev_addr[1] << 8) | dev->dev_addr[2]; dest_mac_addr_l = (dev->dev_addr[3] << 16) | \ (dev->dev_addr[4] << 8) | dev->dev_addr[5]; lock_rx_qs(priv); for(i = 0; i <= priv->max_filer_rules; i++) { gfar_write_filer(priv, i, rqfcr, rqfpr); } /* ARP request filer, filling the packet to queue #1 */ rqfcr = (rqfcr_queue << 10) | RQFCR_AND | RQFCR_CMP_EXACT | RQFCR_PID_MASK; rqfpr = RQFPR_ARQ; gfar_write_filer(priv, 0, rqfcr, rqfpr); rqfcr = (rqfcr_queue << 10) | RQFCR_AND | RQFCR_CMP_EXACT | RQFCR_PID_PARSE; rqfpr = RQFPR_ARQ; gfar_write_filer(priv, 1, rqfcr, rqfpr); /* DEST_IP address in ARP packet, filling it to queue #1 */ rqfcr = (rqfcr_queue << 10) | RQFCR_AND | RQFCR_CMP_EXACT | RQFCR_PID_MASK; rqfpr = FPR_FILER_MASK; gfar_write_filer(priv, 2, rqfcr, rqfpr); rqfcr = RQFCR_GPI | (rqfcr_queue << 10) | RQFCR_CMP_EXACT | RQFCR_PID_DIA; rqfpr = wakeup_ip; gfar_write_filer(priv, 3, rqfcr, rqfpr); /* Unicast packet, filling it to queue #1 */ rqfcr = (rqfcr_queue << 10) | RQFCR_AND | RQFCR_CMP_EXACT | RQFCR_PID_DAH; rqfpr = dest_mac_addr_h; gfar_write_filer(priv, 4, rqfcr, rqfpr); rqfcr = RQFCR_GPI | (rqfcr_queue << 10) | RQFCR_CMP_EXACT | RQFCR_PID_DAL; mb(); rqfpr = dest_mac_addr_l; gfar_write_filer(priv, 5, rqfcr, rqfpr); unlock_rx_qs(priv); } static int gfar_arp_suspend(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; unsigned long flags; u32 tempval; netif_device_detach(dev); if(netif_running(dev)) { local_irq_save(flags); lock_tx_qs(priv); lock_rx_qs(priv); gfar_halt_tx_nodisable(dev); /* Disable Tx */ tempval = gfar_read(®s->maccfg1); tempval &= ~MACCFG1_TX_EN; gfar_write(®s->maccfg1, tempval); unlock_rx_qs(priv); unlock_tx_qs(priv); local_irq_restore(flags); disable_napi(priv); gfar_halt_rx(dev); gfar_config_filer_table(dev); gfar_enable_filer(dev); gfar_rx_start(dev); } return 0; } static int gfar_suspend(struct device* dev) { struct gfar_private* priv = dev_get_drvdata(dev); struct net_device* ndev = priv->ndev; struct gfar __iomem* regs = priv->gfargrp[0].regs; unsigned long flags; u32 tempval; int magic_packet = priv->wol_en && (priv->wol_opts & GIANFAR_WOL_MAGIC) && (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); int arp_packet = priv->wol_en && (priv->wol_opts & GIANFAR_WOL_ARP) && (priv->device_flags & FSL_GIANFAR_DEV_HAS_ARP_PACKET); if(arp_packet) { pmc_enable_wake(priv->ofdev, PM_SUSPEND_MEM, 1); pmc_enable_lossless(1); gfar_arp_suspend(ndev); return 0; } netif_device_detach(ndev); if(netif_running(ndev)) { local_irq_save(flags); lock_tx_qs(priv); lock_rx_qs(priv); gfar_halt_nodisable(ndev); /* Disable Tx, and Rx if wake-on-LAN is disabled. */ tempval = gfar_read(®s->maccfg1); tempval &= ~MACCFG1_TX_EN; if(!magic_packet) { tempval &= ~MACCFG1_RX_EN; } gfar_write(®s->maccfg1, tempval); unlock_rx_qs(priv); unlock_tx_qs(priv); local_irq_restore(flags); disable_napi(priv); if(magic_packet) { pmc_enable_wake(priv->ofdev, PM_SUSPEND_MEM, 1); /* Enable interrupt on Magic Packet */ gfar_write(®s->imask, IMASK_MAG); /* Enable Magic Packet mode */ tempval = gfar_read(®s->maccfg2); tempval |= MACCFG2_MPEN; gfar_write(®s->maccfg2, tempval); } else { phy_stop(priv->phydev); } } return 0; } static int gfar_arp_resume(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); if(!netif_running(dev)) { netif_device_attach(dev); return 0; } gfar_tx_start(dev); stop_gfar(dev); gfar_halt_rx(dev); gfar_init_filer_table(priv); startup_gfar(dev); gfar_rx_start(dev); netif_device_attach(dev); enable_napi(priv); return 0; } static int gfar_resume(struct device* dev) { struct gfar_private* priv = dev_get_drvdata(dev); struct net_device* ndev = priv->ndev; struct gfar __iomem* regs = priv->gfargrp[0].regs; unsigned long flags; u32 tempval; int magic_packet = priv->wol_en && (priv->wol_opts & GIANFAR_WOL_MAGIC) && (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); int arp_packet = priv->wol_en && (priv->wol_opts & GIANFAR_WOL_ARP) && (priv->device_flags & FSL_GIANFAR_DEV_HAS_ARP_PACKET); if(arp_packet) { pmc_enable_wake(priv->ofdev, PM_SUSPEND_MEM, 0); pmc_enable_lossless(0); gfar_arp_resume(ndev); return 0; } else if(magic_packet) { pmc_enable_wake(priv->ofdev, PM_SUSPEND_MEM, 0); } if(!netif_running(ndev)) { netif_device_attach(ndev); return 0; } if(!magic_packet && priv->phydev) { phy_start(priv->phydev); } /* Disable Magic Packet mode, in case something * else woke us up. */ local_irq_save(flags); lock_tx_qs(priv); lock_rx_qs(priv); tempval = gfar_read(®s->maccfg2); tempval &= ~MACCFG2_MPEN; gfar_write(®s->maccfg2, tempval); gfar_start(ndev); unlock_rx_qs(priv); unlock_tx_qs(priv); local_irq_restore(flags); netif_device_attach(ndev); enable_napi(priv); return 0; } static int gfar_restore(struct device* dev) { struct gfar_private* priv = dev_get_drvdata(dev); struct net_device* ndev = priv->ndev; if(!netif_running(ndev)) { return 0; } gfar_init_bds(ndev); init_registers(ndev); gfar_set_mac_address(ndev); gfar_init_mac(ndev); gfar_start(ndev); priv->oldlink = 0; priv->oldspeed = 0; priv->oldduplex = -1; if(priv->phydev) { phy_start(priv->phydev); } netif_device_attach(ndev); enable_napi(priv); return 0; } static struct dev_pm_ops gfar_pm_ops = { .suspend = gfar_suspend, .resume = gfar_resume, .freeze = gfar_suspend, .thaw = gfar_resume, .restore = gfar_restore, }; #define GFAR_PM_OPS (&gfar_pm_ops) #else #define GFAR_PM_OPS NULL #endif /* Reads the controller's registers to determine what interface * connects it to the PHY. */ static phy_interface_t gfar_get_interface(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 ecntrl; ecntrl = gfar_read(®s->ecntrl); if(ecntrl & ECNTRL_SGMII_MODE) { return PHY_INTERFACE_MODE_SGMII; } if(ecntrl & ECNTRL_TBI_MODE) { if(ecntrl & ECNTRL_REDUCED_MODE) { return PHY_INTERFACE_MODE_RTBI; } else { return PHY_INTERFACE_MODE_TBI; } } if(ecntrl & ECNTRL_REDUCED_MODE) { if(ecntrl & ECNTRL_REDUCED_MII_MODE) { return PHY_INTERFACE_MODE_RMII; } else { phy_interface_t interface = priv->interface; /* * This isn't autodetected right now, so it must * be set by the device tree or platform code. */ if(interface == PHY_INTERFACE_MODE_RGMII_ID) { return PHY_INTERFACE_MODE_RGMII_ID; } return PHY_INTERFACE_MODE_RGMII; } } if(priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) { return PHY_INTERFACE_MODE_GMII; } return PHY_INTERFACE_MODE_MII; } /* Initializes driver's PHY state, and attaches to the PHY. * Returns 0 on success. */ static int mdio_phy_config(struct net_device* dev) { struct phy_device* mdio_phy; struct gfar_private* priv = NULL; // printk(" ************ %s run ***********\n",__func__); priv = netdev_priv(dev); if(!priv->phy_node) { dev_warn(&dev->dev, "error: SGMII mode requires that the " "device tree specify a mdio-handle\n"); return -1; } mdio_phy = of_phy_find_device(priv->phy_node); if(!mdio_phy) { dev_err(&dev->dev, "error: Could not get TBI device\n"); return -1; } phy_write(mdio_phy, 0x16, 0x12); phy_write(mdio_phy, 0x14, 0x1); phy_write(mdio_phy, 0x14, 0x8001); phy_write(mdio_phy, 0x16, 0x0); return 0 ; } /* Initializes driver's PHY state, and attaches to the PHY. * Returns 0 on success. */ static int init_phy(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); uint gigabit_support = priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? SUPPORTED_1000baseT_Full : 0; phy_interface_t interface; priv->oldlink = 0; priv->oldspeed = 0; priv->oldduplex = -1; interface = gfar_get_interface(dev); priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, interface); if(!priv->phydev) priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, interface); if(!priv->phydev) { dev_err(&dev->dev, "could not attach to PHY\n"); return -ENODEV; } if(interface == PHY_INTERFACE_MODE_SGMII) { gfar_configure_serdes(dev); mdio_phy_config(dev); } /* Remove any features not supported by the controller */ priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); priv->phydev->advertising = priv->phydev->supported; return 0; } /* * Initialize TBI PHY interface for communicating with the * SERDES lynx PHY on the chip. We communicate with this PHY * through the MDIO bus on each controller, treating it as a * "normal" PHY at the address found in the TBIPA register. We assume * that the TBIPA register is valid. Either the MDIO bus code will set * it to a value that doesn't conflict with other PHYs on the bus, or the * value doesn't matter, as there are no other PHYs on the bus. */ static void gfar_configure_serdes(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct phy_device* tbiphy; if(!priv->tbi_node) { dev_warn(&dev->dev, "error: SGMII mode requires that the " "device tree specify a tbi-handle\n"); return; } tbiphy = of_phy_find_device(priv->tbi_node); if(!tbiphy) { dev_err(&dev->dev, "error: Could not get TBI device\n"); return; } /* * If the link is already up, we must already be ok, and don't need to * configure and reset the TBI<->SerDes link. Maybe U-Boot configured * everything for us? Resetting it takes the link down and requires * several seconds for it to come back. */ if(phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) { return; } /* Single clk mode, mii mode off(for serdes communication) */ phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); phy_write(tbiphy, MII_ADVERTISE, ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM); phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); } static void init_registers(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = NULL; int i = 0; for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Clear IEVENT */ gfar_write(®s->ievent, IEVENT_INIT_CLEAR); /* Initialize IMASK */ gfar_write(®s->imask, IMASK_INIT_CLEAR); } regs = priv->gfargrp[0].regs; /* Init hash registers to zero */ gfar_write(®s->igaddr0, 0); gfar_write(®s->igaddr1, 0); gfar_write(®s->igaddr2, 0); gfar_write(®s->igaddr3, 0); gfar_write(®s->igaddr4, 0); gfar_write(®s->igaddr5, 0); gfar_write(®s->igaddr6, 0); gfar_write(®s->igaddr7, 0); gfar_write(®s->gaddr0, 0); gfar_write(®s->gaddr1, 0); gfar_write(®s->gaddr2, 0); gfar_write(®s->gaddr3, 0); gfar_write(®s->gaddr4, 0); gfar_write(®s->gaddr5, 0); gfar_write(®s->gaddr6, 0); gfar_write(®s->gaddr7, 0); /* Zero out the rmon mib registers if it has them */ if(priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); /* Mask off the CAM interrupts */ gfar_write(®s->rmon.cam1, 0xffffffff); gfar_write(®s->rmon.cam2, 0xffffffff); } /* Initialize the max receive buffer length */ gfar_write(®s->mrblr, priv->rx_buffer_size); /* Initialize the Minimum Frame Length Register */ gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); } /* Halt the receive and transmit queues */ static void gfar_halt_nodisable(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = NULL; u32 tempval; int i = 0; for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Mask all interrupts */ gfar_write(®s->imask, IMASK_INIT_CLEAR); /* Clear all interrupts */ gfar_write(®s->ievent, IEVENT_INIT_CLEAR); } regs = priv->gfargrp[0].regs; /* Stop the DMA, and wait for it to stop */ tempval = gfar_read(®s->dmactrl); if((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != (DMACTRL_GRS | DMACTRL_GTS)) { tempval |= (DMACTRL_GRS | DMACTRL_GTS); gfar_write(®s->dmactrl, tempval); spin_event_timeout(((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == (IEVENT_GRSC | IEVENT_GTSC)), -1, 0); } } #ifdef CONFIG_PM /* Halt the receive queues */ static void gfar_halt_rx(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 tempval; int i = 0; /* Disable Rx in MACCFG1 */ tempval = gfar_read(®s->maccfg1); tempval &= ~MACCFG1_RX_EN; gfar_write(®s->maccfg1, tempval); for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Mask all interrupts */ gfar_write(®s->imask, IMASK_INIT_CLEAR | IMASK_FGPI); /* Clear all interrupts */ gfar_write(®s->ievent, IEVENT_INIT_CLEAR); } regs = priv->gfargrp[0].regs; /* Stop the DMA, and wait for it to stop */ tempval = gfar_read(®s->dmactrl); if((tempval & DMACTRL_GRS) != DMACTRL_GRS) { tempval |= DMACTRL_GRS; gfar_write(®s->dmactrl, tempval); while(!(gfar_read(®s->ievent) & IEVENT_GRSC)) { cpu_relax(); } } } /* Halt the transmit queues */ static void gfar_halt_tx_nodisable(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = NULL; u32 tempval; int i = 0; for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Mask all interrupts */ gfar_write(®s->imask, IMASK_INIT_CLEAR | IMASK_FGPI); /* Clear all interrupts */ gfar_write(®s->ievent, IEVENT_INIT_CLEAR); } regs = priv->gfargrp[0].regs; /* Stop the DMA, and wait for it to stop */ tempval = gfar_read(®s->dmactrl); if((tempval & DMACTRL_GTS) != DMACTRL_GTS) { tempval |= DMACTRL_GTS; gfar_write(®s->dmactrl, tempval); while(!(gfar_read(®s->ievent) & IEVENT_GTSC)) { cpu_relax(); } } } #endif /* Halt the receive and transmit queues */ void gfar_halt(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 tempval; gfar_halt_nodisable(dev); /* Disable Rx and Tx */ tempval = gfar_read(®s->maccfg1); tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); gfar_write(®s->maccfg1, tempval); } static void free_grp_irqs(struct gfar_priv_grp* grp) { #ifdef CONFIG_GFAR_SW_PKT_STEERING int i; struct gfar_private* priv = grp->priv; int cpus = num_online_cpus(); if(priv->sps) { for(i = 0; i < cpus; i++) { free_irq(grp->msg_virtual_tx[i]->irq, grp); } } #endif free_irq(grp->interruptError, grp); #ifndef CONFIG_RX_TX_BD_XNGE free_irq(grp->interruptTransmit, grp); #endif free_irq(grp->interruptReceive, grp); } void free_bds(struct gfar_private* priv) { unsigned long region_size = 0; region_size = (sizeof(struct txbd8) + sizeof(struct sk_buff*)) * priv->total_tx_ring_size + (sizeof(struct rxbd8) + sizeof(struct sk_buff*)) * priv->total_rx_ring_size; #ifdef CONFIG_GIANFAR_L2SRAM if(priv->bd_in_ram) { dma_free_coherent(&priv->ofdev->dev, region_size, priv->tx_queue[0]->tx_bd_base, priv->tx_queue[0]->tx_bd_dma_base); } else { mpc85xx_cache_sram_free(priv->tx_queue[0]->tx_bd_base); } #else dma_free_coherent(&priv->ofdev->dev, region_size, priv->tx_queue[0]->tx_bd_base, priv->tx_queue[0]->tx_bd_dma_base); #endif } void stop_gfar(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); unsigned long flags; int i; phy_stop(priv->phydev); /* Lock it down */ local_irq_save(flags); lock_tx_qs(priv); lock_rx_qs(priv); gfar_halt(dev); #ifdef CONFIG_GFAR_SKBUFF_RECYCLING priv->skbuff_truesize = 0; #endif unlock_rx_qs(priv); unlock_tx_qs(priv); local_irq_restore(flags); if(priv->ptimer_present) { gfar_1588_stop(dev); } /* Free the IRQs */ if(priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { for(i = 0; i < priv->num_grps; i++) { free_grp_irqs(&priv->gfargrp[i]); } } else { for(i = 0; i < priv->num_grps; i++) free_irq(priv->gfargrp[i].interruptTransmit, &priv->gfargrp[i]); } free_skb_resources(priv); } #ifdef CONFIG_GFAR_SKBUFF_RECYCLING /* * function: gfar_reset_skb_handler * Resetting skb handler spin lock entry in the driver initialization. * Execute only once. */ static void gfar_reset_skb_handler(struct gfar_skb_handler* sh) { spin_lock_init(&sh->lock); sh->recycle_max = GFAR_DEFAULT_RECYCLE_MAX; sh->recycle_count = 0; sh->recycle_queue = NULL; sh->recycle_enable = 1; } /* * function: gfar_free_recycle_queue * Reset SKB handler struction and free existance socket buffer * and data buffer in the recycling queue */ void gfar_free_recycle_queue(struct gfar_skb_handler* sh, int lock_flag) { unsigned long flags = 0; struct sk_buff* clist = NULL; struct sk_buff* skb; /* Get recycling queue */ /* just for making sure there is recycle_queue */ if(lock_flag) { spin_lock_irqsave(&sh->lock, flags); } if(sh->recycle_queue) { /* pick one from head; most recent one */ clist = sh->recycle_queue; sh->recycle_enable = 0; sh->recycle_count = 0; sh->recycle_queue = NULL; } if(lock_flag) { spin_unlock_irqrestore(&sh->lock, flags); } while(clist) { skb = clist; clist = clist->next; dev_kfree_skb_any(skb); } } #endif static void free_skb_tx_queue(struct gfar_priv_tx_q* tx_queue) { struct txbd8* txbdp; struct gfar_private* priv = netdev_priv(tx_queue->dev); int i, j; txbdp = tx_queue->tx_bd_base; for(i = 0; i < tx_queue->tx_ring_size; i++) { if(!tx_queue->tx_skbuff[i]) { continue; } dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, txbdp->length, DMA_TO_DEVICE); txbdp->lstatus = 0; for(j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; j++) { txbdp++; dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, txbdp->length, DMA_TO_DEVICE); } txbdp++; dev_kfree_skb_any(tx_queue->tx_skbuff[i]); tx_queue->tx_skbuff[i] = NULL; } #ifndef CONFIG_GIANFAR_L2SRAM kfree(tx_queue->tx_skbuff); #endif } static void free_skb_rx_queue(struct gfar_priv_rx_q* rx_queue) { struct rxbd8* rxbdp; struct gfar_private* priv = netdev_priv(rx_queue->dev); int i; rxbdp = rx_queue->rx_bd_base; for(i = 0; i < rx_queue->rx_ring_size; i++) { if(rx_queue->rx_skbuff[i]) { dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr, priv->rx_buffer_size, DMA_FROM_DEVICE); dev_kfree_skb_any(rx_queue->rx_skbuff[i]); rx_queue->rx_skbuff[i] = NULL; } rxbdp->lstatus = 0; rxbdp->bufPtr = 0; rxbdp++; } #ifndef CONFIG_GIANFAR_L2SRAM kfree(rx_queue->rx_skbuff); #endif } /* If there are any tx skbs or rx skbs still around, free them. * Then free tx_skbuff and rx_skbuff */ static void free_skb_resources(struct gfar_private* priv) { struct gfar_priv_tx_q* tx_queue = NULL; struct gfar_priv_rx_q* rx_queue = NULL; int i, cpu; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING /* 1: spinlocking of skb_handler is required */ gfar_free_recycle_queue(&(priv->skb_handler), 1); for(i = 0; i < priv->num_tx_queues ; i++) { for_each_possible_cpu(cpu) { gfar_free_recycle_queue( per_cpu_ptr(priv->tx_queue[i]->local_sh, cpu), 0); } free_percpu(priv->tx_queue[i]->local_sh); } for(i = 0; i < priv->num_rx_queues ; i++) { /* 1: spinlocking of skb_handler is required */ gfar_free_recycle_queue(&(priv->rx_queue[i]->skb_handler), 1); for_each_possible_cpu(cpu) { gfar_free_recycle_queue( per_cpu_ptr(priv->rx_queue[i]->local_sh, cpu), 0); } free_percpu(priv->rx_queue[i]->local_sh); } #endif if((priv->device_flags & FSL_GIANFAR_DEV_HAS_ARP_PACKET)) { rx_queue = priv->rx_queue[priv->num_rx_queues - 1]; dma_free_coherent(&priv->ofdev->dev, priv->wk_buffer_size * rx_queue->rx_ring_size \ + RXBUF_ALIGNMENT, (void*)priv->wk_buf_vaddr, priv->wk_buf_paddr); } /* Go through all the buffer descriptors and free their data buffers */ for(i = 0; i < priv->num_tx_queues; i++) { tx_queue = priv->tx_queue[i]; if(tx_queue->tx_skbuff) { free_skb_tx_queue(tx_queue); } } for(i = 0; i < priv->num_rx_queues; i++) { rx_queue = priv->rx_queue[i]; if(rx_queue->rx_skbuff) { free_skb_rx_queue(rx_queue); } } free_bds(priv); } void gfar_start(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 tempval; int i = 0; /* Enable Rx and Tx in MACCFG1 */ tempval = gfar_read(®s->maccfg1); tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); gfar_write(®s->maccfg1, tempval); /* Initialize DMACTRL to have WWR and WOP */ tempval = gfar_read(®s->dmactrl); tempval |= DMACTRL_INIT_SETTINGS; gfar_write(®s->dmactrl, tempval); /* Make sure we aren't stopped */ tempval = gfar_read(®s->dmactrl); tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); gfar_write(®s->dmactrl, tempval); for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Clear THLT/RHLT, so that the DMA starts polling now */ gfar_write(®s->tstat, priv->gfargrp[i].tstat); gfar_write(®s->rstat, priv->gfargrp[i].rstat); /* Unmask the interrupts we look for */ gfar_write(®s->imask, IMASK_DEFAULT); } dev->trans_start = jiffies; /* prevent tx timeout */ } #ifdef CONFIG_PM void gfar_rx_start(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 tempval; int i = 0; /* Enable Rx in MACCFG1 */ tempval = gfar_read(®s->maccfg1); tempval |= MACCFG1_RX_EN; gfar_write(®s->maccfg1, tempval); /* Make sure we aren't stopped */ tempval = gfar_read(®s->dmactrl); tempval &= ~DMACTRL_GRS; gfar_write(®s->dmactrl, tempval); for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Clear RHLT, so that the DMA starts polling now */ gfar_write(®s->rstat, priv->gfargrp[i].rstat); } } void gfar_tx_start(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 tempval; int i = 0; /* Enable Tx in MACCFG1 */ tempval = gfar_read(®s->maccfg1); tempval |= MACCFG1_TX_EN; gfar_write(®s->maccfg1, tempval); /* Make sure we aren't stopped */ tempval = gfar_read(®s->dmactrl); tempval &= ~DMACTRL_GTS; gfar_write(®s->dmactrl, tempval); for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; /* Clear THLT, so that the DMA starts polling now */ gfar_write(®s->rstat, priv->gfargrp[i].tstat); } } #endif void gfar_configure_tx_coalescing(struct gfar_private* priv, long unsigned int tx_mask) { struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 __iomem* baddr; int i = 0, mask = 0x1; /* Backward compatible case ---- even if we enable * multiple queues, there's only single reg to program */ if(priv->mode == SQ_SG_MODE) { gfar_write(®s->txic, 0); if(likely(priv->tx_queue[0]->txcoalescing)) { gfar_write(®s->txic, priv->tx_queue[0]->txic); } } if(priv->mode == MQ_MG_MODE) { baddr = ®s->txic0; for(i = 0; i < priv->num_tx_queues; i++) { if(tx_mask & mask) { if(likely(priv->tx_queue[i]->txcoalescing)) { gfar_write(baddr + i, 0); gfar_write(baddr + i, priv->tx_queue[i]->txic); } } mask = mask << 0x1; } } } void gfar_configure_rx_coalescing(struct gfar_private* priv, long unsigned int rx_mask) { struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 __iomem* baddr; int i = 0, mask = 0x1; /* Backward compatible case ---- even if we enable * multiple queues, there's only single reg to program */ if(priv->mode == SQ_SG_MODE) { gfar_write(®s->rxic, 0); if(unlikely(priv->rx_queue[0]->rxcoalescing)) { gfar_write(®s->rxic, priv->rx_queue[0]->rxic); } } if(priv->mode == MQ_MG_MODE) { baddr = ®s->rxic0; for(i = 0; i < priv->num_rx_queues; i++) { if(rx_mask & mask) { if(likely(priv->rx_queue[i]->rxcoalescing)) { gfar_write(baddr + i, 0); gfar_write(baddr + i, priv->rx_queue[i]->rxic); } } mask = mask << 0x1; } } } static int register_grp_irqs(struct gfar_priv_grp* grp) { struct gfar_private* priv = grp->priv; struct net_device* dev = priv->ndev; int err; #ifdef CONFIG_GFAR_SW_PKT_STEERING int i, j; int cpus = num_online_cpus(); struct cpumask cpumask_msg_intrs; #endif /* If the device has multiple interrupts, register for * them. Otherwise, only register for the one */ if(priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { /* Install our interrupt handlers for Error, * Transmit, and Receive */ if((err = request_irq(grp->interruptError, gfar_error, 0, grp->int_name_er, grp)) < 0) { if(netif_msg_intr(priv)) printk(KERN_ERR "%s: Can't get IRQ %d\n", dev->name, grp->interruptError); goto err_irq_fail; } #ifndef CONFIG_RX_TX_BD_XNGE if((err = request_irq(grp->interruptTransmit, gfar_transmit, 0, grp->int_name_tx, grp)) < 0) { if(netif_msg_intr(priv)) printk(KERN_ERR "%s: Can't get IRQ %d\n", dev->name, grp->interruptTransmit); goto tx_irq_fail; } #endif if((err = request_irq(grp->interruptReceive, gfar_receive, 0, grp->int_name_rx, grp)) < 0) { if(netif_msg_intr(priv)) printk(KERN_ERR "%s: Can't get IRQ %d\n", dev->name, grp->interruptReceive); goto rx_irq_fail; } } else { if((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0, grp->int_name_tx, grp)) < 0) { if(netif_msg_intr(priv)) printk(KERN_ERR "%s: Can't get IRQ %d\n", dev->name, grp->interruptTransmit); goto err_irq_fail; } } #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { for(i = 0; i < cpus; i++) { sprintf(grp->int_name_vtx[i], "%s_g%d_vtx%d", priv->ndev->name, grp->grp_id, i); err = request_irq(grp->msg_virtual_tx[i]->irq, gfar_virtual_transmit, 0, grp->int_name_vtx[i], grp); if(err < 0) { priv->sps = 0; printk(KERN_WARNING "%s: Can't request msg IRQ %d for dev %s\n", __func__, grp->msg_virtual_tx[i]->irq, dev->name); for(j = 0; j < i; j++) { free_irq(grp->msg_virtual_tx[j]->irq, grp); clrbits32(grp->msg_virtual_tx[j]->mer, 1 << grp->msg_virtual_tx[j]->msg_num); } goto vtx_irq_fail; } cpumask_clear(&cpumask_msg_intrs); cpumask_set_cpu(i, &cpumask_msg_intrs); irq_set_affinity(grp->msg_virtual_tx[i]->irq, &cpumask_msg_intrs); fsl_enable_msg(grp->msg_virtual_tx[i]); } } #endif return 0; #ifdef CONFIG_GFAR_SW_PKT_STEERING vtx_irq_fail: free_irq(grp->interruptReceive, grp); #endif rx_irq_fail: #ifndef CONFIG_RX_TX_BD_XNGE free_irq(grp->interruptTransmit, grp); #endif tx_irq_fail: free_irq(grp->interruptError, grp); err_irq_fail: return err; } /* Bring the controller up and running */ int startup_gfar(struct net_device* ndev) { struct gfar_private* priv = netdev_priv(ndev); struct gfar __iomem* regs = NULL; int err, i, j, cpu; for(i = 0; i < priv->num_grps; i++) { regs = priv->gfargrp[i].regs; gfar_write(®s->imask, IMASK_INIT_CLEAR); } regs = priv->gfargrp[0].regs; err = gfar_alloc_skb_resources(ndev); if(err) { return err; } gfar_init_mac(ndev); #ifdef CONFIG_GFAR_SKBUFF_RECYCLING priv->skbuff_truesize = GFAR_DEFAULT_RECYCLE_TRUESIZE; gfar_reset_skb_handler(&(priv->skb_handler)); for(i = 0; i < priv->num_tx_queues; i++) { priv->tx_queue[i]->local_sh = alloc_percpu( struct gfar_skb_handler); for_each_possible_cpu(cpu) { gfar_reset_skb_handler( per_cpu_ptr(priv->tx_queue[i]->local_sh, cpu)); } } for(i = 0; i < priv->num_rx_queues; i++) { priv->rx_queue[i]->rx_skbuff_truesize = GFAR_DEFAULT_RECYCLE_TRUESIZE; gfar_reset_skb_handler(&(priv->rx_queue[i]->skb_handler)); priv->rx_queue[i]->local_sh = alloc_percpu( struct gfar_skb_handler); for_each_possible_cpu(cpu) { gfar_reset_skb_handler( per_cpu_ptr(priv->rx_queue[i]->local_sh, cpu)); } } #endif for(i = 0; i < priv->num_grps; i++) { err = register_grp_irqs(&priv->gfargrp[i]); if(err) { for(j = 0; j < i; j++) { free_grp_irqs(&priv->gfargrp[j]); } goto irq_fail; } } /* Start the controller */ gfar_start(ndev); phy_start(priv->phydev); gfar_configure_tx_coalescing(priv, 0xFF); gfar_configure_rx_coalescing(priv, 0xFF); return 0; irq_fail: free_skb_resources(priv); return err; } /* Called when something needs to use the ethernet device */ /* Returns 0 for success. */ static int gfar_enet_open(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); int err; enable_napi(priv); /* Initialize a bunch of registers */ init_registers(dev); gfar_set_mac_address(dev); err = init_phy(dev); if(err) { disable_napi(priv); return err; } err = startup_gfar(dev); if(err) { disable_napi(priv); return err; } netif_tx_start_all_queues(dev); device_set_wakeup_enable(&priv->ofdev->dev, priv->wol_en); return err; } static inline struct txfcb* gfar_add_fcb(struct sk_buff* skb) { struct txfcb* fcb = (struct txfcb*)skb_push(skb, GMAC_FCB_LEN); memset(fcb, 0, GMAC_FCB_LEN); return fcb; } static inline void gfar_tx_checksum(struct sk_buff* skb, struct txfcb* fcb) { u8 flags = 0; /* If we're here, it's a IP packet with a TCP or UDP * payload. We set it to checksum, using a pseudo-header * we provide */ flags = TXFCB_DEFAULT; /* Tell the controller what the protocol is */ /* And provide the already calculated phcs */ if(!((ip_hdr(skb)->frag_off) & htons(IP_MF | IP_OFFSET))) { /* If not fragmented packet */ if(ip_hdr(skb)->protocol == IPPROTO_UDP) { if(udp_hdr(skb)->check) { fcb->phcs = udp_hdr(skb)->check; flags |= TXFCB_NPH; } flags |= TXFCB_UDP | TXFCB_TUP | TXFCB_CTU; } else if(ip_hdr(skb)->protocol == IPPROTO_TCP) { if(tcp_hdr(skb)->check) { flags |= TXFCB_NPH; fcb->phcs = tcp_hdr(skb)->check; } flags |= TXFCB_TUP | TXFCB_CTU; } } /* l3os is the distance between the start of the * frame (skb->data) and the start of the IP hdr. * l4os is the distance between the start of the * l3 hdr and the l4 hdr */ fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); fcb->l4os = skb_network_header_len(skb); fcb->flags = flags; } void inline gfar_tx_vlan(struct sk_buff* skb, struct txfcb* fcb) { fcb->flags |= TXFCB_VLN; fcb->vlctl = vlan_tx_tag_get(skb); } static inline struct txbd8* skip_txbd(struct txbd8* bdp, int stride, struct txbd8* base, int ring_size) { struct txbd8* new_bd = bdp + stride; return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; } static inline struct txbd8* next_txbd(struct txbd8* bdp, struct txbd8* base, int ring_size) { return skip_txbd(bdp, 1, base, ring_size); } static int gfar_xmit_skb(struct sk_buff* skb, struct net_device* dev, int rq) { struct gfar_private* priv = netdev_priv(dev); struct gfar_priv_tx_q* tx_queue = NULL; struct netdev_queue* txq; struct gfar __iomem* regs = NULL; struct txfcb* fcb = NULL; struct txbd8* txbdp, *txbdp_start, *base; u32 lstatus; int i; u32 bufaddr; unsigned long flags; unsigned int nr_frags, length; tx_queue = priv->tx_queue[rq]; txq = netdev_get_tx_queue(dev, rq); base = tx_queue->tx_bd_base; regs = tx_queue->grp->regs; /* total number of fragments in the SKB */ nr_frags = skb_shinfo(skb)->nr_frags; /* check if there is space to queue this packet */ if((nr_frags + 1) > tx_queue->num_txbdfree) { /* no space, stop the queue */ netif_tx_stop_queue(txq); dev->stats.tx_fifo_errors++; return NETDEV_TX_BUSY; } /* Update transmit stats */ txq->tx_bytes += skb->len; txq->tx_packets++; txbdp = txbdp_start = tx_queue->cur_tx; if(nr_frags == 0) { lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); } else { /* Place the fragment addresses and lengths into the TxBDs */ for(i = 0; i < nr_frags; i++) { /* Point at the next BD, wrapping as needed */ txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); length = skb_shinfo(skb)->frags[i].size; lstatus = txbdp->lstatus | length | BD_LFLAG(TXBD_READY); /* Handle the last BD specially */ if(i == nr_frags - 1) { lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); } bufaddr = dma_map_page(&priv->ofdev->dev, skb_shinfo(skb)->frags[i].page, skb_shinfo(skb)->frags[i].page_offset, length, DMA_TO_DEVICE); /* set the TxBD length and buffer pointer */ txbdp->bufPtr = bufaddr; txbdp->lstatus = lstatus; } lstatus = txbdp_start->lstatus; } /* Set up checksumming */ if(CHECKSUM_PARTIAL == skb->ip_summed) { fcb = gfar_add_fcb(skb); lstatus |= BD_LFLAG(TXBD_TOE); gfar_tx_checksum(skb, fcb); } if(priv->vlgrp && vlan_tx_tag_present(skb)) { if(unlikely(NULL == fcb)) { fcb = gfar_add_fcb(skb); lstatus |= BD_LFLAG(TXBD_TOE); } gfar_tx_vlan(skb, fcb); } /* setup the TxBD length and buffer pointer for the first BD */ tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); /* * We can work in parallel with gfar_clean_tx_ring(), except * when modifying num_txbdfree. Note that we didn't grab the lock * when we were reading the num_txbdfree and checking for available * space, that's because outside of this function it can only grow, * and once we've got needed space, it cannot suddenly disappear. * * The lock also protects us from gfar_error(), which can modify * regs->tstat and thus retrigger the transfers, which is why we * also must grab the lock before setting ready bit for the first * to be transmitted BD. */ spin_lock_irqsave(&tx_queue->txlock, flags); /* * The powerpc-specific eieio() is used, as wmb() has too strong * semantics (it requires synchronization between cacheable and * uncacheable mappings, which eieio doesn't provide and which we * don't need), thus requiring a more expensive sync instruction. At * some point, the set of architecture-independent barrier functions * should be expanded to include weaker barriers. */ eieio(); txbdp_start->lstatus = lstatus; /* Update the current skb pointer to the next entry we will use * (wrapping if necessary) */ tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & TX_RING_MOD_MASK(tx_queue->tx_ring_size); tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); /* reduce TxBD free count */ tx_queue->num_txbdfree -= (nr_frags + 1); txq->trans_start = jiffies; /* If the next BD still needs to be cleaned up, then the bds are full. We need to tell the kernel to stop sending us stuff. */ if(!tx_queue->num_txbdfree) { netif_stop_subqueue(dev, tx_queue->qindex); dev->stats.tx_fifo_errors++; } /* Tell the DMA to go go go */ gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); /* Unlock priv */ spin_unlock_irqrestore(&tx_queue->txlock, flags); return NETDEV_TX_OK; } /*software TCP segmentation offload*/ static int gfar_tso(struct sk_buff* skb, struct net_device* dev, int rq) { struct gfar_private* priv = netdev_priv(dev); int i = 0; struct iphdr* iph; int ihl; int id; unsigned int offset = 0; struct tcphdr* th; unsigned thlen; unsigned int seq; __be32 delta; unsigned int oldlen; unsigned int mss; unsigned int doffset; unsigned int headroom; unsigned int len; int nfrags; int pos; int hsize; int ret; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING int howmany_reuse = 0; struct gfar_skb_handler* sh; int free_skb; struct sk_buff* local_head; unsigned long flags; struct gfar_skb_handler* local_sh; local_sh = per_cpu_ptr(priv->tx_queue[rq]->local_sh, smp_processor_id()); if(local_sh->recycle_queue) { local_head = local_sh->recycle_queue; free_skb = local_sh->recycle_count; local_sh->recycle_queue = NULL; local_sh->recycle_count = 0; } else { local_head = NULL; free_skb = 0; } /* global skb_handler for this device */ sh = &priv->skb_handler; #endif /*processing mac header*/ skb_reset_mac_header(skb); skb->mac_len = skb->network_header - skb->mac_header; __skb_pull(skb, skb->mac_len); /*processing IP header*/ iph = ip_hdr(skb); ihl = iph->ihl * 4; __skb_pull(skb, ihl); skb_reset_transport_header(skb); iph = ip_hdr(skb); id = ntohs(iph->id); /*processing TCP header*/ th = tcp_hdr(skb); thlen = th->doff * 4; oldlen = (u16)~skb->len; __skb_pull(skb, thlen); mss = skb_shinfo(skb)->gso_size; seq = ntohl(th->seq); delta = htonl(oldlen + (thlen + mss)); /*processing SKB*/ doffset = skb->data - skb_mac_header(skb); offset = doffset; nfrags = skb_shinfo(skb)->nr_frags; __skb_push(skb, doffset); headroom = skb_headroom(skb); pos = skb_headlen(skb); /*duplicating SKB*/ hsize = skb_headlen(skb) - offset; if(hsize < 0) { hsize = 0; } do { struct sk_buff* nskb; skb_frag_t* frag; int size; len = skb->len - offset; if(len > mss) { len = mss; } #ifdef CONFIG_GFAR_SKBUFF_RECYCLING if(!free_skb) { spin_lock_irqsave(&sh->lock, flags); if(!free_skb && sh->recycle_count) { /* refill local buffer */ local_head = sh->recycle_queue; free_skb = sh->recycle_count; sh->recycle_queue = NULL; sh->recycle_count = 0; } spin_unlock_irqrestore(&sh->lock, flags); } if(local_head) { nskb = local_head;; local_head = nskb->next; nskb->next = NULL; free_skb--; howmany_reuse++; } else { nskb = gfar_new_skb(dev); } #else nskb = alloc_skb(hsize + doffset + headroom, GFP_ATOMIC); #endif skb_reserve(nskb, headroom); __skb_put(nskb, doffset + hsize); nskb->ip_summed = skb->ip_summed; nskb->vlan_tci = skb->vlan_tci; nskb->mac_len = skb->mac_len; skb_reset_mac_header(nskb); skb_set_network_header(nskb, skb->mac_len); nskb->transport_header = (nskb->network_header + skb_network_header_len(skb)); skb_copy_from_linear_data(skb, nskb->data, doffset + hsize); frag = skb_shinfo(nskb)->frags; /*move skb data*/ while(pos < offset + len && i < nfrags) { *frag = skb_shinfo(skb)->frags[i]; get_page(frag->page); size = frag->size; if(pos < offset) { frag->page_offset += offset - pos; frag->size -= offset - pos; } skb_shinfo(nskb)->nr_frags++; if(pos + size <= offset + len) { i++; pos += size; } else { frag->size -= pos + size - (offset + len); goto skip_fraglist; } frag++; } skip_fraglist: nskb->data_len = len - hsize; nskb->len += nskb->data_len; /*update TCP header*/ if((offset + len) >= skb->len) delta = htonl(oldlen + (nskb->tail - nskb->transport_header) + nskb->data_len); th = tcp_hdr(nskb); th->fin = th->psh = 0; th->seq = htonl(seq); th->cwr = 0; seq += mss; th->check = ~csum_fold((__force __wsum)((__force u32)th->check + (__force u32)delta)); /*update IP header*/ iph = ip_hdr(nskb); iph->id = htons(id++); iph->tot_len = htons(nskb->len - nskb->mac_len); iph->check = 0; iph->check = ip_fast_csum(skb_network_header(nskb), iph->ihl); ret = gfar_xmit_skb(nskb, dev, rq); if(unlikely(ret != NETDEV_TX_OK)) { skb = nskb; goto out_tso; } } while((offset += len) < skb->len); out_tso: #ifdef CONFIG_GFAR_SKBUFF_RECYCLING if(free_skb) { /* return to local_sh for next time */ local_sh->recycle_queue = local_head; local_sh->recycle_count = free_skb; } priv->extra_stats.rx_skbr += howmany_reuse; #endif dev_kfree_skb_any(skb); return ret; } /* This is called by the kernel when a frame is ready for transmission. */ /* It is pointed to by the dev->hard_start_xmit function pointer */ static int gfar_start_xmit(struct sk_buff* skb, struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar_priv_tx_q* tx_queue = NULL; struct netdev_queue* txq; struct gfar __iomem* regs = NULL; struct txfcb* fcb = NULL; struct txbd8* txbdp, *txbdp_start, *base; u32 lstatus; int i, rq = 0; u32 bufaddr; unsigned long flags; unsigned int nr_frags, length; #ifdef CONFIG_RX_TX_BD_XNGE struct sk_buff* new_skb; int skb_curtx = 0; #endif #ifdef CONFIG_AS_FASTPATH if(devfp_tx_hook && (skb->pkt_type != PACKET_FASTROUTE)) if(devfp_tx_hook(skb, dev) == AS_FP_STOLEN) { return 0; } #endif #ifdef CONFIG_RX_TX_BD_XNGE rq = smp_processor_id() + 1; #else #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { rq = smp_processor_id(); } else #endif rq = skb->queue_mapping; #endif tx_queue = priv->tx_queue[rq]; txq = netdev_get_tx_queue(dev, rq); base = tx_queue->tx_bd_base; regs = tx_queue->grp->regs; /* make space for additional header when fcb is needed */ if(((skb->ip_summed == CHECKSUM_PARTIAL) || (priv->vlgrp && vlan_tx_tag_present(skb))) && (skb_headroom(skb) < GMAC_FCB_LEN)) { struct sk_buff* skb_new; skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); if(!skb_new) { dev->stats.tx_errors++; kfree_skb(skb); return NETDEV_TX_OK; } kfree_skb(skb); skb = skb_new; } if(skb_shinfo(skb)->gso_size) { return gfar_tso(skb, dev, rq); } /* total number of fragments in the SKB */ nr_frags = skb_shinfo(skb)->nr_frags; #ifndef CONFIG_RX_TX_BD_XNGE /* check if there is space to queue this packet */ if((nr_frags + 1) > tx_queue->num_txbdfree) { /* no space, stop the queue */ netif_tx_stop_queue(txq); dev->stats.tx_fifo_errors++; return NETDEV_TX_BUSY; } #endif /* Update transmit stats */ txq->tx_bytes += skb->len; txq->tx_packets ++; txbdp = txbdp_start = tx_queue->cur_tx; #ifdef CONFIG_RX_TX_BD_XNGE txbdp->lstatus &= BD_LFLAG(TXBD_WRAP); #endif if(nr_frags == 0) { lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); } else { /* Place the fragment addresses and lengths into the TxBDs */ for(i = 0; i < nr_frags; i++) { /* Point at the next BD, wrapping as needed */ txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); length = skb_shinfo(skb)->frags[i].size; #ifdef CONFIG_RX_TX_BD_XNGE txbdp->lstatus &= BD_LFLAG(TXBD_WRAP); #endif lstatus = txbdp->lstatus | length | BD_LFLAG(TXBD_READY); /* Handle the last BD specially */ if(i == nr_frags - 1) { lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); } bufaddr = dma_map_page(&priv->ofdev->dev, skb_shinfo(skb)->frags[i].page, skb_shinfo(skb)->frags[i].page_offset, length, DMA_TO_DEVICE); /* set the TxBD length and buffer pointer */ txbdp->bufPtr = bufaddr; txbdp->lstatus = lstatus; } lstatus = txbdp_start->lstatus; } /* Set up checksumming */ if(CHECKSUM_PARTIAL == skb->ip_summed) { fcb = gfar_add_fcb(skb); lstatus |= BD_LFLAG(TXBD_TOE); gfar_tx_checksum(skb, fcb); } if(priv->vlgrp && vlan_tx_tag_present(skb)) { if(unlikely(NULL == fcb)) { fcb = gfar_add_fcb(skb); lstatus |= BD_LFLAG(TXBD_TOE); } gfar_tx_vlan(skb, fcb); } if(priv->ptimer_present) { /* Enable ptp flag so that Tx time stamping happens */ if(gfar_ptp_do_txstamp(skb)) { if(fcb == NULL) { fcb = gfar_add_fcb(skb); } fcb->ptp = 0x01; lstatus |= BD_LFLAG(TXBD_TOE); } } #ifdef CONFIG_RX_TX_BD_XNGE new_skb = tx_queue->tx_skbuff[tx_queue->skb_curtx]; skb_curtx = tx_queue->skb_curtx; if(new_skb && skb->owner != RT_PKT_ID) { /* Packet from Kernel free the skb to recycle poll */ gfar_kfree_skb(new_skb , new_skb->queue_mapping); new_skb = NULL; } #endif /* setup the TxBD length and buffer pointer for the first BD */ txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); /* * We can work in parallel with gfar_clean_tx_ring(), except * when modifying num_txbdfree. Note that we didn't grab the lock * when we were reading the num_txbdfree and checking for available * space, that's because outside of this function it can only grow, * and once we've got needed space, it cannot suddenly disappear. * * The lock also protects us from gfar_error(), which can modify * regs->tstat and thus retrigger the transfers, which is why we * also must grab the lock before setting ready bit for the first * to be transmitted BD. */ #ifndef CONFIG_RX_TX_BD_XNGE #ifdef CONFIG_GFAR_SW_PKT_STEERING if(!priv->sps) #endif spin_lock_irqsave(&tx_queue->txlock, flags); #endif /* * The powerpc-specific eieio() is used, as wmb() has too strong * semantics (it requires synchronization between cacheable and * uncacheable mappings, which eieio doesn't provide and which we * don't need), thus requiring a more expensive sync instruction. At * some point, the set of architecture-independent barrier functions * should be expanded to include weaker barriers. */ eieio(); txbdp_start->lstatus = lstatus; eieio(); /* force lstatus write before tx_skbuff */ tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; /* Update the current skb pointer to the next entry we will use * (wrapping if necessary) */ tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & TX_RING_MOD_MASK(tx_queue->tx_ring_size); tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); #ifndef CONFIG_RX_TX_BD_XNGE /* reduce TxBD free count */ tx_queue->num_txbdfree -= (nr_frags + 1); /* If the next BD still needs to be cleaned up, then the bds are full. We need to tell the kernel to stop sending us stuff. */ if(!tx_queue->num_txbdfree) { netif_stop_subqueue(dev, tx_queue->qindex); dev->stats.tx_fifo_errors++; } #endif dev->trans_start = jiffies; /* Tell the DMA to go go go */ gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); /* Unlock priv */ #ifndef CONFIG_RX_TX_BD_XNGE #ifdef CONFIG_GFAR_SW_PKT_STEERING if(!priv->sps) #endif spin_unlock_irqrestore(&tx_queue->txlock, flags); #endif #ifdef CONFIG_RX_TX_BD_XNGE if((skb->skb_owner == NULL) || skb_has_frags(skb) || skb_cloned(skb) || skb_header_cloned(skb) || (atomic_read(&skb->users) > 1)) { dev_kfree_skb_any(skb); tx_queue->tx_skbuff[skb_curtx] = NULL; } else { gfar_clean_reclaim_skb(skb); } skb->new_skb = new_skb; #endif return NETDEV_TX_OK; } /* * This is called by try_fastroute when a fastroute frame is ready for * transmission. */ int gfar_fast_xmit(struct sk_buff* skb, struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar_priv_tx_q* tx_queue = NULL; struct netdev_queue* txq; struct gfar __iomem* regs = NULL; struct txbd8* txbdp, *txbdp_start, *base; u32 lstatus; int rq = 0; unsigned long flags; #ifdef CONFIG_RX_TX_BD_XNGE struct sk_buff* new_skb; int skb_curtx = 0; #endif #ifdef CONFIG_RX_TX_BD_XNGE rq = smp_processor_id() + 1; #else #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { rq = smp_processor_id(); } else #endif rq = skb->queue_mapping; #endif tx_queue = priv->tx_queue[rq]; txq = netdev_get_tx_queue(dev, rq); base = tx_queue->tx_bd_base; regs = tx_queue->grp->regs; #ifndef CONFIG_RX_TX_BD_XNGE /* check if there is space to queue this packet */ if(unlikely(tx_queue->num_txbdfree < 1)) { /* no space, stop the queue */ netif_tx_stop_queue(txq); dev->stats.tx_fifo_errors++; return NETDEV_TX_BUSY; } #endif /* Update transmit stats */ txq->tx_bytes += skb->len; txq->tx_packets++; txbdp = txbdp_start = tx_queue->cur_tx; #ifdef CONFIG_RX_TX_BD_XNGE txbdp->lstatus &= BD_LFLAG(TXBD_WRAP); #endif lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); #ifdef CONFIG_AS_FASTPATH /* Set up checksumming */ if(CHECKSUM_PARTIAL == skb->ip_summed) { struct txfcb* fcb = NULL; fcb = gfar_add_fcb(skb); lstatus |= BD_LFLAG(TXBD_TOE); gfar_tx_checksum(skb, fcb); } #endif #ifdef CONFIG_RX_TX_BD_XNGE new_skb = tx_queue->tx_skbuff[tx_queue->skb_curtx]; skb_curtx = tx_queue->skb_curtx; if(new_skb && (skb->owner != RT_PKT_ID)) { /* Packet from Kernel free the skb to recycle poll */ gfar_kfree_skb(new_skb , new_skb->queue_mapping); new_skb = NULL; } #endif txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); /* * We can work in parallel with gfar_clean_tx_ring(), except * when modifying num_txbdfree. Note that we didn't grab the lock * when we were reading the num_txbdfree and checking for available * space, that's because outside of this function it can only grow, * and once we've got needed space, it cannot suddenly disappear. * * The lock also protects us from gfar_error(), which can modify * regs->tstat and thus retrigger the transfers, which is why we * also must grab the lock before setting ready bit for the first * to be transmitted BD. */ #ifndef CONFIG_RX_TX_BD_XNGE #ifdef CONFIG_GFAR_SW_PKT_STEERING if(!priv->sps) #endif spin_lock_irqsave(&tx_queue->txlock, flags); #endif /* * The powerpc-specific eieio() is used, as wmb() has too strong * semantics (it requires synchronization between cacheable and * uncacheable mappings, which eieio doesn't provide and which we * don't need), thus requiring a more expensive sync instruction. At * some point, the set of architecture-independent barrier functions * should be expanded to include weaker barriers. */ eieio(); txbdp_start->lstatus = lstatus; eieio(); /* force lstatus write before tx_skbuff */ /* setup the TxBD length and buffer pointer for the first BD */ tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; /* Update the current skb pointer to the next entry we will use * (wrapping if necessary) */ tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & TX_RING_MOD_MASK(tx_queue->tx_ring_size); tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); #ifndef CONFIG_RX_TX_BD_XNGE /* reduce TxBD free count */ tx_queue->num_txbdfree -= 1; /* If the next BD still needs to be cleaned up, then the bds are full. We need to tell the kernel to stop sending us stuff. */ if(unlikely(!tx_queue->num_txbdfree)) { netif_stop_subqueue(dev, tx_queue->qindex); dev->stats.tx_fifo_errors++; } #endif /* Tell the DMA to go go go */ gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); #ifndef CONFIG_RX_TX_BD_XNGE #ifdef CONFIG_GFAR_SW_PKT_STEERING if(!priv->sps) #endif spin_unlock_irqrestore(&tx_queue->txlock, flags); #endif #ifdef CONFIG_RX_TX_BD_XNGE if((skb->skb_owner == NULL) || skb_has_frags(skb) || skb_cloned(skb) || skb_header_cloned(skb) || (atomic_read(&skb->users) > 1)) { dev_kfree_skb_any(skb); tx_queue->tx_skbuff[skb_curtx] = NULL; } else { gfar_clean_reclaim_skb(skb); } skb->new_skb = new_skb; #endif return NETDEV_TX_OK; } EXPORT_SYMBOL(gfar_fast_xmit); /* Stops the kernel queue, and halts the controller */ static int gfar_close(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); disable_napi(priv); cancel_work_sync(&priv->reset_task); stop_gfar(dev); /* Disconnect from the PHY */ phy_disconnect(priv->phydev); priv->phydev = NULL; netif_tx_stop_all_queues(dev); return 0; } /* Changes the mac address if the controller is not running. */ static int gfar_set_mac_address(struct net_device* dev) { gfar_set_mac_for_addr(dev, 0, dev->dev_addr); return 0; } /********************************************************************** * gfar_accept_fastpath * * Used to authenticate to the kernel that a fast path entry can be * added to device's routing table cache * * Input : pointer to ethernet interface network device structure and * a pointer to the designated entry to be added to the cache. * Output : zero upon success, negative upon failure **********************************************************************/ #ifdef CONFIG_NET_GIANFAR_FP static int gfar_accept_fastpath(struct net_device* dev, struct dst_entry* dst) { struct net_device* odev = dst->dev; const struct net_device_ops* ops = odev->netdev_ops; if((dst->ops->protocol != __constant_htons(ETH_P_IP)) || (odev->type != ARPHRD_ETHER) || (ops->ndo_accept_fastpath == NULL)) { return -1; } return 0; } static inline int neigh_is_valid(struct neighbour* neigh) { return neigh->nud_state & NUD_VALID; } u32 gfar_fastroute_hash(u8 daddr, u8 saddr) { u32 hash; hash = ((u32)daddr ^ saddr) & NETDEV_FASTROUTE_HMASK; return hash; } #endif /* try_fastroute() -- Checks the fastroute cache to see if a given packet * can be routed immediately to another device. If it can, we send it. * If we used a fastroute, we return 1. Otherwise, we return 0. * Returns 0 if CONFIG_NET_GIANFAR_FP is not on */ static inline int try_fastroute(struct sk_buff* skb, struct net_device* dev, int length) { #ifdef CONFIG_NET_GIANFAR_FP struct ethhdr* eth; struct iphdr* iph; unsigned int hash; struct rtable* rt; struct net_device* odev; struct gfar_private* priv = netdev_priv(dev); struct netdev_queue* txq = NULL; const struct net_device_ops* ops; u16 q_idx = 0; /* this is correct. pull padding already */ eth = (struct ethhdr*)(skb->data); /* Only route ethernet IP packets */ if(eth->h_proto != __constant_htons(ETH_P_IP)) { return 0; } iph = (struct iphdr*)(skb->data + ETH_HLEN); /* Generate the hash value */ hash = gfar_fastroute_hash((*(u8*)&iph->daddr), (*(u8*)&iph->saddr)); #ifdef FASTPATH_DEBUG printk(KERN_INFO "%s: hash = %d (%d, %d)\n", __func__, hash, (*(u8*)&iph->daddr), (*(u8*)&iph->saddr)); #endif rt = (struct rtable*)(dev->fastpath[hash]); /* Only support big endian */ if((rt != NULL) && ((*(u32*)(&iph->daddr)) == (*(u32*)(&rt->rt_dst))) && ((*(u32*)(&iph->saddr)) == (*(u32*)(&rt->rt_src))) && !(rt->u.dst.obsolete > 0)) { odev = rt->u.dst.dev; /* get output device */ ops = odev->netdev_ops; /* Make sure the packet is: * 1) IPv4 * 2) without any options (header length of 5) * 3) Not a multicast packet * 4) going to a valid destination * 5) Not out of time-to-live */ if(iph->version == 4 && iph->ihl == 5 && (!(eth->h_dest[0] & 0x01)) && neigh_is_valid(rt->u.dst.neighbour) && iph->ttl > 1) { q_idx = skb_tx_hash(odev, skb); skb_set_queue_mapping(skb, q_idx); txq = netdev_get_tx_queue(odev, q_idx); /* Fast Route Path: Taken if the outgoing * device is ready to transmit the packet now */ if((!netif_tx_queue_stopped(txq)) && (!spin_is_locked(&txq->_xmit_lock)) && (skb->len <= (odev->mtu + ETH_HLEN + 2 + 4))) { skb->pkt_type = PACKET_FASTROUTE; skb->protocol = __constant_htons(ETH_P_IP); skb_set_network_header(skb, ETH_HLEN); ip_decrease_ttl(iph); memcpy(eth->h_source, odev->dev_addr, MAC_ADDR_LEN); memcpy(eth->h_dest, rt->u.dst.neighbour->ha, MAC_ADDR_LEN); skb->dev = odev; if(likely(ops->ndo_start_xmit == gfar_start_xmit)) { gfar_fast_xmit(skb, odev); } else if(ops->ndo_start_xmit(skb, odev) != 0) { panic("%s: FastRoute path corrupted", dev->name); } priv->extra_stats.rx_fast++; } else { skb_reset_network_header(skb); /* Tell the skb what kind of packet this is*/ skb->protocol = eth_type_trans(skb, dev); /* Prep the skb for the packet */ if(netif_receive_skb(skb) == NET_RX_DROP) { priv->extra_stats.kernel_dropped++; } } return 1; } } #endif /* CONFIG_NET_GIANFAR_FP */ return 0; } /* Enables and disables VLAN insertion/extraction */ static void gfar_vlan_rx_register(struct net_device* dev, struct vlan_group* grp) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = NULL; unsigned long flags; u32 tempval; regs = priv->gfargrp[0].regs; local_irq_save(flags); lock_rx_qs(priv); priv->vlgrp = grp; if(grp) { /* Enable VLAN tag insertion */ tempval = gfar_read(®s->tctrl); tempval |= TCTRL_VLINS; gfar_write(®s->tctrl, tempval); /* Enable VLAN tag extraction */ tempval = gfar_read(®s->rctrl); tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); gfar_write(®s->rctrl, tempval); } else { /* Disable VLAN tag insertion */ tempval = gfar_read(®s->tctrl); tempval &= ~TCTRL_VLINS; gfar_write(®s->tctrl, tempval); /* Disable VLAN tag extraction */ tempval = gfar_read(®s->rctrl); tempval &= ~RCTRL_VLEX; /* If parse is no longer required, then disable parser */ if(tempval & RCTRL_REQ_PARSER) { tempval |= RCTRL_PRSDEP_INIT; } else { tempval &= ~RCTRL_PRSDEP_INIT; } gfar_write(®s->rctrl, tempval); } gfar_change_mtu(dev, dev->mtu); unlock_rx_qs(priv); local_irq_restore(flags); } static int gfar_change_mtu(struct net_device* dev, int new_mtu) { int tempsize, tempval; struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; int oldsize = priv->rx_buffer_size; int frame_size = new_mtu + ETH_HLEN; #ifdef CONFIG_GFAR_SW_PKT_STEERING if(rcv_pkt_steering && priv->sps) { printk(KERN_ERR "Can't change mtu with rcv_pkt_steering on\n"); return -EINVAL; } #endif if(priv->vlgrp) { frame_size += VLAN_HLEN; } if((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { if(netif_msg_drv(priv)) printk(KERN_ERR "%s: Invalid MTU setting\n", dev->name); return -EINVAL; } if(gfar_uses_fcb(priv)) { frame_size += GMAC_FCB_LEN; } frame_size += priv->padding; tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + INCREMENTAL_BUFFER_SIZE; /* Only stop and start the controller if it isn't already * stopped, and we changed something */ if((oldsize != tempsize) && (dev->flags & IFF_UP)) { stop_gfar(dev); } priv->rx_buffer_size = tempsize; dev->mtu = new_mtu; gfar_write(®s->mrblr, priv->rx_buffer_size); gfar_write(®s->maxfrm, priv->rx_buffer_size); /* If the mtu is larger than the max size for standard * ethernet frames (ie, a jumbo frame), then set maccfg2 * to allow huge frames, and to check the length */ tempval = gfar_read(®s->maccfg2); if(priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) { tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); } else { tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); } gfar_write(®s->maccfg2, tempval); if((oldsize != tempsize) && (dev->flags & IFF_UP)) { startup_gfar(dev); } #ifdef CONFIG_GFAR_SKBUFF_RECYCLING gfar_skbr_register_truesize(priv); #endif /*CONFIG_GFAR_SKBUFF_RECYCLING*/ return 0; } /* gfar_reset_task gets scheduled when a packet has not been * transmitted after a set amount of time. * For now, assume that clearing out all the structures, and * starting over will fix the problem. */ static void gfar_reset_task(struct work_struct* work) { struct gfar_private* priv = container_of(work, struct gfar_private, reset_task); struct net_device* dev = priv->ndev; if(dev->flags & IFF_UP) { netif_tx_stop_all_queues(dev); stop_gfar(dev); startup_gfar(dev); netif_tx_start_all_queues(dev); } netif_tx_schedule_all(dev); } static void gfar_timeout(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); dev->stats.tx_errors++; schedule_work(&priv->reset_task); } /* Interrupt Handler for Transmit complete */ #ifdef CONFIG_GIANFAR_TXNAPI static int gfar_clean_tx_ring(struct gfar_priv_tx_q* tx_queue, int tx_work_limit) #else static int gfar_clean_tx_ring(struct gfar_priv_tx_q* tx_queue) #endif { struct net_device* dev = tx_queue->dev; struct gfar_private* priv = netdev_priv(dev); struct gfar_priv_rx_q* rx_queue = NULL; struct txbd8* bdp; struct txbd8* lbdp = NULL; struct txbd8* base = tx_queue->tx_bd_base; struct sk_buff* skb; int skb_dirtytx; int tx_ring_size = tx_queue->tx_ring_size; int frags = 0; int i; int howmany = 0; u32 lstatus; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING int howmany_recycle = 0; #endif rx_queue = priv->rx_queue[tx_queue->qindex]; bdp = tx_queue->dirty_tx; skb_dirtytx = tx_queue->skb_dirtytx; while((skb = tx_queue->tx_skbuff[skb_dirtytx])) { unsigned long flags; frags = skb_shinfo(skb)->nr_frags; lbdp = skip_txbd(bdp, frags, base, tx_ring_size); lstatus = lbdp->lstatus; /* Only clean completed frames */ if((lstatus & BD_LFLAG(TXBD_READY)) && (lstatus & BD_LENGTH_MASK)) { break; } dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, bdp->length, DMA_TO_DEVICE); bdp->lstatus &= BD_LFLAG(TXBD_WRAP); bdp = next_txbd(bdp, base, tx_ring_size); for(i = 0; i < frags; i++) { dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr, bdp->length, DMA_TO_DEVICE); bdp->lstatus &= BD_LFLAG(TXBD_WRAP); bdp = next_txbd(bdp, base, tx_ring_size); } #ifdef CONFIG_TCP_FAST_ACK if(skb->sk && skb->truesize == SKB_DATA_ALIGN(MAX_TCP_HEADER) + sizeof(struct sk_buff) && TCP_SKB_CB(skb)->flags == TCPCB_FLAG_ACK && skb_queue_len(&skb->sk->sk_ack_queue) < GFAR_DEFAULT_RECYCLE_MAX && spin_trylock(&skb->sk->sk_ack_queue.lock)) { __skb_queue_head(&skb->sk->sk_ack_queue, skb); spin_unlock(&skb->sk->sk_ack_queue.lock); if(skb->destructor) { skb->destructor(skb); } } else #endif { #ifdef CONFIG_GFAR_SKBUFF_RECYCLING howmany_recycle += gfar_kfree_skb(skb, tx_queue->qindex); #else dev_kfree_skb_any(skb); #endif } tx_queue->tx_skbuff[skb_dirtytx] = NULL; skb_dirtytx = (skb_dirtytx + 1) & TX_RING_MOD_MASK(tx_ring_size); howmany++; #ifndef CONFIG_GIANFAR_TXNAPI spin_lock_irqsave(&tx_queue->txlock, flags); tx_queue->num_txbdfree += frags + 1; spin_unlock_irqrestore(&tx_queue->txlock, flags); #else tx_queue->num_txbdfree += frags + 1; #endif } /* If we freed a buffer, we can restart transmission, if necessary */ if(__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree) { netif_wake_subqueue(dev, tx_queue->qindex); } /* Update dirty indicators */ tx_queue->skb_dirtytx = skb_dirtytx; tx_queue->dirty_tx = bdp; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING priv->extra_stats.rx_skbr_free += howmany_recycle; #endif return howmany; } #ifdef CONFIG_GIANFAR_TXNAPI static void gfar_schedule_cleanup_rx(struct gfar_priv_grp* gfargrp) { unsigned long flags; u32 imask = 0; if(napi_schedule_prep(&gfargrp->napi_rx)) { spin_lock_irqsave(&gfargrp->grplock, flags); imask = gfar_read(&gfargrp->regs->imask); imask = imask & IMASK_RX_DISABLED; gfar_write(&gfargrp->regs->imask, imask); spin_unlock_irqrestore(&gfargrp->grplock, flags); __napi_schedule(&gfargrp->napi_rx); } else { gfar_write(&gfargrp->regs->ievent, IEVENT_RX_MASK); } } static void gfar_schedule_cleanup_tx(struct gfar_priv_grp* gfargrp) { unsigned long flags; u32 imask = 0; #ifdef CONFIG_GFAR_SW_PKT_STEERING int cpu = smp_processor_id(); #endif spin_lock_irqsave(&gfargrp->grplock, flags); #ifdef CONFIG_GFAR_SW_PKT_STEERING if(napi_schedule_prep(&gfargrp->napi_tx[cpu])) { #else if(napi_schedule_prep(&gfargrp->napi_tx)) { #endif imask = gfar_read(&gfargrp->regs->imask); imask = imask & IMASK_TX_DISABLED; gfar_write(&gfargrp->regs->imask, imask); #ifdef CONFIG_GFAR_SW_PKT_STEERING __napi_schedule(&gfargrp->napi_tx[cpu]); #else __napi_schedule(&gfargrp->napi_tx); #endif } else { gfar_write(&gfargrp->regs->ievent, IEVENT_TX_MASK); } spin_unlock_irqrestore(&gfargrp->grplock, flags); } #else static void gfar_schedule_cleanup(struct gfar_priv_grp* gfargrp) { unsigned long flags; spin_lock_irqsave(&gfargrp->grplock, flags); if(napi_schedule_prep(&gfargrp->napi)) { gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); __napi_schedule(&gfargrp->napi); } else { /* * Clear IEVENT, so interrupts aren't called again * because of the packets that have already arrived. */ gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); } spin_unlock_irqrestore(&gfargrp->grplock, flags); } #endif /* Interrupt Handler for Transmit complete */ static irqreturn_t gfar_transmit(int irq, void* grp_id) { #ifdef CONFIG_GIANFAR_TXNAPI #ifdef CONFIG_GFAR_SW_PKT_STEERING struct gfar_priv_grp* grp = (struct gfar_priv_grp*)grp_id; struct gfar_private* priv = grp->priv; unsigned int tstat = gfar_read(&grp->regs->tstat); int cpu = smp_processor_id(); unsigned long flags; if(priv->sps) { spin_lock_irqsave(&grp->grplock, flags); if(tstat & (0x8000 >> !cpu)) { fsl_send_msg(grp->msg_virtual_tx[!cpu], 0x1); } if(tstat & (0x8000 >> cpu)) if(napi_schedule_prep(&grp->napi_tx[cpu])) { __napi_schedule(&grp->napi_tx[cpu]); } gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); /* clear TXF0,TXF1 in TSTAT */ gfar_write(&grp->regs->tstat, (tstat & 0xC000)); spin_unlock_irqrestore(&grp->grplock, flags); } else { #endif gfar_schedule_cleanup_tx((struct gfar_priv_grp*)grp_id); #ifdef CONFIG_GFAR_SW_PKT_STEERING } #endif #else #ifdef CONFIG_GFAR_TX_NONAPI struct gfar_priv_grp* grp = (struct gfar_priv_grp*)grp_id; struct gfar_private* priv = priv = grp->priv; unsigned int mask = TSTAT_TXF0_MASK; unsigned int tstat = gfar_read(&grp->regs->tstat); int i; struct gfar_priv_tx_q* tx_queue = NULL; tstat = gfar_read(&grp->regs->tstat); tstat = tstat & TSTAT_TXF_MASK_ALL; /* Clear IEVENT */ gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); for(i = 0; i < priv->num_tx_queues; i++) { if(tstat & mask) { tx_queue = priv->tx_queue[i]; gfar_clean_tx_ring(tx_queue); } mask = mask >> 0x1; } gfar_configure_tx_coalescing(priv, grp->tx_bit_map); #else gfar_schedule_cleanup((struct gfar_priv_grp*)grp_id); #endif #endif return IRQ_HANDLED; } static void gfar_new_rxbdp(struct gfar_priv_rx_q* rx_queue, struct rxbd8* bdp, struct sk_buff* skb) { struct net_device* dev = rx_queue->dev; struct gfar_private* priv = netdev_priv(dev); dma_addr_t buf; buf = dma_map_single(&priv->ofdev->dev, skb->data, priv->rx_buffer_size, DMA_FROM_DEVICE); gfar_init_rxbdp(rx_queue, bdp, buf); } #ifdef CONFIG_GFAR_SKBUFF_RECYCLING static unsigned int skbuff_truesize(unsigned int buffer_size) { return SKB_DATA_ALIGN(buffer_size + RXBUF_ALIGNMENT + NET_SKB_PAD) + sizeof(struct sk_buff); } static void gfar_skbr_register_truesize(struct gfar_private* priv) { int i = 0; priv->skbuff_truesize = skbuff_truesize(priv->rx_buffer_size); for(i = 0; i < priv->num_rx_queues; i++) priv->rx_queue[i]->rx_skbuff_truesize = skbuff_truesize(priv->rx_buffer_size); } static inline void gfar_clean_reclaim_skb(struct sk_buff* skb) { unsigned int truesize; unsigned int size; unsigned int alignamount; struct net_device* owner; #ifdef CONFIG_AS_FASTPATH if(!skb->asf) { /* Execute only if packet is not belonging to ASF */ #endif skb_dst_drop(skb); if(skb->destructor) { skb->destructor(skb); skb->destructor = NULL; } #ifdef CONFIG_XFRM if(skb->sp) { secpath_put(skb->sp); skb->sp = NULL; } #endif #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) nf_conntrack_put(skb->nfct); nf_conntrack_put_reasm(skb->nfct_reasm); skb->nfct = NULL; skb->nfct_reasm = NULL; #endif #ifdef CONFIG_BRIDGE_NETFILTER nf_bridge_put(skb->nf_bridge); skb->nf_bridge = NULL; #endif #ifdef CONFIG_NET_SCHED skb->tc_index = 0; #ifdef CONFIG_NET_CLS_ACT skb->tc_verd = 0; #endif #endif #ifdef CONFIG_AS_FASTPATH } #endif /* re-initialization * We are not going to touch the buffer size, so * skb->truesize can be used as the truesize again */ if(skb_shinfo(skb)->nr_frags) { int i; for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) { put_page(skb_shinfo(skb)->frags[i].page); } skb_shinfo(skb)->nr_frags = 0; } owner = skb->skb_owner; truesize = skb->truesize; size = truesize - sizeof(struct sk_buff); /* clear structure by &tail */ #ifdef CONFIG_AS_FASTPATH if(!skb->asf) { /* Execute only if packet is not belonging to ASF */ #endif cacheable_memzero(skb, offsetof(struct sk_buff, tail)); #ifdef CONFIG_AS_FASTPATH } else { /* Just reset the fields used in software DPA */ skb->next = skb->prev = NULL; skb->asf = 0; skb->dev = NULL; skb->len = 0; skb->ip_summed = 0; skb->transport_header = NULL; skb->mac_header = NULL; skb->network_header = NULL; skb->pkt_type = 0; skb->mac_len = 0; skb->protocol = 0; skb->vlan_tci = 0; skb->data = 0; } #endif atomic_set(&skb->users, 1); /* reset data and tail pointers */ skb->data = skb->head + NET_SKB_PAD; skb_reset_tail_pointer(skb); /* shared info clean up */ atomic_set(&(skb_shinfo(skb)->dataref), 1); /* We need the data buffer to be aligned properly. We will * reserve as many bytes as needed to align the data properly */ alignamount = ((unsigned)skb->data) & (RXBUF_ALIGNMENT - 1); if(alignamount) { skb_reserve(skb, RXBUF_ALIGNMENT - alignamount); } skb->dev = owner; /* Keep incoming device pointer for recycling */ skb->skb_owner = owner; } static int gfar_kfree_skb(struct sk_buff* skb, int qindex) { struct gfar_private* priv; struct gfar_skb_handler* sh; unsigned long flags = 0; if((skb->skb_owner == NULL) || skb_has_frags(skb) || skb_cloned(skb) || skb_header_cloned(skb) || (atomic_read(&skb->users) > 1)) { goto _normal_free; } priv = netdev_priv(skb->skb_owner); #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { qindex = 0; } #endif if(skb->truesize == priv->skbuff_truesize) { #ifdef CONFIG_GFAR_SW_PKT_STEERING if(rcv_pkt_steering && priv->sps) { sh = &__get_cpu_var(gfar_cpu_dev).sh; } else #endif sh = per_cpu_ptr(priv->rx_queue[qindex]->local_sh, smp_processor_id()); /* loosly checking */ if(likely(sh->recycle_count < sh->recycle_max)) { gfar_clean_reclaim_skb(skb); skb->next = sh->recycle_queue; sh->recycle_queue = skb; sh->recycle_count++; return 1; } else { sh = &priv->skb_handler; gfar_clean_reclaim_skb(skb); spin_lock_irqsave(&sh->lock, flags); if(likely(sh->recycle_count < sh->recycle_max)) { if(unlikely(!sh->recycle_enable)) { spin_unlock_irqrestore(&sh->lock, flags); return 0; } skb->next = sh->recycle_queue; sh->recycle_queue = skb; sh->recycle_count++; spin_unlock_irqrestore(&sh->lock, flags); return 1; } else { spin_unlock_irqrestore(&sh->lock, flags); } } } _normal_free: /* skb is not recyclable */ dev_kfree_skb_any(skb); return 0; } int gfar_recycle_skb(struct sk_buff* skb) { unsigned long int flags; struct gfar_private* priv; struct gfar_skb_handler* sh; if((skb->skb_owner == NULL) || skb_has_frags(skb) || skb_cloned(skb) || skb_header_cloned(skb) || (atomic_read(&skb->users) > 1)) { return 0; } priv = netdev_priv(skb->skb_owner); if(skb->truesize == priv->skbuff_truesize) { sh = &priv->skb_handler; /* loosly checking */ gfar_clean_reclaim_skb(skb); spin_lock_irqsave(&sh->lock, flags); if(likely(sh->recycle_count < sh->recycle_max)) { /* lock sh for add one */ if(unlikely(!sh->recycle_enable)) { spin_unlock_irqrestore(&sh->lock, flags); return 0; } skb->next = sh->recycle_queue; sh->recycle_queue = skb; sh->recycle_count++; spin_unlock_irqrestore(&sh->lock, flags); priv->extra_stats.rx_skbr_free++; return 1; } else { spin_unlock_irqrestore(&sh->lock, flags); } } /* skb is not recyclable */ return 0; } #endif /* RECYCLING */ /* * normal new skb routine */ struct sk_buff* gfar_new_skb(struct net_device* dev) { unsigned int alignamount; struct gfar_private* priv = netdev_priv(dev); struct sk_buff* skb = NULL; skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); if(!skb) { return NULL; } alignamount = RXBUF_ALIGNMENT - (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); /* We need the data buffer to be aligned properly. We will reserve * as many bytes as needed to align the data properly * Do only if not already aligned */ if(alignamount != RXBUF_ALIGNMENT) { skb_reserve(skb, alignamount); } GFAR_CB(skb)->alignamount = alignamount; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING skb->dev = dev; #endif /* Keep incoming device pointer for recycling */ skb->skb_owner = dev; return skb; } EXPORT_SYMBOL(gfar_new_skb); static inline void count_errors(unsigned short status, struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct net_device_stats* stats = &dev->stats; struct gfar_extra_stats* estats = &priv->extra_stats; /* If the packet was truncated, none of the other errors * matter */ if(status & RXBD_TRUNCATED) { stats->rx_length_errors++; estats->rx_trunc++; return; } /* Count the errors, if there were any */ if(status & (RXBD_LARGE | RXBD_SHORT)) { stats->rx_length_errors++; if(status & RXBD_LARGE) { estats->rx_large++; } else { estats->rx_short++; } } if(status & RXBD_NONOCTET) { stats->rx_frame_errors++; estats->rx_nonoctet++; } if(status & RXBD_CRCERR) { estats->rx_crcerr++; stats->rx_crc_errors++; } if(status & RXBD_OVERRUN) { estats->rx_overrun++; stats->rx_crc_errors++; } } static inline unsigned long __wk_phy_to_virt(struct net_device* dev, unsigned long phy) { struct gfar_private* priv = netdev_priv(dev); unsigned long virt, offset; offset = phy - priv->wk_buf_align_paddr; virt = priv->wk_buf_align_vaddr + offset; return virt; } static void gfar_receive_wakeup(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar_priv_rx_q* rx_queue = priv->rx_queue[priv->num_rx_queues - 1]; struct rxbd8* bdp = rx_queue->cur_rx; struct sk_buff* skb; unsigned char* data; u16 len; int ret; /* get the first full descriptor */ while(!(bdp->status & RXBD_EMPTY)) { rmb(); if(bdp->status & RXBD_ERR) { printk(KERN_ERR "Wake up packet error!\n"); goto out; } data = (u8*)__wk_phy_to_virt(dev, bdp->bufPtr); len = bdp->length; /* allocate the skb */ skb = netdev_alloc_skb(dev, len); if(!skb) { dev->stats.rx_dropped++; priv->extra_stats.rx_skbmissing++; goto out; } /* The wake up packet has the FCB */ data += (GMAC_FCB_LEN + priv->padding); len -= (GMAC_FCB_LEN + priv->padding); /* remove the FCS from the packet length */ len -= 4; /* copy received packet to skb buffer */ memcpy(skb->data, data, len); /* Prep the skb for the packet */ skb_put(skb, len); /* Tell the skb what kind of packet this is */ skb->protocol = eth_type_trans(skb, dev); ret = netif_rx(skb); if(NET_RX_DROP == ret) { priv->extra_stats.kernel_dropped++; } else { /* Increment the number of packets */ dev->stats.rx_packets++; dev->stats.rx_bytes += len; } out: bdp->status &= RXBD_CLEAN; bdp->status |= RXBD_EMPTY; bdp->length = 0; mb(); /* Update to the next pointer */ if(bdp->status & RXBD_WRAP) { bdp = priv->wk_bd_base; } else { bdp++; } } rx_queue->cur_rx = bdp; } irqreturn_t gfar_receive(int irq, void* grp_id) { struct gfar_priv_grp* gfargrp = grp_id; struct gfar __iomem* regs = gfargrp->regs; struct gfar_private* priv = gfargrp->priv; struct net_device* dev = priv->ndev; u32 ievent; ievent = gfar_read(®s->ievent); if((ievent & IEVENT_FGPI) == IEVENT_FGPI) { gfar_write(®s->ievent, ievent & IEVENT_RX_MASK); gfar_receive_wakeup(dev); return IRQ_HANDLED; } #ifdef CONFIG_GIANFAR_TXNAPI gfar_schedule_cleanup_rx((struct gfar_priv_grp*)grp_id); #else #ifdef CONFIG_GFAR_TX_NONAPI struct gfar_priv_grp* grp = (struct gfar_priv_grp*)grp_id; u32 tempval; /* * Clear IEVENT, so interrupts aren't called again * because of the packets that have already arrived. */ gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); if(napi_schedule_prep(&grp->napi)) { tempval = gfar_read(&grp->regs->imask); tempval &= IMASK_RX_DISABLED; gfar_write(&grp->regs->imask, tempval); __napi_schedule(&grp->napi); } else { if(netif_msg_rx_err(grp->priv)) printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n", dev->name, gfar_read(&grp->regs->ievent), gfar_read(&grp->regs->imask)); } #else gfar_schedule_cleanup((struct gfar_priv_grp*)grp_id); #endif #endif return IRQ_HANDLED; } /* gfar_process_frame() -- handle one incoming packet if skb * isn't NULL. */ static int gfar_process_frame(struct net_device* dev, struct sk_buff* skb, int amount_pull) { struct gfar_private* priv = netdev_priv(dev); struct rxfcb* fcb = NULL; int ret; /* fcb is at the beginning if exists */ fcb = (struct rxfcb*)skb->data; /* Remove the padded bytes, if there are any */ if(amount_pull) { int queue_map; /* If FCB->QT field contains a value > num_rx_queues then a direct mapping to virtual queues using QT as index will result in a CRASH, when we are going to free the SKB. So, need to map the QT value to existing virtual queues only. using modulo by num_rx_queues. */ queue_map = fcb->rq - (priv->num_rx_queues * (fcb->rq / priv->num_rx_queues)); skb_record_rx_queue(skb, queue_map); skb_pull(skb, amount_pull); } #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { skb_set_queue_mapping(skb, smp_processor_id()); } #endif if(priv->ptimer_present) { gfar_ptp_store_rxstamp(dev, skb); skb_pull(skb, 8); } if(priv->rx_csum_enable) { gfar_rx_checksum(skb, fcb); } #ifdef CONFIG_AS_FASTPATH if(devfp_rx_hook) { int drop = 0; /* Drop the packet silently if IP Checksum is not correct */ if((fcb->flags & RXFCB_CIP) && (fcb->flags & RXFCB_EIP)) { drop = 1; goto drop_pkt; } if(priv->vlgrp && (fcb->flags & RXFCB_VLN)) { struct net_device* vlan_dev = NULL; vlan_dev = vlan_group_get_device(priv->vlgrp, fcb->vlctl & VLAN_VID_MASK); if(vlan_dev) { skb->vlan_tci = fcb->vlctl; skb->dev = vlan_dev; } else { drop = 1; } } else { skb->dev = dev; } drop_pkt: if(drop) { #ifdef CONFIG_GFAR_SKBUFF_RECYCLING gfar_kfree_skb(skb, skb_get_rx_queue(skb)); #else dev_kfree_skb_any(skb); #endif return 0; } if(devfp_rx_hook(skb, dev) == AS_FP_STOLEN) { return 0; } } #endif #ifdef CONFIG_NET_GIANFAR_FP if(netdev_fastroute && (try_fastroute(skb, dev, skb->len) != 0)) { return 0; } #endif /* Tell the skb what kind of packet this is */ skb->protocol = eth_type_trans(skb, dev); /* Send the packet up the stack */ if(unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) { ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); } else { ret = netif_receive_skb(skb); } if(NET_RX_DROP == ret) { priv->extra_stats.kernel_dropped++; } return 0; } /* gfar_clean_rx_ring() -- Processes each frame in the rx ring * until the budget/quota has been reached. Returns the number * of frames handled */ int gfar_clean_rx_ring(struct gfar_priv_rx_q* rx_queue, int rx_work_limit) { struct net_device* dev = rx_queue->dev; struct rxbd8* bdp, *base; struct sk_buff* skb; int pkt_len; int amount_pull; int howmany = 0; struct gfar_private* priv = netdev_priv(dev); #ifdef CONFIG_GFAR_SW_PKT_STEERING int ret; #endif #ifdef CONFIG_GFAR_SKBUFF_RECYCLING int howmany_reuse = 0; struct gfar_skb_handler* sh; int free_skb; struct sk_buff* local_head; unsigned long flags; struct gfar_skb_handler* local_sh; int global_skb_handler = 0; /* 0 if per-cpu SKB handler is in use, 1 if global (stored in 'priv') in use */ #ifdef CONFIG_GFAR_SW_PKT_STEERING struct sk_buff* local_tail; int temp; #endif #endif /* Get the first full descriptor */ bdp = rx_queue->cur_rx; base = rx_queue->rx_bd_base; if(priv->ptimer_present) { amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); } else amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + priv->padding; #ifdef CONFIG_GFAR_SKBUFF_RECYCLING #ifdef CONFIG_GFAR_SW_PKT_STEERING if(rcv_pkt_steering && priv->sps) { local_head = NULL; free_skb = 0; sh = &__get_cpu_var(gfar_cpu_dev).sh; } else { #endif local_sh = per_cpu_ptr(rx_queue->local_sh, smp_processor_id()); if(local_sh->recycle_queue) { local_head = local_sh->recycle_queue; free_skb = local_sh->recycle_count; local_sh->recycle_queue = NULL; local_sh->recycle_count = 0; } else { local_head = NULL; free_skb = 0; } /* global skb_handler for this device */ sh = &rx_queue->skb_handler; #ifdef CONFIG_GFAR_SW_PKT_STEERING } #endif if((sh->recycle_count == 0) && (priv->skb_handler.recycle_count > 0)) { global_skb_handler = 1; sh = &priv->skb_handler; } #endif while(!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { struct sk_buff* newskb = NULL; rmb(); #ifndef CONFIG_RX_TX_BD_XNGE #ifdef CONFIG_GFAR_SKBUFF_RECYCLING if(!free_skb) { if(global_skb_handler) { spin_lock_irqsave(&sh->lock, flags); } if(sh->recycle_count) { /* refill local buffer */ local_head = sh->recycle_queue; free_skb = sh->recycle_count; sh->recycle_queue = NULL; sh->recycle_count = 0; } if(global_skb_handler) { spin_unlock_irqrestore(&sh->lock, flags); } } if(local_head) { newskb = local_head; local_head = newskb->next; newskb->next = NULL; free_skb--; howmany_reuse++; } else { newskb = gfar_new_skb(dev); } #else /* Add another skb for the future */ newskb = gfar_new_skb(dev); #endif #endif skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, priv->rx_buffer_size, DMA_FROM_DEVICE); if(unlikely(!(bdp->status & RXBD_ERR) && bdp->length > priv->rx_buffer_size)) { bdp->status = RXBD_LARGE; } #ifndef CONFIG_RX_TX_BD_XNGE /* We drop the frame if we failed to allocate a new buffer */ if(unlikely(!newskb || !(bdp->status & RXBD_LAST) || bdp->status & RXBD_ERR)) { count_errors(bdp->status, dev); if(unlikely(!newskb)) { newskb = skb; } else if(skb) { dev_kfree_skb_any(skb); } #else if(unlikely(!(bdp->status & RXBD_LAST) || bdp->status & RXBD_ERR)) { count_errors(bdp->status, dev); newskb = skb; #endif } else { /* Increment the number of packets */ rx_queue->stats.rx_packets++; howmany++; if(likely(skb)) { pkt_len = bdp->length - ETH_FCS_LEN; /* Remove the FCS from the packet length */ skb_put(skb, pkt_len); rx_queue->stats.rx_bytes += pkt_len; skb_record_rx_queue(skb, rx_queue->qindex); if(in_irq() || irqs_disabled()) { printk("Interrupt problem!\n"); } #ifdef CONFIG_RX_TX_BD_XNGE skb->owner = RT_PKT_ID; #endif #ifdef CONFIG_GFAR_SW_PKT_STEERING /* Process packet here or send it to other cpu for processing based on packet headers hash value */ if(rcv_pkt_steering && priv->sps) { ret = distribute_packet(dev, skb, amount_pull); if(ret) gfar_process_frame(dev, skb, amount_pull); } else { gfar_process_frame(dev, skb, amount_pull); } #else #ifdef CONFIG_GFAR_HW_TCP_RECEIVE_OFFLOAD if((rx_queue->qindex >= TCP_CHL_OFFSET) && priv->tcp_hw_channel[rx_queue->qindex - TCP_CHL_OFFSET]) { gfar_hwaccel_tcp4_receive(priv, rx_queue, skb, amount_pull); } else #endif gfar_process_frame(dev, skb, amount_pull); #endif #ifdef CONFIG_RX_TX_BD_XNGE newskb = skb->new_skb; skb->owner = 0; skb->new_skb = NULL; #endif } else { if(netif_msg_rx_err(priv)) printk(KERN_WARNING "%s: Missing skb!\n", dev->name); rx_queue->stats.rx_dropped++; priv->extra_stats.rx_skbmissing++; } } #ifdef CONFIG_RX_TX_BD_XNGE if(!newskb) { #ifdef CONFIG_GFAR_SKBUFF_RECYCLING if(global_skb_handler) { spin_lock_irqsave(&sh->lock, flags); } if(!free_skb && sh->recycle_count) { /* refill local buffer */ local_head = sh->recycle_queue; free_skb = sh->recycle_count; sh->recycle_queue = NULL; sh->recycle_count = 0; } if(global_skb_handler) { spin_unlock_irqrestore(&sh->lock, flags); } if(local_head) { newskb = local_head; local_head = newskb->next; newskb->next = NULL; free_skb--; howmany_reuse++; } else { newskb = gfar_new_skb(dev); } #else /* Add another skb for the future */ newskb = gfar_new_skb(dev); #endif } if(!newskb) /* All memory Exhausted,a BUG */ { BUG(); } #endif rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; /* Setup the new bdp */ gfar_new_rxbdp(rx_queue, bdp, newskb); /* Update to the next pointer */ bdp = next_bd(bdp, base, rx_queue->rx_ring_size); /* update to point at the next skb */ rx_queue->skb_currx = (rx_queue->skb_currx + 1) & RX_RING_MOD_MASK(rx_queue->rx_ring_size); } #ifdef CONFIG_GFAR_SKBUFF_RECYCLING #ifdef CONFIG_GFAR_SW_PKT_STEERING if(rcv_pkt_steering && priv->sps) { if(free_skb > 0) { /* return left over skb to cpu's recycle buffer */ if(global_skb_handler) { spin_lock_irqsave(&sh->lock, flags); } if(sh->recycle_max >= (sh->recycle_count + free_skb)) { temp = free_skb - 1; local_tail = local_head; while(temp--) { local_tail = local_tail->next; } local_tail->next = sh->recycle_queue; sh->recycle_queue = local_head; sh->recycle_count += free_skb; if(global_skb_handler) spin_unlock_irqrestore(&sh->lock, flags); } else { if(global_skb_handler) spin_unlock_irqrestore(&sh->lock, flags); /* free the left over skbs if recycle buffer cant accomodate */ temp = free_skb; while(temp--) { local_tail = local_head; local_head = local_head->next; if(local_tail) { dev_kfree_skb_any(local_tail); } } } } } else { #endif if(free_skb) { #ifdef CONFIG_RX_TX_BD_XNGE /* Return to local_sh for next time */ if(local_sh->recycle_queue) { struct sk_buff* local_tail = local_sh->recycle_queue; while(local_tail->next) { local_tail = local_tail->next; } local_tail->next = local_head; } else { local_sh->recycle_queue = local_head; } local_sh->recycle_count += free_skb; #else local_sh->recycle_queue = local_head; local_sh->recycle_count = free_skb; #endif } #ifdef CONFIG_GFAR_SW_PKT_STEERING } #endif priv->extra_stats.rx_skbr += howmany_reuse; #endif /* Update the current rxbd pointer to be the next one */ rx_queue->cur_rx = bdp; return howmany; } #ifdef CONFIG_GIANFAR_TXNAPI static int gfar_poll_tx(struct napi_struct* napi, int budget) { #ifdef CONFIG_GFAR_SW_PKT_STEERING int cpu = smp_processor_id(); struct gfar_priv_grp* gfargrp = container_of(napi, struct gfar_priv_grp, napi_tx[cpu]); #else struct gfar_priv_grp* gfargrp = container_of(napi, struct gfar_priv_grp, napi_tx); #endif struct gfar_private* priv = gfargrp->priv; struct gfar __iomem* regs = gfargrp->regs; struct gfar_priv_tx_q* tx_queue = NULL; int budget_per_queue = 0, tx_cleaned = 0, i = 0, num_act_qs = 0; int tx_cleaned_per_queue = 0, mask = TSTAT_TXF0_MASK; unsigned long flags; u32 imask, tstat, tstat_local; #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { tx_queue = priv->tx_queue[cpu]; tx_cleaned = gfar_clean_tx_ring(tx_queue, budget); } else { #endif tstat = gfar_read(®s->tstat); tstat = tstat & TSTAT_TXF_MASK_ALL; tstat_local = tstat; while(tstat_local) { num_act_qs++; tstat_local &= (tstat_local - 1); } budget_per_queue = budget / num_act_qs; gfar_write(®s->ievent, IEVENT_TX_MASK); for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { mask = mask >> i; if(tstat & mask) { tx_queue = priv->tx_queue[i]; spin_lock_irqsave(&tx_queue->txlock, flags); tx_cleaned_per_queue = gfar_clean_tx_ring(tx_queue, budget_per_queue); spin_unlock_irqrestore(&tx_queue->txlock, flags); tx_cleaned += tx_cleaned_per_queue; tx_cleaned_per_queue = 0; } mask = TSTAT_TXF0_MASK; } budget = (num_act_qs * DEFAULT_TX_RING_SIZE) + 1; #ifdef CONFIG_GFAR_SW_PKT_STEERING } #endif if(tx_cleaned < budget) { napi_complete(napi); #ifdef CONFIG_GFAR_SW_PKT_STEERING if(!priv->sps) { #endif spin_lock_irq(&gfargrp->grplock); imask = gfar_read(®s->imask); imask |= IMASK_DEFAULT_TX; gfar_write(®s->ievent, IEVENT_TX_MASK); gfar_write(®s->imask, imask); spin_unlock_irq(&gfargrp->grplock); gfar_configure_tx_coalescing(priv, gfargrp->tx_bit_map); #ifdef CONFIG_GFAR_SW_PKT_STEERING } else { gfar_write(®s->ievent, IEVENT_TX_MASK); } #endif return 1; } #ifdef CONFIG_GFAR_SW_PKT_STEERING if(priv->sps) { return 1; } else #endif return tx_cleaned; } static int gfar_poll_rx(struct napi_struct* napi, int budget) { struct gfar_priv_grp* gfargrp = container_of(napi, struct gfar_priv_grp, napi_rx); struct gfar_private* priv = gfargrp->priv; struct gfar __iomem* regs = gfargrp->regs; struct gfar_priv_rx_q* rx_queue = NULL; int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; int num_act_qs = 0, mask = RSTAT_RXF0_MASK, i, napi_done = 1; u32 imask, rstat, rstat_local, rstat_rxf, rstat_rhalt; u32 ievent; rstat = gfar_read(®s->rstat); rstat_rxf = (rstat & RSTAT_RXF_ALL_MASK); rstat_rxf |= gfargrp->rstat_prev; rstat_local = rstat_rxf; while(rstat_local) { num_act_qs++; rstat_local &= (rstat_local - 1); } budget_per_queue = budget / num_act_qs; gfar_write(®s->rstat, rstat_rxf); gfar_write(&gfargrp->regs->ievent, IEVENT_RX_MASK); gfargrp->rstat_prev = rstat_rxf; for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { mask = RSTAT_RXF0_MASK >> i; rstat_rhalt = RSTAT_CLEAR_RHALT >> i; if(rstat_rxf & mask) { rx_queue = priv->rx_queue[i]; rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue, budget_per_queue); rx_cleaned += rx_cleaned_per_queue; if(rx_cleaned_per_queue >= budget_per_queue) { napi_done = 0; } else { gfargrp->rstat_prev &= ~(mask); gfar_write(®s->rstat, rstat_rhalt); } } } if(napi_done) { napi_complete(napi); gfar_configure_rx_coalescing(priv, gfargrp->rx_bit_map); spin_lock_irq(&gfargrp->grplock); imask = gfar_read(®s->imask); imask |= IMASK_DEFAULT_RX; gfar_write(®s->imask, imask); ievent = gfar_read(®s->ievent); ievent &= IEVENT_RX_MASK; if(ievent) { imask = imask & IMASK_RX_DISABLED; gfar_write(&gfargrp->regs->imask, imask); gfar_write(&gfargrp->regs->ievent, IEVENT_RX_MASK); napi_schedule(napi); } spin_unlock_irq(&gfargrp->grplock); } return rx_cleaned; } #else static int gfar_poll(struct napi_struct* napi, int budget) { struct gfar_priv_grp* gfargrp = container_of(napi, struct gfar_priv_grp, napi); struct gfar_private* priv = gfargrp->priv; struct gfar __iomem* regs = gfargrp->regs; struct gfar_priv_tx_q* tx_queue = NULL; struct gfar_priv_rx_q* rx_queue = NULL; int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; int tx_cleaned = 0, i, left_over_budget = budget; unsigned long serviced_queues = 0; int num_queues = 0; num_queues = gfargrp->num_rx_queues; budget_per_queue = budget / num_queues; /* Clear IEVENT, so interrupts aren't called again * because of the packets that have already arrived */ #ifdef CONFIG_GFAR_TX_NONAPI gfar_write(&gfargrp->regs->ievent, IEVENT_RX_MASK); #else gfar_write(®s->ievent, IEVENT_RTX_MASK); #endif while(num_queues && left_over_budget) { budget_per_queue = left_over_budget / num_queues; left_over_budget = 0; for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { if(test_bit(i, &serviced_queues)) { continue; } rx_queue = priv->rx_queue[i]; #ifndef CONFIG_RX_TX_BD_XNGE #ifndef CONFIG_GFAR_TX_NONAPI tx_queue = priv->tx_queue[rx_queue->qindex]; tx_cleaned += gfar_clean_tx_ring(tx_queue); #endif #endif rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue, budget_per_queue); rx_cleaned += rx_cleaned_per_queue; if(rx_cleaned_per_queue < budget_per_queue) { left_over_budget = left_over_budget + (budget_per_queue - rx_cleaned_per_queue); set_bit(i, &serviced_queues); num_queues--; } } } #ifndef CONFIG_RX_TX_BD_XNGE #ifndef CONFIG_GFAR_TX_NONAPI if(tx_cleaned) { return budget; } #endif #endif if(rx_cleaned < budget) { napi_complete(napi); /* Clear the halt bit in RSTAT */ gfar_write(®s->rstat, gfargrp->rstat); gfar_write(®s->imask, IMASK_DEFAULT); /* If we are coalescing interrupts, update the timer */ /* Otherwise, clear it */ gfar_configure_rx_coalescing(priv, gfargrp->rx_bit_map); #ifndef CONFIG_RX_TX_BD_XNGE #ifndef CONFIG_GFAR_TX_NONAPI gfar_configure_tx_coalescing(priv, gfargrp->tx_bit_map); #endif #endif } return rx_cleaned; } #endif #ifdef CONFIG_NET_POLL_CONTROLLER /* * Polling 'interrupt' - used by things like netconsole to send skbs * without having to re-enable interrupts. It's not called while * the interrupt routine is executing. */ static void gfar_netpoll(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); int i = 0; /* If the device has multiple interrupts, run tx/rx */ if(priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { for(i = 0; i < priv->num_grps; i++) { disable_irq(priv->gfargrp[i].interruptTransmit); disable_irq(priv->gfargrp[i].interruptReceive); disable_irq(priv->gfargrp[i].interruptError); gfar_interrupt(priv->gfargrp[i].interruptTransmit, &priv->gfargrp[i]); enable_irq(priv->gfargrp[i].interruptError); enable_irq(priv->gfargrp[i].interruptReceive); enable_irq(priv->gfargrp[i].interruptTransmit); } } else { for(i = 0; i < priv->num_grps; i++) { disable_irq(priv->gfargrp[i].interruptTransmit); gfar_interrupt(priv->gfargrp[i].interruptTransmit, &priv->gfargrp[i]); enable_irq(priv->gfargrp[i].interruptTransmit); } } } #endif /* The interrupt handler for devices with one interrupt */ static irqreturn_t gfar_interrupt(int irq, void* grp_id) { struct gfar_priv_grp* gfargrp = grp_id; /* Save ievent for future reference */ u32 events = gfar_read(&gfargrp->regs->ievent); /* Check for reception */ if(events & IEVENT_RX_MASK) { gfar_receive(irq, grp_id); } /* Check for transmit completion */ if(events & IEVENT_TX_MASK) { gfar_transmit(irq, grp_id); } /* Check for errors */ if(events & IEVENT_ERR_MASK) { gfar_error(irq, grp_id); } return IRQ_HANDLED; } /* Called every time the controller might need to be made * aware of new link state. The PHY code conveys this * information through variables in the phydev structure, and this * function converts those variables into the appropriate * register values, and can bring down the device if needed. */ static void adjust_link(struct net_device* dev) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; unsigned long flags; struct phy_device* phydev = priv->phydev; int new_state = 0; local_irq_save(flags); lock_tx_qs(priv); if(phydev->link) { u32 tempval = gfar_read(®s->maccfg2); u32 ecntrl = gfar_read(®s->ecntrl); /* Now we make sure that we can be in full duplex mode. * If not, we operate in half-duplex mode. */ if(phydev->duplex != priv->oldduplex) { new_state = 1; if(!(phydev->duplex)) { tempval &= ~(MACCFG2_FULL_DUPLEX); } else { tempval |= MACCFG2_FULL_DUPLEX; } priv->oldduplex = phydev->duplex; } if(phydev->speed != priv->oldspeed) { new_state = 1; switch(phydev->speed) { case 1000: tempval = ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); ecntrl &= ~(ECNTRL_R100); break; case 100: case 10: tempval = ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); /* Reduced mode distinguishes * between 10 and 100 */ if(phydev->speed == SPEED_100) { ecntrl |= ECNTRL_R100; } else { ecntrl &= ~(ECNTRL_R100); } break; default: if(netif_msg_link(priv)) printk(KERN_WARNING "%s: Ack! Speed (%d) is not 10/100/1000!\n", dev->name, phydev->speed); break; } priv->oldspeed = phydev->speed; } gfar_write(®s->maccfg2, tempval); gfar_write(®s->ecntrl, ecntrl); if(!priv->oldlink) { new_state = 1; priv->oldlink = 1; } } else if(priv->oldlink) { new_state = 1; priv->oldlink = 0; priv->oldspeed = 0; priv->oldduplex = -1; } if(new_state && netif_msg_link(priv)) { phy_print_status(phydev); } unlock_tx_qs(priv); local_irq_restore(flags); } /* Update the hash table based on the current list of multicast * addresses we subscribe to. Also, change the promiscuity of * the device based on the flags (this function is called * whenever dev->flags is changed */ static void gfar_set_multi(struct net_device* dev) { struct netdev_hw_addr* ha; struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; u32 tempval; if(dev->flags & IFF_PROMISC) { /* Set RCTRL to PROM */ tempval = gfar_read(®s->rctrl); tempval |= RCTRL_PROM; gfar_write(®s->rctrl, tempval); } else { /* Set RCTRL to not PROM */ tempval = gfar_read(®s->rctrl); tempval &= ~(RCTRL_PROM); gfar_write(®s->rctrl, tempval); } if(dev->flags & IFF_ALLMULTI) { /* Set the hash to rx all multicast frames */ gfar_write(®s->igaddr0, 0xffffffff); gfar_write(®s->igaddr1, 0xffffffff); gfar_write(®s->igaddr2, 0xffffffff); gfar_write(®s->igaddr3, 0xffffffff); gfar_write(®s->igaddr4, 0xffffffff); gfar_write(®s->igaddr5, 0xffffffff); gfar_write(®s->igaddr6, 0xffffffff); gfar_write(®s->igaddr7, 0xffffffff); gfar_write(®s->gaddr0, 0xffffffff); gfar_write(®s->gaddr1, 0xffffffff); gfar_write(®s->gaddr2, 0xffffffff); gfar_write(®s->gaddr3, 0xffffffff); gfar_write(®s->gaddr4, 0xffffffff); gfar_write(®s->gaddr5, 0xffffffff); gfar_write(®s->gaddr6, 0xffffffff); gfar_write(®s->gaddr7, 0xffffffff); } else { int em_num; int idx; /* zero out the hash */ gfar_write(®s->igaddr0, 0x0); gfar_write(®s->igaddr1, 0x0); gfar_write(®s->igaddr2, 0x0); gfar_write(®s->igaddr3, 0x0); gfar_write(®s->igaddr4, 0x0); gfar_write(®s->igaddr5, 0x0); gfar_write(®s->igaddr6, 0x0); gfar_write(®s->igaddr7, 0x0); gfar_write(®s->gaddr0, 0x0); gfar_write(®s->gaddr1, 0x0); gfar_write(®s->gaddr2, 0x0); gfar_write(®s->gaddr3, 0x0); gfar_write(®s->gaddr4, 0x0); gfar_write(®s->gaddr5, 0x0); gfar_write(®s->gaddr6, 0x0); gfar_write(®s->gaddr7, 0x0); /* If we have extended hash tables, we need to * clear the exact match registers to prepare for * setting them */ if(priv->extended_hash) { em_num = GFAR_EM_NUM + 1; gfar_clear_exact_match(dev); idx = 1; } else { idx = 0; em_num = 0; } if(netdev_mc_empty(dev)) { return; } /* Parse the list, and set the appropriate bits */ netdev_for_each_mc_addr(ha, dev) { if(idx < em_num) { gfar_set_mac_for_addr(dev, idx, ha->addr); idx++; } else { gfar_set_hash_for_addr(dev, ha->addr); } } } } /* Clears each of the exact match registers to zero, so they * don't interfere with normal reception */ static void gfar_clear_exact_match(struct net_device* dev) { int idx; u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0}; for(idx = 1; idx < GFAR_EM_NUM + 1; idx++) { gfar_set_mac_for_addr(dev, idx, (u8*)zero_arr); } } /* Set the appropriate hash bit for the given addr */ /* The algorithm works like so: * 1) Take the Destination Address (ie the multicast address), and * do a CRC on it (little endian), and reverse the bits of the * result. * 2) Use the 8 most significant bits as a hash into a 256-entry * table. The table is controlled through 8 32-bit registers: * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is * gaddr7. This means that the 3 most significant bits in the * hash index which gaddr register to use, and the 5 other bits * indicate which bit (assuming an IBM numbering scheme, which * for PowerPC (tm) is usually the case) in the register holds * the entry. */ static void gfar_set_hash_for_addr(struct net_device* dev, u8* addr) { u32 tempval; struct gfar_private* priv = netdev_priv(dev); u32 result = ether_crc(MAC_ADDR_LEN, addr); int width = priv->hash_width; u8 whichbit = (result >> (32 - width)) & 0x1f; u8 whichreg = result >> (32 - width + 5); u32 value = (1 << (31 - whichbit)); tempval = gfar_read(priv->hash_regs[whichreg]); tempval |= value; gfar_write(priv->hash_regs[whichreg], tempval); } /* There are multiple MAC Address register pairs on some controllers * This function sets the numth pair to a given address */ static void gfar_set_mac_for_addr(struct net_device* dev, int num, u8* addr) { struct gfar_private* priv = netdev_priv(dev); struct gfar __iomem* regs = priv->gfargrp[0].regs; int idx; char tmpbuf[MAC_ADDR_LEN]; u32 tempval; u32 __iomem* macptr = ®s->macstnaddr1; macptr += num * 2; /* Now copy it into the mac registers backwards, cuz */ /* little endian is silly */ for(idx = 0; idx < MAC_ADDR_LEN; idx++) { tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; } gfar_write(macptr, *((u32*)(tmpbuf))); tempval = *((u32*)(tmpbuf + 4)); gfar_write(macptr + 1, tempval); } /* GFAR error interrupt handler */ static irqreturn_t gfar_error(int irq, void* grp_id) { struct gfar_priv_grp* gfargrp = grp_id; struct gfar __iomem* regs = gfargrp->regs; struct gfar_private* priv = gfargrp->priv; struct net_device* dev = priv->ndev; /* Save ievent for future reference */ u32 events = gfar_read(®s->ievent); /* Clear IEVENT */ gfar_write(®s->ievent, events & IEVENT_ERR_MASK); /* Magic Packet is not an error. */ if((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && (events & IEVENT_MAG)) { events &= ~IEVENT_MAG; } /* Hmm... */ if(netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", dev->name, events, gfar_read(®s->imask)); /* Update the error counters */ if(events & IEVENT_TXE) { dev->stats.tx_errors++; if(events & IEVENT_LC) { dev->stats.tx_window_errors++; } if(events & IEVENT_CRL) { dev->stats.tx_aborted_errors++; } if(events & IEVENT_XFUN) { unsigned long flags; if(netif_msg_tx_err(priv)) printk(KERN_DEBUG "%s: TX FIFO underrun, " "packet dropped.\n", dev->name); dev->stats.tx_dropped++; priv->extra_stats.tx_underrun++; local_irq_save(flags); lock_tx_qs(priv); /* Reactivate the Tx Queues */ gfar_write(®s->tstat, gfargrp->tstat); unlock_tx_qs(priv); local_irq_restore(flags); } if(netif_msg_tx_err(priv)) { printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); } } if(events & IEVENT_BSY) { dev->stats.rx_errors++; priv->extra_stats.rx_bsy++; gfar_receive(irq, grp_id); if(netif_msg_rx_err(priv)) printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", dev->name, gfar_read(®s->rstat)); } if(events & IEVENT_BABR) { dev->stats.rx_errors++; priv->extra_stats.rx_babr++; if(netif_msg_rx_err(priv)) { printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); } } if(events & IEVENT_EBERR) { priv->extra_stats.eberr++; if(netif_msg_rx_err(priv)) { printk(KERN_DEBUG "%s: bus error\n", dev->name); } } if((events & IEVENT_RXC) && netif_msg_rx_status(priv)) { printk(KERN_DEBUG "%s: control frame\n", dev->name); } if(events & IEVENT_BABT) { priv->extra_stats.tx_babt++; if(netif_msg_tx_err(priv)) { printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); } } return IRQ_HANDLED; } static struct of_device_id gfar_match[] = { { .type = "network", .compatible = "gianfar", }, { .compatible = "fsl,etsec2", }, {}, }; MODULE_DEVICE_TABLE(of, gfar_match); /* Structure for a device driver */ static struct of_platform_driver gfar_driver = { .driver = { .name = "fsl-gianfar", .owner = THIS_MODULE, .pm = GFAR_PM_OPS, .of_match_table = gfar_match, }, .probe = gfar_probe, .remove = gfar_remove, }; static int __init gfar_init(void) { #ifdef CONFIG_GFAR_SW_PKT_STEERING gfar_cpu_dev_init(); #endif gfar_1588_proc_init(gfar_match, sizeof(gfar_match)); return of_register_platform_driver(&gfar_driver); } static void __exit gfar_exit(void) { #ifdef CONFIG_GFAR_SW_PKT_STEERING gfar_cpu_dev_exit(); #endif gfar_1588_proc_exit(); of_unregister_platform_driver(&gfar_driver); } module_init(gfar_init); module_exit(gfar_exit);