#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/dma-mapping.h>
#include <linux/mm.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/of_spi.h>
#include <linux/slab.h>

#include <asm/cpm.h>
#include <asm/qe.h>
#include <asm/irq.h>
#include "spi_mpc.h"

#define USB_GPIO_MASK   (0x3<<18)
#define USB_GPIO_VALUE  (0x2<<18)
#define USB_GPIO_37     (1<<(31-(37-32)))
#define USB_GPIO_38     (1<<(31-(38-32)))
#define USB_GPIO_39     (1<<(31-(39-32)))

static int spi_loop = 0;
module_param(spi_loop, int, S_IRUGO);
MODULE_PARM_DESC(spi_loop, "SPI LOOP MODE");

extern u32 fsl_get_sys_freq(void);
extern u32 get_brgfreq(void);

static struct spi_master* g_master;
struct gpio_struct* g_pGPIORegs = NULL;

struct spi_master* get_spi_master(void)
{
    return g_master;
}

EXPORT_SYMBOL(get_spi_master);

void spi_reg_dump(void)
{
    static int i = 0;
    uint32_t base = (uint32_t)ioremap(0xe0007000, GFP_KERNEL);

    uint32_t buf[6];
    buf[0] = in_be32((u32*)(base + 0));
    buf[1] = in_be32((u32*)(base + 4));
    buf[2] = in_be32((u32*)(base + 8));
    buf[3] = in_be32((u32*)(base + 12));
    buf[4] = in_be32((u32*)(base + 16));
    buf[5] = in_be32((u32*)(base + 20));

    printk("spi->base = 0x%x,num:%d\n", base, i++);
    printk("spi->mode = 0x%x\n", buf[0]);
    printk("spi->event = 0x%x\n", buf[1]);
    printk("spi->mask = 0x%x\n", buf[2]);
    printk("spi->command = 0x%x\n", buf[3]);
    printk("spi->transmit = 0x%x\n", buf[4]);
    printk("spi->receive = 0x%x\n", buf[5]);

    iounmap((void*)base);
}

static inline void mpc8xxx_spi_write_reg(__be32 __iomem* reg, u32 val)
{
    out_be32(reg, val);
}

static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem* reg)
{
    return in_be32(reg);
}

MPC83XX_SPI_RX_BUF(u8)
MPC83XX_SPI_RX_BUF(u16)
MPC83XX_SPI_RX_BUF(u32)
MPC83XX_SPI_TX_BUF(u8)
MPC83XX_SPI_TX_BUF(u16)
MPC83XX_SPI_TX_BUF(u32)

static void mpc8xxx_spi_change_mode(struct spi_device* spi)
{
    struct mpc8xxx_spi* mspi = spi_master_get_devdata(spi->master);
    struct spi_mpc8xxx_cs* cs = spi->controller_state;
    __be32 __iomem* mode = &mspi->base->mode;
    unsigned long flags;

    if(cs->hw_mode == mpc8xxx_spi_read_reg(mode))
    {
        return;
    }

    /* Turn off IRQs locally to minimize time that SPI is disabled. */
    local_irq_save(flags);

    /* Turn off SPI unit prior changing mode */
    mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
    mpc8xxx_spi_write_reg(mode, cs->hw_mode);
    local_irq_restore(flags);
}

static
int mpc8xxx_spi_setup_transfer(struct spi_device* spi, struct spi_transfer* t)
{
    struct mpc8xxx_spi* mpc8xxx_spi;
    u8 bits_per_word, pm;
    u32 hz;
    struct spi_mpc8xxx_cs*   cs = spi->controller_state;

    mpc8xxx_spi = spi_master_get_devdata(spi->master);

    if(t)
    {
        bits_per_word = t->bits_per_word;
        hz = t->speed_hz;
    }
    else
    {
        bits_per_word = 0;
        hz = 0;
    }

    /* spi_transfer level calls that work per-word */
    if(!bits_per_word)
    {
        bits_per_word = spi->bits_per_word;
    }

    /* Make sure its a bit width we support [4..16, 32] */
    if((bits_per_word < 4)
       || ((bits_per_word > 16) && (bits_per_word != 32)))
    {
        return -EINVAL;
    }

    if(!hz)
    {
        hz = spi->max_speed_hz;
    }

    cs->rx_shift = 0;
    cs->tx_shift = 0;

    if(bits_per_word <= 8)
    {
        cs->get_rx = mpc8xxx_spi_rx_buf_u8;
        cs->get_tx = mpc8xxx_spi_tx_buf_u8;
    }
    else if(bits_per_word <= 16)
    {
        cs->get_rx = mpc8xxx_spi_rx_buf_u16;
        cs->get_tx = mpc8xxx_spi_tx_buf_u16;
    }
    else if(bits_per_word <= 32)
    {
        cs->get_rx = mpc8xxx_spi_rx_buf_u32;
        cs->get_tx = mpc8xxx_spi_tx_buf_u32;
    }
    else
    {
        return -EINVAL;
    }

    mpc8xxx_spi->rx_shift = cs->rx_shift;
    mpc8xxx_spi->tx_shift = cs->tx_shift;
    mpc8xxx_spi->get_rx = cs->get_rx;
    mpc8xxx_spi->get_tx = cs->get_tx;

    if(bits_per_word == 32)
    {
        bits_per_word = 0;
    }
    else
    {
        bits_per_word = bits_per_word - 1;
    }

    /* mask out bits we are going to set */
    cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
                     | SPMODE_PM(0xF));

    cs->hw_mode |= SPMODE_LEN(bits_per_word);


    if((mpc8xxx_spi->spibrg / hz) > 64)
    {
        cs->hw_mode |= SPMODE_DIV16;
        pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;

        WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
                  "Will use %d Hz instead.\n", dev_name(&spi->dev),
                  hz, mpc8xxx_spi->spibrg / 1024);

        if(pm > 16)
        {
            pm = 16;
        }
    }
    else
    {
        pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
    }

    if(pm)
    {
        pm--;
    }

    cs->hw_mode |= SPMODE_PM(pm);

    mpc8xxx_spi_change_mode(spi);

    return 0;
}

static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi* mspi,
                                struct spi_transfer* t, unsigned int len)
{
    u32 word;

    mspi->count = len;

    /* enable rx ints */
    mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
    /* transmit word */
    word = mspi->get_tx(mspi);
    mpc8xxx_spi_write_reg(&mspi->base->transmit, word);

    return 0;
}

void spi_cs_sel(void)
{
    uint32_t value;
    struct gpio_struct* gpio_reg = g_pGPIORegs;

    value = in_be32(&gpio_reg->dat);
    value  &= ~(USB_GPIO_37);
    out_be32(&gpio_reg->dat, value);

}

void spi_cs_unsel(void)
{
    uint32_t value;
    struct gpio_struct* gpio_reg = g_pGPIORegs;

    value = in_be32(&gpio_reg->dat);
    value  |= USB_GPIO_37;
    out_be32(&gpio_reg->dat, value);
}

int spi_cs_init(void)
{
    u32 value;
    u32* ptr;
    struct gpio_struct* gpio_reg;

    ptr = (u32*)ioremap(0xe0000118, 4);     // SICR_2  GPIO[32:39] is select
    value = in_be32(ptr);
    value = (value & (~USB_GPIO_MASK)) | (USB_GPIO_VALUE);
    out_be32(ptr, value);
    value = in_be32(ptr);
//printk("SICR_2 = 0x%x\n",value);
    iounmap(ptr);

    ptr = (u32*)ioremap(0xe0000150, 0x4);  //GPR_1 GPIO[32:39] is mult with USB
    value = in_be32(ptr);
    value |= (1 << 5);
    out_be32(ptr, value);
    value = in_be32(ptr);
//printk("%s:GPR_1 = 0x%x\n",__func__,value);
    iounmap(ptr);

    gpio_reg = (struct gpio_struct*)ioremap(0xe0000d00, 0x14); //GR2DIR
    g_pGPIORegs = gpio_reg;

    value = in_be32(&gpio_reg->dir);
    value  |=  USB_GPIO_37;
    out_be32(&gpio_reg->dir, value);

    value = in_be32(&gpio_reg->dat);
    value  |= USB_GPIO_37;
    out_be32(&gpio_reg->dat, value);

    return 0;
}

void spi_cs_exit(void)
{
    iounmap(g_pGPIORegs);
}

static int mpc8xxx_spi_bufs(struct spi_device* spi, struct spi_transfer* t,
                            bool is_dma_mapped)
{
    struct mpc8xxx_spi* mpc8xxx_spi = spi_master_get_devdata(spi->master);
    unsigned int len = t->len;
    u8 bits_per_word;
    int ret;

    bits_per_word = spi->bits_per_word;

    mpc8xxx_spi->tx = t->tx_buf;
    mpc8xxx_spi->rx = t->rx_buf;

    INIT_COMPLETION(mpc8xxx_spi->done);

    spi_cs_sel();

    ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);

    if(ret)
    {
        return ret;
    }

    wait_for_completion(&mpc8xxx_spi->done);

    spi_cs_unsel();
    /* disable rx ints */
    mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
    return mpc8xxx_spi->count;
}

static void mpc8xxx_spi_do_one_msg(struct spi_message* m)
{
    struct spi_device* spi = m->spi;
    struct spi_transfer* t;
    unsigned int cs_change;
    int status;

    cs_change = 1;
    status = 0;

    list_for_each_entry(t, &m->transfers, transfer_list)
    {
        if(t->len)
        {
            status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
        }

        if(status)
        {
            status = -EMSGSIZE;
            break;
        }

        m->actual_length += t->len;

    }

    m->status = status;
    m->complete(m->context);

    // FIXED @SJM20130226
    mpc8xxx_spi_setup_transfer(spi, NULL);
}

static void mpc8xxx_spi_work(struct work_struct* work)
{
    struct mpc8xxx_spi* mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
                                                   work);

    spin_lock_irq(&mpc8xxx_spi->lock);

    while(!list_empty(&mpc8xxx_spi->queue))
    {
        struct spi_message* m = container_of(mpc8xxx_spi->queue.next,
                                             struct spi_message, queue);

        list_del_init(&m->queue);
        spin_unlock_irq(&mpc8xxx_spi->lock);

        mpc8xxx_spi_do_one_msg(m);

        spin_lock_irq(&mpc8xxx_spi->lock);
    }

    spin_unlock_irq(&mpc8xxx_spi->lock);
}

static int mpc8xxx_spi_setup(struct spi_device* spi)
{
    struct mpc8xxx_spi* mpc8xxx_spi;
    int retval;
    u32 hw_mode;
    struct spi_mpc8xxx_cs*   cs = spi->controller_state;

    if(!spi->max_speed_hz)
    {
        return -EINVAL;
    }

    if(!cs)
    {
        cs = kzalloc(sizeof * cs, GFP_KERNEL);

        if(!cs)
        {
            return -ENOMEM;
        }

        spi->controller_state = cs;
    }

    mpc8xxx_spi = spi_master_get_devdata(spi->master);

    hw_mode = cs->hw_mode; /* Save orginal settings */
    cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
    /* mask out bits we are going to set */
    cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
                     | SPMODE_REV | SPMODE_LOOP);

    /* cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
     cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;*/
    cs->hw_mode |= SPMODE_REV;

    if(spi_loop == 1)
    {
        cs->hw_mode |= SPMODE_LOOP;
    }


    retval = mpc8xxx_spi_setup_transfer(spi, NULL);

    if(retval < 0)
    {
        cs->hw_mode = hw_mode; /* Restore settings */
        printk("%s:spi setup transfer err\n", __func__);
        return retval;
    }

    return 0;
}

static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi* mspi, u32 events)
{
    /* We need handle RX first */

    if(events & SPIE_NE)
    {
        u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);

        if(mspi->rx)
        {
            mspi->get_rx(rx_data, mspi);
        }
    }

    if((events & SPIE_NF) == 0)

        /* spin until TX is done */
        while(((events =
                    mpc8xxx_spi_read_reg(&mspi->base->event)) &
               SPIE_NF) == 0)
        {
            cpu_relax();
        }

    /* Clear the events */
    mpc8xxx_spi_write_reg(&mspi->base->event, events);

    mspi->count -= 1;

    if(mspi->count)
    {
        u32 word = mspi->get_tx(mspi);
        mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
    }
    else
    {
        complete(&mspi->done);
    }

}

static irqreturn_t mpc8xxx_spi_irq(s32 irq, void* context_data)
{
    struct mpc8xxx_spi* mspi = context_data;
    irqreturn_t ret = IRQ_NONE;
    u32 events;

    /* Get interrupt events(tx/rx) */
    events = mpc8xxx_spi_read_reg(&mspi->base->event);

    if(events)
    {
        ret = IRQ_HANDLED;
    }

    mpc8xxx_spi_cpu_irq(mspi, events);
    return ret;
}

static int mpc8xxx_spi_transfer(struct spi_device* spi, struct spi_message* m)
{
    struct mpc8xxx_spi* mpc8xxx_spi = spi_master_get_devdata(spi->master);
    unsigned long flags;

    m->actual_length = 0;
    m->status = -EINPROGRESS;

    spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
    list_add_tail(&m->queue, &mpc8xxx_spi->queue);
    queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
    spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);

    return 0;
}


static void mpc8xxx_spi_cleanup(struct spi_device* spi)
{
    kfree(spi->controller_state);
}

static const char* mpc8xxx_spi_strmode(unsigned int flags)
{
    if(flags & SPI_QE_CPU_MODE)
    {
        return "QE CPU";
    }
    else if(flags & SPI_CPM_MODE)
    {
        if(flags & SPI_QE)
        {
            return "QE";
        }
        else if(flags & SPI_CPM2)
        {
            return "CPM2";
        }
        else
        {
            return "CPM1";
        }
    }

    return "CPU";
}

static struct spi_master* __devinit
mpc8xxx_spi_probe(struct device* dev, struct resource* mem, unsigned int irq)
{
    struct fsl_spi_platform_data* pdata = dev->platform_data;
    struct spi_master* master;
    struct mpc8xxx_spi* mpc8xxx_spi;
    u32 regval;
    int ret = 0;


    master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));

    if(master == NULL)
    {
        ret = -ENOMEM;
        goto err;
    }

    dev_set_drvdata(dev, master);

    master->setup = mpc8xxx_spi_setup;
    master->transfer = mpc8xxx_spi_transfer;
    master->cleanup = mpc8xxx_spi_cleanup;

    mpc8xxx_spi = spi_master_get_devdata(master);
    mpc8xxx_spi->dev = dev;
    mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
    mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
    mpc8xxx_spi->flags = pdata->flags;
    mpc8xxx_spi->spibrg = pdata->sysclk;
    mpc8xxx_spi->rx_shift = 0;
    mpc8xxx_spi->tx_shift = 0;

    init_completion(&mpc8xxx_spi->done);


    mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));

    if(mpc8xxx_spi->base == NULL)
    {
        ret = -ENOMEM;
        goto err_ioremap;
    }

    mpc8xxx_spi->irq = irq;

    /* Register for SPI Interrupt */
    ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
                      0, "mpc8xxx_spi", mpc8xxx_spi);

    if(ret != 0)
    {
        goto unmap_io;
    }

    master->bus_num = 0x7000;

    master->num_chipselect = pdata->max_chipselect;

    /* SPI controller initializations */
    mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
    mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
    mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
    mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);

    /* Enable SPI interface */

    if(spi_loop == 1)
    {
        regval =  SPMODE_INIT_VAL | SPMODE_ENABLE | SPMODE_LOOP;
    }
    else
    {
        regval =  SPMODE_INIT_VAL | SPMODE_ENABLE;
    }

    mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
    spin_lock_init(&mpc8xxx_spi->lock);
    init_completion(&mpc8xxx_spi->done);
    INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
    INIT_LIST_HEAD(&mpc8xxx_spi->queue);

    mpc8xxx_spi->workqueue = create_singlethread_workqueue(
                                 dev_name(master->dev.parent));

    if(mpc8xxx_spi->workqueue == NULL)
    {
        ret = -EBUSY;
        goto free_irq;
    }

    ret = spi_register_master(master);

    if(ret < 0)
    {
        goto unreg_master;
    }

    dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
             mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));

    g_master = master;
    return master;

unreg_master:
    destroy_workqueue(mpc8xxx_spi->workqueue);
free_irq:
    free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
unmap_io:
    iounmap(mpc8xxx_spi->base);
err_ioremap:
    spi_master_put(master);
err:
    return ERR_PTR(ret);
}

static int __devexit mpc8xxx_spi_remove(struct device* dev)
{
    struct mpc8xxx_spi* mpc8xxx_spi;
    struct spi_master* master;

    master = dev_get_drvdata(dev);
    mpc8xxx_spi = spi_master_get_devdata(master);

    flush_workqueue(mpc8xxx_spi->workqueue);
    destroy_workqueue(mpc8xxx_spi->workqueue);

    spi_unregister_master(master);

    free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
    iounmap(mpc8xxx_spi->base);

    return 0;
}

struct mpc8xxx_spi_probe_info
{
    struct fsl_spi_platform_data pdata;
};

static int __devinit of_mpc8xxx_spi_probe(struct of_device* ofdev,
                                          const struct of_device_id* ofid)
{
    struct device* dev = &ofdev->dev;
    struct device_node* np = ofdev->node;
    struct mpc8xxx_spi_probe_info* pinfo;
    struct fsl_spi_platform_data* pdata;
    struct spi_master* master;
    struct resource mem;
    struct resource irq;
    const void* prop;
    int ret = -ENOMEM;

    pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);

    if(!pinfo)
    {
        return -ENOMEM;
    }

    pdata = &pinfo->pdata;
    dev->platform_data = pdata;

    /* Allocate bus num dynamically. */
    pdata->bus_num = -1;

    /* SPI controller is either clocked from QE or SoC clock. */
    pdata->sysclk = get_brgfreq();

    if(pdata->sysclk == -1)
    {
        pdata->sysclk = fsl_get_sys_freq();

        if(pdata->sysclk == -1)
        {
            ret = -ENODEV;
            goto err_clk;
        }
    }

    prop = of_get_property(np, "mode", NULL);
    pdata->max_chipselect = 5;
    ret = of_address_to_resource(np, 0, &mem);

    if(ret)
    {
        goto err;
    }

    ret = of_irq_to_resource(np, 0, &irq);

    if(!ret)
    {
        ret = -EINVAL;
        goto err;
    }

    master = mpc8xxx_spi_probe(dev, &mem, irq.start);

    if(IS_ERR(master))
    {
        ret = PTR_ERR(master);
        goto err;
    }

    of_register_spi_devices(master, np);

    return 0;

err:
err_clk:
    kfree(pinfo);
    return ret;
}

static int __devexit of_mpc8xxx_spi_remove(struct of_device* ofdev)
{
    return  mpc8xxx_spi_remove(&ofdev->dev);
}

static const struct of_device_id of_mpc8xxx_spi_match[] =
{
    { .compatible = "fsl,spi" },
    {},
};

static struct of_platform_driver of_mpc8xxx_spi_driver =
{
    .name       = "mpc8xxx_spi",
    .match_table    = of_mpc8xxx_spi_match,
    .probe      = of_mpc8xxx_spi_probe,
    .remove     = __devexit_p(of_mpc8xxx_spi_remove),
};

int mpc_spi_init(void)
{
    int rv = 0;

    spi_cs_init();
    rv = of_register_platform_driver(&of_mpc8xxx_spi_driver);

    if(rv)
    {
        printk(" of_register_platform_driver failed (%i)\n", rv);
    }

    return rv;
}

void mpc_spi_exit(void)
{
    of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
    spi_cs_exit();
}