/*
 * P1010 RDB Device Tree Source
 *
 * Copyright 2010-2011 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "fsl,P1010";
	compatible = "fsl,P1010RDB";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,P1010@0 {
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
	};

	ifc@ffe1e000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,ifc", "simple-bus";
		reg = <0x0 0xffe1e000 0 0x2000>;
		interrupts = <16 2 19 2>;
		interrupt-parent = <&mpic>;

		/* NOR, NAND Flashes and CPLD on board */
/*
		ranges = <0x0 0x0 0x0 0xee000000 0x02000000
			        0x1 0x0 0x0 0xff800000 0x00010000
			        0x3 0x0 0x0 0xffb00000 0x00100000>;
*/

		ranges = <0x0 0x0 0x0 0xff800000 0x00010000
	            0x3 0x0 0x0 0xffb00000 0x00100000>;

		nand@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,ifc-nand";
			reg = <0x0 0x0 0x10000>;

			partition@0 {
				/* This location must not be altered  */
				/* 1MB for u-boot Bootloader Image */
				reg = <0x0 0x00100000>;
				label = "NAND U-Boot Image";
			};

			partition@100000 {
				/* 1MB for DTB Image */
				reg = <0x00100000 0x00100000>;
				label = "NAND DTB Image";
			};

			partition@200000 {
				/* 4MB for Linux Kernel Image */
				reg = <0x00200000 0x00400000>;
				label = "NAND Linux Kernel Image";
			};

			partition@a00000 {
				// 16MB for Compressed Root file System Image 
				reg = <0x00a00000 0x01000000>;
				label = "NAND Compressed RFS Image";
			};
/*
			partition@a00000 {
				// 15MB for JFFS2 based Root file System 
				reg = <0x00a00000 0x00f00000>;
				label = "NAND JFFS2 Root File System";
			};

			partition@1900000 {
				// 7MB for User Area 
				reg = <0x01900000 0x00700000>;
				label = "NAND User area";
			};
*/
		};

		cpld@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,p1010rdb-cpld";
			reg = <0x3 0x0 0x0100000>;
			bank-width = <1>;
			device-width = <1>;
		};

	};

	soc@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,p1020-immr", "simple-bus";
		ranges = <0x0  0x0 0xffe00000 0x100000>;
		bus-frequency = <0>;		// Filled out by uboot.

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <12>;
		};

		ecm@1000 {
			compatible = "fsl,p1020-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <16 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,p1020-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};
/*
		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};
*/
		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

/*

		spi@7000 {
			cell-index = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,espi";
			reg = <0x7000 0x1000>;
			interrupts = <59 0x2>;
			interrupt-parent = <&mpic>;
			espi,num-ss-bits = <4>;
			mode = "cpu";

			fsl_m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,espi-flash","spansion,s25sl12801";
				reg = <0>;
				linux,modalias = "fsl_m25p80";
				modal = "s25sl128b";
				spi-max-frequency = <50000000>;
				mode = <0>;

				partition@0 {
					// 512KB for u-boot Bootloader Image
					reg = <0x0 0x00080000>;
					label = "SPI (RO) U-Boot Image";
					read-only;
				};

				partition@80000 {
					// 512KB for DTB Image 
					reg = <0x00080000 0x00080000>;
					label = "SPI (RO) DTB Image";
					read-only;
				};

				partition@100000 {
					// 4MB for Linux Kernel Image
					reg = <0x00100000 0x00400000>;
					label = "SPI (RO) Linux Kernel Image";
					read-only;
				};

				partition@500000 {
					// 4MB for Compressed RFS Image
					reg = <0x00500000 0x00400000>;
					label = "SPI (RO) Compressed RFS Image";
					read-only;
				};

				partition@900000 {
					// 7MB for JFFS2 based RFS 
					reg = <0x00900000 0x00700000>;
					label = "SPI (RW) JFFS2 RFS";
				};
			};

// If SPI flash node exists legerity cannot be in device tree because both
// are sitting at same CS #0
// either legerity or SPI flash node will be deleted by u-boot fixup at runtime.
			legerity@0{
				compatible = "fsl,espi-slic","zarlink,le88266";
				reg = <0>;
				linux,modalias = "legerity";
				spi-max-frequency = <8000000>;
				ch1-rx-slot = <0>;
				ch1-tx-slot = <0>;
				ch2-rx-slot = <2>;
				ch2-tx-slot = <2>;
			};
		};
*/
		gpio: gpio-controller@f000 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8572-gpio";
			reg = <0xf000 0x100>;
			interrupts = <47 0x2>;
			interrupt-parent = <&mpic>;
			gpio-controller;
		};

		tdm@16000 {
			device_type = "tdm";
			compatible = "fsl,starlite-tdm";
			reg = <0x16000 0x200 0x2c000 0x2000>;
			clock-frequency = <0>;
			interrupts = <16 8 62 8>;
			interrupt-parent = < &mpic >;
		};

		sata@18000 {
			compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			cell-index = <1>;
			interrupts = <74 0x2>;
			interrupt-parent = <&mpic>;
		};

		sata@19000 {
			compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			cell-index = <2>;
			interrupts = <41 0x2>;
			interrupt-parent = <&mpic>;
		};
/*
		can0@1c000 {
			compatible = "fsl,flexcan-v1.0";
			reg = <0x1c000 0x1000>;
			interrupts = <48 0x2>;
			interrupt-parent = <&mpic>;
			fsl,flexcan-clock-source = <1>;
			fsl,flexcan-clock-divider = <2>;
		};

		can1@1d000 {
			compatible = "fsl,flexcan-v1.0";
			reg = <0x1d000 0x1000>;
			interrupts = <61 0x2>;
			interrupt-parent = <&mpic>;
			fsl,flexcan-clock-source = <1>;
			fsl,flexcan-clock-divider = <2>;
		};
*/

		L2: l2-cache-controller@20000 {
			compatible = "fsl,p1020-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>; // L2,256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};


		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};


		mdio@24000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-mdio";
			reg = <0x24000 0x1000 0xb0030 0x4>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <3 1>;
				reg = <0x00>;
			};

			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
			//	interrupts = <2 1>;
				reg = <0x02>;
			};

			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
			//	interrupts = <2 1>;
				reg = <0x01>;
			};
			
		};

		mdio@25000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-tbi";
			reg = <0x25000 0x1000 0xb1030 0x4>;

			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@26000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-tbi";
			reg = <0x26000 0x1000 0xb1030 0x4>;

			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};


		ptp_timer: ptimer@b0e00 {
			compatible = "fsl,gianfar-ptp-timer";
			reg = <0xb0e00 0xb0>;
			interrupts = <68 2 69 2 70 2>;
			interrupt-parent = <&mpic>;
			tmr-prsc = <0x2>;
			cksel = <1>;
		};
/*
		usb@22000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-usb2-dr";
			reg = <0x22000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <28 0x2>;
			dr_mode = "host";
			phy_type = "utmi";
		};
*/

		crypto: crypto@30000 {
			compatible = "fsl,p4080-sec4.0", "fsl,sec4.0";
			#address-cells = <1>;
			#size-cells = <1>;
			reg		 = <0x30000 0x10000>;
			interrupts	 = <58 2>;
			interrupt-parent = <&mpic>;

			sec_jr0: jr@1000 {
				compatible = "fsl,p4080-sec4.0-job-ring", "fsl,sec4.0-job-ring";
				reg	   = <0x1000 0x1000>;
				interrupts	 = <45 2>;
				interrupt-parent = <&mpic>;
			};

			sec_jr1: jr@2000 {
				compatible = "fsl,p4080-sec4.0-job-ring", "fsl,sec4.0-job-ring";
				reg	   = <0x2000 0x1000>;
				interrupts	 = <45 2>;
				interrupt-parent = <&mpic>;
			};

			sec_jr2: jr@3000 {
				compatible = "fsl,p4080-sec4.0-job-ring", "fsl,sec4.0-job-ring";
				reg	   = <0x3000 0x1000>;
				interrupts	 = <45 2>;
				interrupt-parent = <&mpic>;
			};

			sec_jr3: jr@4000 {
				compatible = "fsl,p4080-sec4.0-job-ring", "fsl,sec4.0-job-ring";
				reg	   = <0x4000 0x1000>;
				interrupts	 = <45 2>;
				interrupt-parent = <&mpic>;
			};
		};
		
		enet0: ethernet@b2000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,index = <0x00>;
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
			tbi-handle = <&tbi1>;
			phy-connection-type = "sgmii";
			#fixed-link = <2 2 100 1 1>;
			ptimer-handle = < &ptp_timer >;
			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb2000 0x1000>;
				rx-bit-map = <0xff>;
				tx-bit-map = <0xff>;
				interrupts = <31 2 32 2 33 2>;
			};

		};

		enet1: ethernet@b0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,index = <0x01>;
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";

			ptimer-handle = < &ptp_timer >;
			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb0000 0x1000>;
				rx-bit-map = <0xff>;
				tx-bit-map = <0xff>;
				interrupts = <29 2 30 2 34 2>;
			};
		};
		
		enet2: ethernet@b1000 {
			#address-cells = <1>;
			#size-cells = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,index = <0x02>;
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			tbi-handle = <&tbi0>;
			phy-connection-type = "sgmii";
			#fixed-link = <1 1 100 0 0>;
			ptimer-handle = < &ptp_timer >;
			queue-group@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xb1000 0x1000>;
				rx-bit-map = <0xff>;
				tx-bit-map = <0xff>;
				interrupts = <35 2 36 2 40 2>;
			};
		};

		sdhci@2e000 {
			compatible = "fsl,p1020-esdhc", "fsl,esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <72 0x2>;
			interrupt-parent = <&mpic>;
			fsl,sdhci-auto-cmd12;
			fsl,sdhci-adma-broken;
			fsl,sdhci-adjust-timeout;
			fsl,sdhci-relax-freq;
			// Filled in by U-Boot 
			clock-frequency = <0>;
		};


		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		message@41400 {
			compatible = "fsl,p1020-msg", "fsl,mpic-msg";
			reg = <0x41400 0x200>;
			interrupts = <
				0xb0 2
				0xb1 2
				0xb2 2
				0xb3 2>;
			interrupt-parent = <&mpic>;
		};

		message@42400 {
			compatible = "fsl,p1020-msg", "fsl,mpic-msg";
			reg = <0x42400 0x200>;
			interrupts = <
				0xb4 2
				0xb5 2
				0xb6 2
				0xb7 2>;
			interrupt-parent = <&mpic>;
		};
		
		timer@41100 {
			compatible = "fsl,mpic-global-timer";
			reg = <0x41100 0x204>;
			interrupts = <0xf7 0x2>;
			interrupt-parent = <&mpic>;
		};

		msi@41600 {
			compatible = "fsl,p1020-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,p2020-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@ffe09000 {
		cell-index = <1>;
		compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0 0xffe09000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <16 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			// IDSEL 0x0 
			0000 0x0 0x0 0x1 &mpic 0x4 0x1
			0000 0x0 0x0 0x2 &mpic 0x5 0x1
			0000 0x0 0x0 0x3 &mpic 0x6 0x1
			0000 0x0 0x0 0x4 &mpic 0x7 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		cell-index = <2>;
		compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0 0xffe0a000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <16 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			// IDSEL 0x0 
			0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0000 0x0 0x0 0x4 &mpic 0x3 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};