#ifndef _IRQ_H_
#define _IRQ_H_

/** IRQ2 FOR CPLD INTERRUPT **/
/** IRQ3 FOR FPGA INTERRUPT **/
#define CSBAR               (0xFFE00000)
#define MPIC_REGS_BASE      (CSBAR + 0x40000)

#define MPIC_CTPR_OFFSET    (0x0080 >> 2)
#define MPIC_IACK_OFFSET    (0x00A0 >> 2)
#define MPIC_EOI_OFFSET     (0x00B0 >> 2)
#define MPIC_FRR_OFFSET     (0x1000 >> 2)
#define MPIC_GCR_OFFSET     (0x1020 >> 2)
#define MPIC_MER_OFFSET     (0x1500 >> 2)

#define MPIC_EIVPR2_OFFSET  (0x10040 >>2)
#define MPIC_EIDR2_OFFSET   (0x10050 >>2)
#define MPIC_EIVPR3_OFFSET  (0x10060 >>2)
#define MPIC_EIDR3_OFFSET   (0x10070 >>2)


#define MPIC_EIVPR_OFFSET(x) ((0x10000 + (x)*0x20) >>2)
#define MPIC_EIDR_OFFSET(x)  ((0x10000 + (x)*0x20 + 0x10) >> 2)

#define MPIC_REG_MAP_SIZE  (0x20070)


/** for EIVPR **/
/*active high to low*/

#define MPIC_EIVPR_PRIORITY(x)  ((x) << 16)
#define MPIC_EIVPR_VECTOR(x)    ((x) << 0)
#define MPIC_EIVPR_MSK          (1 << 31) /** interrupt disable */
#define MPIC_EIVPR_A            (1 << 30)
#define MPIC_EIVPR_S            (1 << (31-9))
#define MPIC_EIVPR_P            (1 << (31-8))
#define MPIC_EIVPR_PRIORITY_MASK (0x000f0000)
#define MPIC_EIVPR_VECTOR_MASK   (0xffff)
/** for EIDR **/
/** interrput is routed to IRQ_OUT for external service */
#define MPIC_EIDR_VALUE (0x00000001)

/** for CTPR **/
/** for all int priority except is servered */
#define MPIC_CTPR_VALUE (0x0)

/** for GCR **/
/** MPIC operate in mixed mode **/
#define MPIC_GCR_M     (1 << 29)

/** for FRR **/
#define IRQ_NUM_MASK   (0x3ff0000)

/** for EOI **/
#define MPIC_EOI_VALUE  (0)

/** for MER **/
#define MPIC_MER_VALUE (0x0000000F)

#endif