#ifndef _BUS_H_
#define _BUS_H_

#define CSBAR                  (0xFFE00000)

#define FPGA_BUS_REG_OFFSET    (0x1e000)
#define FPGA_BUS_REG_MAP_SIZE  (0x2000)

#define FPGA_BUS_BASE          (0xffb00000)
#define FPGA_BUS_MAP_SIZE      (0x10000)

#define FPGA_BUS_CSPR3_OFFSET  (0x34 >> 2)
#define FPGA_BUS_AMASK3_OFFSET (0xc4 >> 2)
#define FPGA_BUS_CSOR3_OFFSET  (0x154 >>2)
#define FPGA_BUS_CCR_OFFSET    (0x44c >>2)
#define FPGA_BUS_FTIM0_OFFSET  (0x250 >>2)
#define FPGA_BUS_FTIM1_OFFSET  (0x254 >>2)
#define FPGA_BUS_FTIM2_OFFSET  (0x258 >>2)

/** RD  **/
#define FPGA_CARD_TYPE_OFFSET       (0x0)
#define FPGA_CPLD_VER_OFFSET        (0x1)
#define FPGA_USER_ID_LOW_OFF        (0x2)
#define FPGA_USER_ID_HIGH_OFF       (0x3)
/** WR  **/
#define FPGA_GLOBAL_REG_OFFSET      (0x10)
#define FPGA_GPIO_CFG_OFFSET        (0x11)
#define FPGA_GPIO_DATA_OFFSET       (0x12)
#define FPGA_INT_MASK_REG_OFFSET    (0x13)
#define FPGA_INT_STATUS_REG_OFFSET  (0x14)

/** FPGA INTERRUPT ALL MASK **/
#define FPGA_INT_REG_MASK           (0xff)


/** gpio bit define **/
#define FPGA_GPIO_BD_SEL            (1<<0x0)
#define FPGA_GPIO_PEAK_BIT          (1<<0x1)
#define FPGA_GPIO_ALARM_LED         (1<<0x2)
#define FPGA_GPIO_RUN_LED           (1<<0x3)
#define FPGA_GPIO4_BIT              (1<<0x4)
#define FPGA_GPIO5_BIT              (1<<0x5)
#define FPGA_GPIO6_BIT              (1<<0x6)
#define FPGA_GPIO7_BIT              (1<<0x7)

#define FPGA_GPIO_STOP_BIT  (FPGA_GPIO7_BIT)
#define FPGA_GPIO_MRS_PHY   (FPGA_GPIO4_BIT|FPGA_GPIO5_BIT|FPGA_GPIO6_BIT)

#define FPGA_INT_MASK (0xff)


/** FPGA 1,2,3 = PEAK ,ALARM LED ,RUN LED as output ,others as input **/

#define GPIO_DEFAULT_CFG (FPGA_GPIO_PEAK_BIT |FPGA_GPIO_ALARM_LED |FPGA_GPIO_RUN_LED)

/** TDM ,GPIO MULTIPLE PINS AS GPIO **/
#define TDM_GPIO_SEL    (1 << 2)
#define GLOBAL_DEFAULT_CFG ( TDM_GPIO_SEL)

int fpga_bus_init(void);
void fpga_bus_exit(void);

unsigned short read_fpga16(unsigned short offset);
void write_fpga16(unsigned short offset, unsigned short value);
#endif