spbx/roms/srcs/images/ethernet/gianfar/fpga_bus.c

#ifdef __KERNEL__
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/time.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/fs.h>

#include "bus.h"

#define REG_CSPR3           (0xFFB00105)
#define REG_CSOR3_OFFSET    (0)
#define REG_AMASK3          (0xFFFF0000)
#define REG_CCR             (0x03000000)
#define REG_FTIM0           (0xE00E000E)
#define REG_FTIM1           (0x0E001F00)
#define REG_FTIM2           (0x0E00001F)

static unsigned int     g_bIsFPGAInited     = 0;
static unsigned int*    g_pFPGAReg          = NULL;
static unsigned short*  g_pRegBase          = NULL;
                      
unsigned short read_fpga16(unsigned short offset)
{
    return *((unsigned short*)(g_pRegBase + offset));
}

void write_fpga16(unsigned short offset, unsigned short value)
{
    *((unsigned short*)(g_pRegBase + offset)) = value;
}

int fpga_bus_init(void)
{
    unsigned int*   pReg = NULL;
    unsigned short* pCs3 = NULL;

    if(g_bIsFPGAInited == 0)
    {
        pReg = (unsigned int*)ioremap((CSBAR + FPGA_BUS_REG_OFFSET),
                                      FPGA_BUS_REG_MAP_SIZE);

        //reg_cspr3
        pReg[FPGA_BUS_CSPR3_OFFSET] = REG_CSPR3;
        //  //reg_amask3
        pReg[FPGA_BUS_AMASK3_OFFSET] = REG_AMASK3;
        //  //csor 3
        pReg[FPGA_BUS_CSOR3_OFFSET] = REG_CSOR3_OFFSET;

        //  // IFC_CCR //IFC_CLK=  50M  ptr[(0x44C>>2)] = 0x07000000;
        //  // IFC_CCR //IFC_CLK=  100M  ptr[(0x44C>>2)] = 0x03000000;
        //  // IFC_CCR //IFC_CLK=  200M  ptr[(0x44C>>2)] = 0x01000000;
        // default for 100M
        pReg[FPGA_BUS_CCR_OFFSET] = REG_CCR;
        //  // FTIM0_CS3_GPCM
        pReg[FPGA_BUS_FTIM0_OFFSET] = REG_FTIM0;
        //  // FTIM1_CS3_GPCM
        pReg[FPGA_BUS_FTIM1_OFFSET] = REG_FTIM1;
        //  // FTIM2_CS3_GPCM
        pReg[FPGA_BUS_FTIM2_OFFSET] = REG_FTIM2;

        g_pFPGAReg = pReg;

        pCs3 = (unsigned short*)ioremap(FPGA_BUS_BASE, FPGA_BUS_MAP_SIZE);
        g_pRegBase = pCs3;

        // Set GPIO Config
        write_fpga16(FPGA_GPIO_CFG_OFFSET,  GPIO_DEFAULT_CFG);
        read_fpga16(FPGA_GPIO_CFG_OFFSET);

        // Set Global Reg
        write_fpga16(FPGA_GLOBAL_REG_OFFSET, GLOBAL_DEFAULT_CFG);
    }

    g_bIsFPGAInited = 1;

    return 0;
}
EXPORT_SYMBOL(fpga_bus_init);

void fpga_bus_exit(void)
{
    if(g_bIsFPGAInited == 1)
    {
        iounmap(g_pFPGAReg);
        iounmap(g_pRegBase);
    }

    g_bIsFPGAInited = 0;
}
EXPORT_SYMBOL(fpga_bus_exit);

int fpga_RedLedCtrl(int iIsOn)
{
    unsigned short value;
    value  = read_fpga16(FPGA_GPIO_DATA_OFFSET);

    value = iIsOn ?
            (value | FPGA_GPIO_ALARM_LED) :
            (value & (~FPGA_GPIO_ALARM_LED));

    write_fpga16(FPGA_GPIO_DATA_OFFSET, value);

    return 0;
}
EXPORT_SYMBOL(fpga_RedLedCtrl);

int fpga_GreenLedCtrl(int flag)
{
    unsigned short value;

    value  = read_fpga16(FPGA_GPIO_DATA_OFFSET);

    value = flag ?
            (value | FPGA_GPIO_RUN_LED) :
            (value & (~FPGA_GPIO_RUN_LED));

    write_fpga16(FPGA_GPIO_DATA_OFFSET, value);

    return 0;
}
EXPORT_SYMBOL(fpga_GreenLedCtrl);

unsigned short fpga_GetCardType(void)
{
    return read_fpga16(FPGA_CARD_TYPE_OFFSET);
}
EXPORT_SYMBOL(fpga_GetCardType);

unsigned short fpga_GetFPGAVer(void)
{
    return read_fpga16(FPGA_CPLD_VER_OFFSET);
}
EXPORT_SYMBOL(fpga_GetFPGAVer);

unsigned int fpga_GetUserId(void)
{
    unsigned short value;

    value  = read_fpga16(FPGA_USER_ID_HIGH_OFF);

    return (value << 16) | read_fpga16(FPGA_USER_ID_LOW_OFF);
}
EXPORT_SYMBOL(fpga_GetUserId);

/** CPLD GPIO 4; CPLD GPIO 5; CPLD GPIO 6  **/
unsigned short  fpga_GetSlot(void)
{
    unsigned short value;

    value  = read_fpga16(FPGA_GPIO_DATA_OFFSET);

    return value;
}
EXPORT_SYMBOL(fpga_GetSlot);

#define SPBX_ID_CAPTURE_END    4
#define FPGA_BOX_ID_CTL_OFF         (0x20)
#define FPGA_BOX_ID_OFF            (0x16)
static unsigned int fpga_GetChassisSn(void)
{
    unsigned char temp;
    unsigned char id[4] = {0, 0, 0, 0};
    unsigned int* pId = (unsigned int*)id;
    unsigned char i;
    int check_id;

    //total 1s
    for(check_id = 1000; check_id > 0; check_id--)
    {
        temp = read_fpga16(FPGA_BOX_ID_CTL_OFF);

        if(temp & SPBX_ID_CAPTURE_END)
        {
            for(i = 0; i < 4; i++)
            {
                write_fpga16(FPGA_BOX_ID_CTL_OFF, i);
                udelay(1);
                id[i] = read_fpga16(FPGA_BOX_ID_OFF) & 0xFF;
            }

            if(*pId != 0)
            {
                return *pId;
            }
        }

        udelay(100);
    }   

    return 0xffffffff;
}
EXPORT_SYMBOL(fpga_GetChassisSn);

#endif