61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
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#ifndef _IRQ_H_
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#define _IRQ_H_
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/** IRQ2 FOR CPLD INTERRUPT **/
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/** IRQ3 FOR FPGA INTERRUPT **/
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#define CSBAR (0xFFE00000)
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#define MPIC_REGS_BASE (CSBAR + 0x40000)
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#define MPIC_CTPR_OFFSET (0x0080 >> 2)
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#define MPIC_IACK_OFFSET (0x00A0 >> 2)
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#define MPIC_EOI_OFFSET (0x00B0 >> 2)
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#define MPIC_FRR_OFFSET (0x1000 >> 2)
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#define MPIC_GCR_OFFSET (0x1020 >> 2)
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#define MPIC_MER_OFFSET (0x1500 >> 2)
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#define MPIC_EIVPR2_OFFSET (0x10040 >>2)
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#define MPIC_EIDR2_OFFSET (0x10050 >>2)
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#define MPIC_EIVPR3_OFFSET (0x10060 >>2)
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#define MPIC_EIDR3_OFFSET (0x10070 >>2)
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#define MPIC_EIVPR_OFFSET(x) ((0x10000 + (x)*0x20) >>2)
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#define MPIC_EIDR_OFFSET(x) ((0x10000 + (x)*0x20 + 0x10) >> 2)
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#define MPIC_REG_MAP_SIZE (0x20070)
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/** for EIVPR **/
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/*active high to low*/
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#define MPIC_EIVPR_PRIORITY(x) ((x) << 16)
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#define MPIC_EIVPR_VECTOR(x) ((x) << 0)
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#define MPIC_EIVPR_MSK (1 << 31) /** interrupt disable */
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#define MPIC_EIVPR_A (1 << 30)
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#define MPIC_EIVPR_S (1 << (31-9))
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#define MPIC_EIVPR_P (1 << (31-8))
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#define MPIC_EIVPR_PRIORITY_MASK (0x000f0000)
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#define MPIC_EIVPR_VECTOR_MASK (0xffff)
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/** for EIDR **/
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/** interrput is routed to IRQ_OUT for external service */
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#define MPIC_EIDR_VALUE (0x00000001)
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/** for CTPR **/
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/** for all int priority except is servered */
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#define MPIC_CTPR_VALUE (0x0)
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/** for GCR **/
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/** MPIC operate in mixed mode **/
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#define MPIC_GCR_M (1 << 29)
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/** for FRR **/
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#define IRQ_NUM_MASK (0x3ff0000)
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/** for EOI **/
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#define MPIC_EOI_VALUE (0)
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/** for MER **/
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#define MPIC_MER_VALUE (0x0000000F)
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#endif
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