78 lines
3.2 KiB
C
78 lines
3.2 KiB
C
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/*
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* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
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*
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* NOTE: This header file is not meant to be included directly.
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*/
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/* This header file contains assembly-language definitions (assembly
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macros, etc.) for this specific Xtensa processor's TIE extensions
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and options. It is customized to this Xtensa processor configuration.
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Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XTENSA_CORE_TIE_ASM_H
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#define _XTENSA_CORE_TIE_ASM_H
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/* Selection parameter values for save-area save/restore macros: */
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/* Option vs. TIE: */
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#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
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#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
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/* Whether used automatically by compiler: */
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#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
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#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
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/* ABI handling across function calls: */
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#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
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#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
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#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (1 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
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*/
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.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.endm // xchal_ncp_store
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (1 byte aligned)
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* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
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*/
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.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
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xchal_sa_start \continue, \ofs
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 0
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#define XCHAL_SA_NUM_ATMPS 0
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#endif /*_XTENSA_CORE_TIE_ASM_H*/
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