313 lines
9.5 KiB
C
313 lines
9.5 KiB
C
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/*
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FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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>>! NOTE: The modification to the GPL is included to allow you to distribute
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>>! a combined work that includes FreeRTOS without being obliged to provide
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>>! the source code for proprietary components outside of the FreeRTOS
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>>! kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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compatible FAT file system, and our tiny thread aware UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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licenses offer ticketed support, indemnification and middleware.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM3 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include <xtensa/config/core.h>
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#include <xtensa/tie/xt_interrupt.h>
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#include <xtensa/tie/xt_timer.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/xtensa_rtos.h"
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#define PORT_ASSERT(x) do { if (!(x)) {ets_printf("%s %u\n", "rtos_port", __LINE__); while(1){}; }} while (0)
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extern char NMIIrqIsOn;
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static char HdlMacSig = 0;
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static char SWReq = 0;
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unsigned cpu_sr;
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static unsigned portBASE_TYPE uxCriticalNesting = 0;
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void vPortEnterCritical(void);
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void vPortExitCritical(void);
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/*
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* See header file for description.
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*/
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portSTACK_TYPE* ICACHE_FLASH_ATTR
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pxPortInitialiseStack(portSTACK_TYPE* pxTopOfStack, pdTASK_CODE pxCode, void* pvParameters)
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{
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#define SET_STKREG(r,v) sp[(r) >> 2] = (portSTACK_TYPE)(v)
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portSTACK_TYPE* sp, *tp;
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/* Create interrupt stack frame aligned to 16 byte boundary */
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sp = (portSTACK_TYPE*)(((INT32U)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
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/* Clear the entire frame (do not use memset() because we don't depend on C library) */
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for (tp = sp; tp <= pxTopOfStack; ++tp) {
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*tp = 0;
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}
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/* Explicitly initialize certain saved registers */
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SET_STKREG(XT_STK_PC, pxCode); /* task entrypoint */
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SET_STKREG(XT_STK_A0, 0); /* to terminate GDB backtrace */
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SET_STKREG(XT_STK_A1, (INT32U)sp + XT_STK_FRMSZ); /* physical top of stack frame */
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SET_STKREG(XT_STK_A2, pvParameters); /* parameters */
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SET_STKREG(XT_STK_EXIT, _xt_user_exit); /* user exception exit dispatcher */
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/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
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#ifdef __XTENSA_CALL0_ABI__
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SET_STKREG(XT_STK_PS, PS_UM | PS_EXCM);
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#else
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/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
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SET_STKREG(XT_STK_PS, PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1));
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#endif
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return sp;
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}
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void PendSV(char req)
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{
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if (req == 1) {
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vPortEnterCritical();
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SWReq = 1;
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xthal_set_intset(1 << ETS_SOFT_INUM);
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vPortExitCritical();
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} else if (req == 2) {
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HdlMacSig = 1;
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xthal_set_intset(1 << ETS_SOFT_INUM);
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}
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}
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extern portBASE_TYPE MacIsrSigPostDefHdl(void);
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void SoftIsrHdl(void* arg)
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{
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ETS_NMI_LOCK();
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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if (HdlMacSig == 1) {
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HdlMacSig = 0;
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xHigherPriorityTaskWoken = MacIsrSigPostDefHdl();
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}
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if (xHigherPriorityTaskWoken || (SWReq == 1)) {
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_xt_timer_int1();
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SWReq = 0;
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}
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ETS_NMI_UNLOCK();
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}
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void xPortSysTickHandle(void)
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{
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if (xTaskIncrementTick() != pdFALSE) {
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vTaskSwitchContext();
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}
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}
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/*
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* See header file for description.
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*/
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portBASE_TYPE ICACHE_FLASH_ATTR
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xPortStartScheduler(void)
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{
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/*******software isr*********/
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_xt_isr_attach(ETS_SOFT_INUM, SoftIsrHdl, NULL);
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_xt_isr_unmask(1 << ETS_SOFT_INUM);
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/* Initialize system tick timer interrupt and schedule the first tick. */
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_xt_tick_timer_init();
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vTaskSwitchContext();
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/* Restore the context of the first task that is going to run. */
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XT_RTOS_INT_EXIT();
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/* Should not get here as the tasks are now running! */
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return pdTRUE;
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}
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void ICACHE_FLASH_ATTR
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vPortEndScheduler(void)
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{
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/* It is unlikely that the CM3 port will require this function as there
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is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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static char ClosedLv1Isr = 0;
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void vPortEnterCritical(void)
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{
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if (NMIIrqIsOn == 0) {
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if (ClosedLv1Isr != 1) {
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portDISABLE_INTERRUPTS();
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ClosedLv1Isr = 1;
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}
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uxCriticalNesting++;
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}
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical(void)
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{
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if (NMIIrqIsOn == 0) {
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if (uxCriticalNesting > 0) {
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uxCriticalNesting--;
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if (uxCriticalNesting == 0) {
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if (ClosedLv1Isr == 1) {
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ClosedLv1Isr = 0;
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portENABLE_INTERRUPTS();
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}
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}
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} else {
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ets_printf("E:C:%d\n", uxCriticalNesting);
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PORT_ASSERT((uxCriticalNesting > 0));
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}
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}
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}
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void ICACHE_FLASH_ATTR ShowCritical(void)
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{
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os_printf("ShowCritical:%d\n", uxCriticalNesting);
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os_printf("HdlMacSig:%d\n", HdlMacSig);
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os_printf("SWReq:%d\n", SWReq);
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ets_delay_us(50000);
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}
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void vPortETSIntrLock(void)
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{
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ETS_INTR_LOCK();
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}
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void vPortETSIntrUnlock(void)
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{
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ETS_INTR_UNLOCK();
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}
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void PortDisableInt_NoNest(void)
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{
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if (NMIIrqIsOn == 0) {
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if (ClosedLv1Isr != 1) {
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portDISABLE_INTERRUPTS();
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ClosedLv1Isr = 1;
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}
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}
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}
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void PortEnableInt_NoNest(void)
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{
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if (NMIIrqIsOn == 0) {
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if (ClosedLv1Isr == 1) {
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ClosedLv1Isr = 0;
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portENABLE_INTERRUPTS();
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}
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}
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}
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/*-----------------------------------------------------------*/
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void ICACHE_FLASH_ATTR ResetCcountVal(unsigned int cnt_val)
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{
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asm volatile("wsr a2, ccount");
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}
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_xt_isr_entry isr[16];
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char _xt_isr_status = 0;
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void ICACHE_FLASH_ATTR
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_xt_isr_attach(uint8 i, _xt_isr func, void* arg)
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{
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isr[i].handler = func;
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isr[i].arg = arg;
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}
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uint16 _xt_isr_handler(uint16 i)
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{
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uint8 index;
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if (i & (1 << ETS_WDT_INUM)) {
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index = ETS_WDT_INUM;
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} else if (i & (1 << ETS_GPIO_INUM)) {
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index = ETS_GPIO_INUM;
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} else {
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index = __builtin_ffs(i) - 1;
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if (index == ETS_MAX_INUM) {
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i &= ~(1 << ETS_MAX_INUM);
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index = __builtin_ffs(i) - 1;
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}
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}
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_xt_clear_ints(1 << index);
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_xt_isr_status = 1;
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isr[index].handler(isr[index].arg);
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_xt_isr_status = 0;
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return i & ~(1 << index);
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}
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