523 lines
17 KiB
C
523 lines
17 KiB
C
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/**
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* spi_interface.c
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*
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* Defines and Macros for the SPI.
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*
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* Copyright @ 2015 Espressif System Co., Ltd.
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* All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are NOT permitted except as agreed by
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* Espressif System Co., Ltd.
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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*/
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/**
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* @file spi_interface.c
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* @brief Defines and Macros for the SPI.
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*/
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#include "spi_interface.h"
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#include "esp8266/eagle_soc.h"
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#include "esp8266/ets_sys.h"
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#include "esp8266/pin_mux_register.h"
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#include "esp_libc.h"
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//*****************************************************************************
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//
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// Make sure all of the definitions in this header have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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// Show the spi registers.
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#define SHOWDEBUG
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void __ShowRegValue(const char * func, uint32_t line)
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{
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#ifndef SHOWDEBUG
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int i;
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uint32_t regAddr = 0x60000140; // SPI--0x60000240, HSPI--0x60000140;
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printf("\r\n FUNC[%s],line[%d]\r\n", func, line);
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printf(" SPI_ADDR [0x%08x]\r\n", READ_PERI_REG(SPI_ADDR(SpiNum_HSPI)));
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printf(" SPI_CMD [0x%08x]\r\n", READ_PERI_REG(SPI_CMD(SpiNum_HSPI)));
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printf(" SPI_CTRL [0x%08x]\r\n", READ_PERI_REG(SPI_CTRL(SpiNum_HSPI)));
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printf(" SPI_CTRL2 [0x%08x]\r\n", READ_PERI_REG(SPI_CTRL2(SpiNum_HSPI)));
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printf(" SPI_CLOCK [0x%08x]\r\n", READ_PERI_REG(SPI_CLOCK(SpiNum_HSPI)));
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printf(" SPI_RD_STATUS [0x%08x]\r\n", READ_PERI_REG(SPI_RD_STATUS(SpiNum_HSPI)));
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printf(" SPI_WR_STATUS [0x%08x]\r\n", READ_PERI_REG(SPI_WR_STATUS(SpiNum_HSPI)));
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printf(" SPI_USER [0x%08x]\r\n", READ_PERI_REG(SPI_USER(SpiNum_HSPI)));
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printf(" SPI_USER1 [0x%08x]\r\n", READ_PERI_REG(SPI_USER1(SpiNum_HSPI)));
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printf(" SPI_USER2 [0x%08x]\r\n", READ_PERI_REG(SPI_USER2(SpiNum_HSPI)));
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printf(" SPI_PIN [0x%08x]\r\n", READ_PERI_REG(SPI_PIN(SpiNum_HSPI)));
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printf(" SPI_SLAVE [0x%08x]\r\n", READ_PERI_REG(SPI_SLAVE(SpiNum_HSPI)));
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printf(" SPI_SLAVE1 [0x%08x]\r\n", READ_PERI_REG(SPI_SLAVE1(SpiNum_HSPI)));
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printf(" SPI_SLAVE2 [0x%08x]\r\n", READ_PERI_REG(SPI_SLAVE2(SpiNum_HSPI)));
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for (i = 0; i < 16; ++i) {
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printf(" ADDR[0x%08x],Value[0x%08x]\r\n", regAddr, READ_PERI_REG(regAddr));
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regAddr += 4;
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}
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#endif
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}
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// Define SPI interrupt enable macro
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#define ETS_SPI_INTR_ENABLE() _xt_isr_unmask(1 << ETS_SPI_INUM)
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/**
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* @brief Based on pAttr initialize SPI module.
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*
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*/
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void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr* pAttr)
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{
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if ((spiNum > SpiNum_HSPI)
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|| (NULL == pAttr)) {
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return;
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}
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// SPI_CPOL & SPI_CPHA
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switch (pAttr->subMode) {
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case SpiSubMode_1:
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CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
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break;
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case SpiSubMode_2:
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SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE
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break;
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case SpiSubMode_3:
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SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
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break;
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case SpiSubMode_0:
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default:
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CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE);
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE);
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// To do nothing
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break;
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}
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// SPI bit order
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if (SpiBitOrder_MSBFirst == pAttr->bitOrder) {
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CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER);
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CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER);
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} else if (SpiBitOrder_LSBFirst == pAttr->bitOrder) {
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SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER);
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SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER);
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} else {
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// To do nothing
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}
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// Disable flash operation mode
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// As earlier as better, if not SPI_CTRL2 can not to be set delay cycles.
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_FLASH_MODE);
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// SPI mode type
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if (SpiMode_Master == pAttr->mode) {
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// SPI mode type
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CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
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// SPI Send buffer
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART );// By default slave send buffer C0-C7
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// SPI Speed
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if (1 < (pAttr->speed)) {
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CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK);
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if (spiNum == SpiNum_HSPI) {
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CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX_CONF_U, SPI1_CLK_EQU_SYS_CLK);
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}
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WRITE_PERI_REG(SPI_CLOCK(spiNum),
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((pAttr->speed & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
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((((pAttr->speed + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
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((pAttr->speed & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
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} else {
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WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
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}
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// By default format:CMD+ADDR+DATA
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI );
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//delay num
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SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S));
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} else if (SpiMode_Slave == pAttr->mode) {
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// BIT19 must do
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SET_PERI_REG_MASK(SPI_PIN(spiNum), BIT19);
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// SPI mode type
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SET_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE);
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// SPI Send buffer
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C8-C15
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
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// If do not set delay cycles, slave not working,master cann't get the data.
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SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S)); //delay num
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// SPI Speed
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WRITE_PERI_REG(SPI_CLOCK(spiNum), 0);
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// By default format::CMD(8bits)+ADDR(8bits)+DATA(32bytes).
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SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
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7, SPI_USR_COMMAND_BITLEN_S);
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SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_WR_ADDR_BITLEN,
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7, SPI_SLV_WR_ADDR_BITLEN_S);
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SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_RD_ADDR_BITLEN,
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7, SPI_SLV_RD_ADDR_BITLEN_S);
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SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_BUF_BITLEN,
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(32 * 8 - 1), SPI_SLV_BUF_BITLEN_S);
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// For 8266 work on slave mode.
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SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_STATUS_BITLEN,
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7, SPI_SLV_STATUS_BITLEN_S);
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} else {
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// To do nothing
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}
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//clear Daul or Quad lines transmission mode
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CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_QIO_MODE | SPI_DIO_MODE | SPI_DOUT_MODE | SPI_QOUT_MODE);
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SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_FASTRD_MODE);
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}
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/**
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* @brief Set address value by master mode.
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*
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*/
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void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr)
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{
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if (spiNum > SpiNum_HSPI) {
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return;
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}
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// Set address
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WRITE_PERI_REG(SPI_ADDR(spiNum), addr);
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}
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/**
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* @brief Set command value by master mode.
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*
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*/
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void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd)
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{
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if (spiNum > SpiNum_HSPI) {
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return;
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}
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// SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
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// bit15-0 is cmd value.
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SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S);
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}
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/**
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* @brief Send data to slave.
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*
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*/
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int ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData* pInData)
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{
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char idx = 0;
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if ((spiNum > SpiNum_HSPI)
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|| (NULL == pInData)
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|| (64 < pInData->dataLen)) {
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return -1;
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}
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uint32_t *value = pInData->data;
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while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
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// Set command by user.
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if (pInData->cmdLen != 0) {
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// Max command length 16 bits.
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SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
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((pInData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S);
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// Enable command
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
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// Load command
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SPIMasterCfgCmd(spiNum, pInData->cmd);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
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SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
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0, SPI_USR_COMMAND_BITLEN_S);
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}
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// Set Address by user.
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if (pInData->addrLen == 0) {
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
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SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
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0, SPI_USR_ADDR_BITLEN_S);
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} else {
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if (NULL == pInData->addr) {
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return -1;
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}
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SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
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((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
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// Enable address
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
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// Load address
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SPIMasterCfgAddr(spiNum, *pInData->addr);
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}
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// Set data by user.
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if (pInData->dataLen != 0) {
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if (NULL == value) {
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return -1;
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}
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// Enable MOSI
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
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// Load send buffer
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do {
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WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++);
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} while (++idx < (pInData->dataLen / 4));
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// Set data send buffer length.Max data length 64 bytes.
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SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
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SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
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0, SPI_USR_MOSI_BITLEN_S);
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}
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// Start send data
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SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
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SHOWREG();
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return 0;
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}
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/**
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* @brief Receive data from slave.
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*
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*/
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int ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData* pOutData)
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{
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char idx = 0;
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if ((spiNum > SpiNum_HSPI)
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|| (NULL == pOutData)) {
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return -1;
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}
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uint32_t *value = pOutData->data;
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while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
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// Set command by user.
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if (pOutData->cmdLen != 0) {
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// Max command length 16 bits.
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SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
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((pOutData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S);
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// Enable command
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SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
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// Load command
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SPIMasterCfgCmd(spiNum, pOutData->cmd);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND);
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SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN,
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0, SPI_USR_COMMAND_BITLEN_S);
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}
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// Set Address by user.
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if (pOutData->addrLen == 0) {
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CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
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SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
|
||
|
|
0, SPI_USR_ADDR_BITLEN_S);
|
||
|
|
} else {
|
||
|
|
if (NULL == pOutData->addr) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN,
|
||
|
|
((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S);
|
||
|
|
// Enable address
|
||
|
|
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR);
|
||
|
|
// Load address
|
||
|
|
SPIMasterCfgAddr(spiNum, *pOutData->addr);
|
||
|
|
}
|
||
|
|
// Set data by user.
|
||
|
|
if (pOutData->dataLen != 0) {
|
||
|
|
if (NULL == value) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
// Clear MOSI enable
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||
|
|
// Enable MOSI
|
||
|
|
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||
|
|
// Set data send buffer length.Max data length 64 bytes.
|
||
|
|
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, ((pOutData->dataLen << 3) - 1), SPI_USR_MISO_BITLEN_S);
|
||
|
|
} else {
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||
|
|
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN,
|
||
|
|
0, SPI_USR_MISO_BITLEN_S);
|
||
|
|
}
|
||
|
|
|
||
|
|
//CLEAR FIFO DATA
|
||
|
|
int fifo_idx = 0;
|
||
|
|
do {
|
||
|
|
WRITE_PERI_REG(SPI_W0(spiNum) + (fifo_idx << 2), 0);
|
||
|
|
} while (++fifo_idx < (pOutData->dataLen / 4));
|
||
|
|
|
||
|
|
// Start send data
|
||
|
|
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||
|
|
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||
|
|
// Read data out
|
||
|
|
do {
|
||
|
|
*pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2));
|
||
|
|
} while (++idx < (pOutData->dataLen / 4));
|
||
|
|
|
||
|
|
SHOWREG();
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Load data to send buffer by slave mode.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
int ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t outLen)
|
||
|
|
{
|
||
|
|
if (NULL == pInData) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
char i;
|
||
|
|
for (i = 0; i < outLen; ++i) {
|
||
|
|
WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *pInData++);
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configurate slave prepare for receive data.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
int ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum, void(*isrFunc)(void*))
|
||
|
|
{
|
||
|
|
if ((spiNum > SpiNum_HSPI)) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
SPIIntEnable(SpiNum_HSPI, SpiIntSrc_WrStaDoneEn
|
||
|
|
| SpiIntSrc_RdStaDoneEn | SpiIntSrc_WrBufDoneEn | SpiIntSrc_RdBufDoneEn);
|
||
|
|
SPIIntDisable(SpiNum_HSPI, SpiIntSrc_TransDoneEn);
|
||
|
|
|
||
|
|
// Maybe enable slave transmission liston
|
||
|
|
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||
|
|
//
|
||
|
|
_xt_isr_attach(ETS_SPI_INUM, isrFunc, NULL);
|
||
|
|
// ETS_SPI_INTR_ATTACH(isrFunc, NULL);
|
||
|
|
// Enable isr
|
||
|
|
ETS_SPI_INTR_ENABLE();
|
||
|
|
|
||
|
|
|
||
|
|
SHOWREG();
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS).
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data)
|
||
|
|
{
|
||
|
|
if (spiNum > SpiNum_HSPI) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||
|
|
// Enable MOSI
|
||
|
|
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI);
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
|
||
|
|
|
||
|
|
// 8bits cmd, 0x04 is eps8266 slave write cmd value
|
||
|
|
WRITE_PERI_REG(SPI_USER2(spiNum),
|
||
|
|
((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S)
|
||
|
|
| MASTER_WRITE_STATUS_TO_SLAVE_CMD);
|
||
|
|
// Set data send buffer length.
|
||
|
|
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN,
|
||
|
|
((sizeof(data) << 3) - 1), SPI_USR_MOSI_BITLEN_S);
|
||
|
|
|
||
|
|
WRITE_PERI_REG(SPI_W0(spiNum), (uint32)(data));
|
||
|
|
// Start SPI
|
||
|
|
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||
|
|
|
||
|
|
SHOWREG();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Receive status register from slave(ESP8266).
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
int ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum)
|
||
|
|
{
|
||
|
|
if (spiNum > SpiNum_HSPI) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||
|
|
// Enable MISO
|
||
|
|
SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO);
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR);
|
||
|
|
|
||
|
|
// 8bits cmd, 0x06 is eps8266 slave read status cmd value
|
||
|
|
WRITE_PERI_REG(SPI_USER2(spiNum),
|
||
|
|
((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S)
|
||
|
|
| MASTER_READ_STATUS_FROM_SLAVE_CMD);
|
||
|
|
// Set revcive buffer length.
|
||
|
|
SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN,
|
||
|
|
7, SPI_USR_MISO_BITLEN_S);
|
||
|
|
|
||
|
|
// start spi module.
|
||
|
|
SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR);
|
||
|
|
|
||
|
|
while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR);
|
||
|
|
|
||
|
|
uint8_t data = (uint8)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
|
||
|
|
SHOWREG();
|
||
|
|
|
||
|
|
return (uint8)(READ_PERI_REG(SPI_W0(spiNum)) & 0xff);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Select SPI CS pin.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs)
|
||
|
|
{
|
||
|
|
if (spiNum > SpiNum_HSPI) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
// clear select
|
||
|
|
SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0);
|
||
|
|
SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable SPI interrupt source.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc)
|
||
|
|
{
|
||
|
|
if (spiNum > SpiNum_HSPI) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
SET_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable SPI interrupt source.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc)
|
||
|
|
{
|
||
|
|
if (spiNum > SpiNum_HSPI) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), intSrc);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear all of SPI interrupt source.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum)
|
||
|
|
{
|
||
|
|
if (spiNum > SpiNum_HSPI) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SpiIntSrc_TransDoneEn
|
||
|
|
| SpiIntSrc_WrStaDoneEn
|
||
|
|
| SpiIntSrc_RdStaDoneEn
|
||
|
|
| SpiIntSrc_WrBufDoneEn
|
||
|
|
| SpiIntSrc_RdBufDoneEn);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|