436 lines
14 KiB
C
436 lines
14 KiB
C
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/*
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* ESPRSSIF MIT License
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*
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* Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
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*
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* Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
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* it is free of charge, to any person obtaining a copy of this software and associated
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* documentation files (the "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "esp_common.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "uart.h"
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enum {
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UART_EVENT_RX_CHAR,
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UART_EVENT_MAX
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};
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typedef struct _os_event_ {
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uint32 event;
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uint32 param;
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} os_event_t;
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xTaskHandle xUartTaskHandle;
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xQueueHandle xQueueUart;
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LOCAL STATUS
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uart_tx_one_char(uint8 uart, uint8 TxChar)
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{
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while (true) {
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uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
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if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) {
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break;
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}
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}
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WRITE_PERI_REG(UART_FIFO(uart) , TxChar);
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return OK;
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}
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LOCAL void
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uart1_write_char(char c)
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{
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if (c == '\n') {
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uart_tx_one_char(UART1, '\r');
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uart_tx_one_char(UART1, '\n');
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} else if (c == '\r') {
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} else {
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uart_tx_one_char(UART1, c);
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}
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}
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LOCAL void
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uart0_write_char(char c)
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{
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if (c == '\n') {
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uart_tx_one_char(UART0, '\r');
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uart_tx_one_char(UART0, '\n');
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} else if (c == '\r') {
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} else {
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uart_tx_one_char(UART0, c);
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}
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}
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LOCAL void
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uart_rx_intr_handler_ssc(void *arg)
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{
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/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
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* uart1 and uart0 respectively
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*/
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os_event_t e;
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portBASE_TYPE xHigherPriorityTaskWoken;
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uint8 RcvChar;
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uint8 uart_no = 0;
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if (UART_RXFIFO_FULL_INT_ST != (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) {
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return;
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}
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RcvChar = READ_PERI_REG(UART_FIFO(uart_no)) & 0xFF;
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_FULL_INT_CLR);
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e.event = UART_EVENT_RX_CHAR;
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e.param = RcvChar;
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xQueueSendFromISR(xQueueUart, (void *)&e, &xHigherPriorityTaskWoken);
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portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
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}
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#if 0
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LOCAL void
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uart_config(uint8 uart_no, UartDevice *uart)
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{
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if (uart_no == UART1) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
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} else {
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/* rcv_buff size if 0x100 */
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_xt_isr_attach(ETS_UART_INUM, uart_rx_intr_handler_ssc, NULL);
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
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}
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uart_div_modify(uart_no, UART_CLK_FREQ / (uart->baut_rate));
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WRITE_PERI_REG(UART_CONF0(uart_no), uart->exist_parity
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| uart->parity
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| (uart->stop_bits << UART_STOP_BIT_NUM_S)
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| (uart->data_bits << UART_BIT_NUM_S));
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//clear rx and tx fifo,not ready
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
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if (uart_no == UART0) {
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//set rx fifo trigger
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WRITE_PERI_REG(UART_CONF1(uart_no),
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((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
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} else {
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WRITE_PERI_REG(UART_CONF1(uart_no),
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((0x01 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
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}
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//clear all interrupt
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WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff);
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//enable rx_interrupt
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA);
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}
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#endif
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LOCAL void
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uart_task(void *pvParameters)
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{
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os_event_t e;
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for (;;) {
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if (xQueueReceive(xQueueUart, (void *)&e, (portTickType)portMAX_DELAY)) {
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switch (e.event) {
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case UART_EVENT_RX_CHAR:
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printf("%c", e.param);
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break;
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default:
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break;
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}
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}
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}
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vTaskDelete(NULL);
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}
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#if 0
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void
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uart_init(void)
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{
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while (READ_PERI_REG(UART_STATUS(0)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
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while (READ_PERI_REG(UART_STATUS(1)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
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UART_ConfigTypeDef uart;
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uart.baut_rate = BIT_RATE_74880;
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uart.data_bits = UART_WordLength_8b;
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uart.flow_ctrl = USART_HardwareFlowControl_None;
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// uart.exist_parity = PARITY_DIS;
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uart.parity = USART_Parity_None;
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uart.stop_bits = USART_StopBits_1;
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uart_config(UART0, &uart);
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uart_config(UART1, &uart);
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os_install_putc1(uart1_write_char);
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_xt_isr_unmask(1 << ETS_UART_INUM);
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xQueueUart = xQueueCreate(32, sizeof(os_event_t));
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xTaskCreate(uart_task, (uint8 const *)"uTask", 512, NULL, tskIDLE_PRIORITY + 2, &xUartTaskHandle);
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}
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#endif
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//=================================================================
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void
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UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
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{
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SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S);
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}
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void
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UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
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{
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SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S);
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}
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void
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UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
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{
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK);
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SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask);
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}
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void
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UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
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{
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN);
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if (Parity_mode == USART_Parity_None) {
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} else {
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SET_PERI_REG_MASK(UART_CONF0(uart_no), Parity_mode | UART_PARITY_EN);
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}
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}
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void
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UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate)
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{
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uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate);
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}
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//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set.
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void
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UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
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{
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if (flow_ctrl & USART_HardwareFlowControl_RTS) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
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SET_PERI_REG_BITS(UART_CONF1(uart_no), UART_RX_FLOW_THRHD, rx_thresh, UART_RX_FLOW_THRHD_S);
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SET_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN);
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} else {
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CLEAR_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN);
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}
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if (flow_ctrl & USART_HardwareFlowControl_CTS) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS);
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN);
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} else {
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN);
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}
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}
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void
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UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
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{
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while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
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}
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void
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UART_ResetFifo(UART_Port uart_no)
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{
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
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}
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void
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UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask)
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{
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WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask);
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}
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void
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UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask)
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{
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask);
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}
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void
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UART_intr_handler_register(void *fn, void *arg)
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{
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_xt_isr_attach(ETS_UART_INUM, fn, arg);
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}
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void
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UART_SetPrintPort(UART_Port uart_no)
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{
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if (uart_no == 1) {
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os_install_putc1(uart1_write_char);
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} else {
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os_install_putc1(uart0_write_char);
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}
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}
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void
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UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
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{
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if (uart_no == UART1) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
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} else {
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
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}
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UART_SetFlowCtrl(uart_no, pUARTConfig->flow_ctrl, pUARTConfig->UART_RxFlowThresh);
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UART_SetBaudrate(uart_no, pUARTConfig->baud_rate);
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WRITE_PERI_REG(UART_CONF0(uart_no),
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((pUARTConfig->parity == USART_Parity_None) ? 0x0 : (UART_PARITY_EN | pUARTConfig->parity))
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| (pUARTConfig->stop_bits << UART_STOP_BIT_NUM_S)
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| (pUARTConfig->data_bits << UART_BIT_NUM_S)
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| ((pUARTConfig->flow_ctrl & USART_HardwareFlowControl_CTS) ? UART_TX_FLOW_EN : 0x0)
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| pUARTConfig->UART_InverseMask);
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UART_ResetFifo(uart_no);
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}
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void
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UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
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{
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uint32 reg_val = 0;
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UART_ClearIntrStatus(uart_no, UART_INTR_MASK);
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reg_val = READ_PERI_REG(UART_CONF1(uart_no)) & ((UART_RX_FLOW_THRHD << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN) ;
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reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_TOUT_INT_ENA) ?
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((((pUARTIntrConf->UART_RX_TimeOutIntrThresh)&UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S) | UART_RX_TOUT_EN) : 0);
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reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_FULL_INT_ENA) ?
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(((pUARTIntrConf->UART_RX_FifoFullIntrThresh)&UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) : 0);
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reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_TXFIFO_EMPTY_INT_ENA) ?
|
||
|
|
(((pUARTIntrConf->UART_TX_FifoEmptyIntrThresh)&UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S) : 0);
|
||
|
|
|
||
|
|
WRITE_PERI_REG(UART_CONF1(uart_no), reg_val);
|
||
|
|
CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_INTR_MASK);
|
||
|
|
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask);
|
||
|
|
}
|
||
|
|
|
||
|
|
LOCAL void
|
||
|
|
uart0_rx_intr_handler(void *para)
|
||
|
|
{
|
||
|
|
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
|
||
|
|
* uart1 and uart0 respectively
|
||
|
|
*/
|
||
|
|
uint8 RcvChar;
|
||
|
|
uint8 uart_no = UART0;//UartDev.buff_uart_no;
|
||
|
|
uint8 fifo_len = 0;
|
||
|
|
uint8 buf_idx = 0;
|
||
|
|
uint8 fifo_tmp[128] = {0};
|
||
|
|
|
||
|
|
uint32 uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
|
||
|
|
|
||
|
|
while (uart_intr_status != 0x0) {
|
||
|
|
if (UART_FRM_ERR_INT_ST == (uart_intr_status & UART_FRM_ERR_INT_ST)) {
|
||
|
|
//printf("FRM_ERR\r\n");
|
||
|
|
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR);
|
||
|
|
} else if (UART_RXFIFO_FULL_INT_ST == (uart_intr_status & UART_RXFIFO_FULL_INT_ST)) {
|
||
|
|
printf("full\r\n");
|
||
|
|
fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
|
||
|
|
buf_idx = 0;
|
||
|
|
|
||
|
|
while (buf_idx < fifo_len) {
|
||
|
|
uart_tx_one_char(UART0, READ_PERI_REG(UART_FIFO(UART0)) & 0xFF);
|
||
|
|
buf_idx++;
|
||
|
|
}
|
||
|
|
|
||
|
|
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
|
||
|
|
} else if (UART_RXFIFO_TOUT_INT_ST == (uart_intr_status & UART_RXFIFO_TOUT_INT_ST)) {
|
||
|
|
printf("tout\r\n");
|
||
|
|
fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
|
||
|
|
buf_idx = 0;
|
||
|
|
|
||
|
|
while (buf_idx < fifo_len) {
|
||
|
|
uart_tx_one_char(UART0, READ_PERI_REG(UART_FIFO(UART0)) & 0xFF);
|
||
|
|
buf_idx++;
|
||
|
|
}
|
||
|
|
|
||
|
|
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR);
|
||
|
|
} else if (UART_TXFIFO_EMPTY_INT_ST == (uart_intr_status & UART_TXFIFO_EMPTY_INT_ST)) {
|
||
|
|
printf("empty\n\r");
|
||
|
|
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_TXFIFO_EMPTY_INT_CLR);
|
||
|
|
CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA);
|
||
|
|
} else {
|
||
|
|
//skip
|
||
|
|
}
|
||
|
|
|
||
|
|
uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
uart_init_new(void)
|
||
|
|
{
|
||
|
|
UART_WaitTxFifoEmpty(UART0);
|
||
|
|
UART_WaitTxFifoEmpty(UART1);
|
||
|
|
|
||
|
|
UART_ConfigTypeDef uart_config;
|
||
|
|
uart_config.baud_rate = BIT_RATE_74880;
|
||
|
|
uart_config.data_bits = UART_WordLength_8b;
|
||
|
|
uart_config.parity = USART_Parity_None;
|
||
|
|
uart_config.stop_bits = USART_StopBits_1;
|
||
|
|
uart_config.flow_ctrl = USART_HardwareFlowControl_None;
|
||
|
|
uart_config.UART_RxFlowThresh = 120;
|
||
|
|
uart_config.UART_InverseMask = UART_None_Inverse;
|
||
|
|
UART_ParamConfig(UART0, &uart_config);
|
||
|
|
|
||
|
|
UART_IntrConfTypeDef uart_intr;
|
||
|
|
uart_intr.UART_IntrEnMask = UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_FULL_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA;
|
||
|
|
uart_intr.UART_RX_FifoFullIntrThresh = 10;
|
||
|
|
uart_intr.UART_RX_TimeOutIntrThresh = 2;
|
||
|
|
uart_intr.UART_TX_FifoEmptyIntrThresh = 20;
|
||
|
|
UART_IntrConfig(UART0, &uart_intr);
|
||
|
|
|
||
|
|
UART_SetPrintPort(UART0);
|
||
|
|
UART_intr_handler_register(uart0_rx_intr_handler, NULL);
|
||
|
|
ETS_UART_INTR_ENABLE();
|
||
|
|
|
||
|
|
/*
|
||
|
|
UART_SetWordLength(UART0,UART_WordLength_8b);
|
||
|
|
UART_SetStopBits(UART0,USART_StopBits_1);
|
||
|
|
UART_SetParity(UART0,USART_Parity_None);
|
||
|
|
UART_SetBaudrate(UART0,74880);
|
||
|
|
UART_SetFlowCtrl(UART0,USART_HardwareFlowControl_None,0);
|
||
|
|
*/
|
||
|
|
|
||
|
|
}
|