738 lines
19 KiB
Plaintext
738 lines
19 KiB
Plaintext
/{
|
|
clocks {
|
|
compatible = "allwinner,clk-init";
|
|
device_type = "clocks";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
reg = <0x0 0x03001000 0x0 0x1000>, /*cpux space*/
|
|
<0x0 0x07010000 0x0 0x400>, /*cpus space*/
|
|
<0x0 0x07000000 0x0 0x4>;
|
|
|
|
/* register fixed rate clock*/
|
|
clk_losc: losc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-clock";
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "losc";
|
|
};
|
|
clk_iosc: iosc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-clock";
|
|
clock-frequency = <16000000>;
|
|
clock-output-names = "iosc";
|
|
};
|
|
clk_hosc: hosc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "hosc";
|
|
};
|
|
clk_osc48m: osc48m {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-clock";
|
|
clock-frequency = <48000000>;
|
|
clock-output-names = "osc48m";
|
|
};
|
|
|
|
/* register allwinner,pll-clock */
|
|
clk_pll_cpu: pll_cpu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_cpu";
|
|
};
|
|
clk_pll_ddr0: pll_ddr0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_ddr0";
|
|
};
|
|
clk_pll_periph0: pll_periph0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
assigned-clock-rates = <600000000>;
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_periph0";
|
|
};
|
|
clk_pll_periph1: pll_periph1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
assigned-clock-rates = <600000000>;
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_periph1";
|
|
};
|
|
clk_pll_gpu: pll_gpu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_gpu";
|
|
};
|
|
clk_pll_video0: pll_video0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_video0";
|
|
};
|
|
clk_pll_video1: pll_video1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
assigned-clock-rates = <594000000>;
|
|
clock-output-names = "pll_video1";
|
|
};
|
|
clk_pll_ve: pll_ve {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
device_type = "clk_pll_ve";
|
|
lock-mode = "new";
|
|
/*assigned-clock-rates = <??>*/
|
|
clock-output-names = "pll_ve";
|
|
};
|
|
clk_pll_de: pll_de {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
assigned-clock-rates = <696000000>;
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_de";
|
|
};
|
|
clk_pll_hsic: pll_hsic {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_hsic";
|
|
};
|
|
clk_pll_audio: pll_audio {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "new";
|
|
clock-output-names = "pll_audio";
|
|
};
|
|
|
|
/* register fixed factor clock*/
|
|
clk_pll_periph0x2: pll_periph0x2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_periph0>;
|
|
clock-mult = <2>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_periph0x2";
|
|
};
|
|
clk_pll_periph0x4: pll_periph0x4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_periph0>;
|
|
clock-mult = <4>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_periph0x4";
|
|
};
|
|
clk_periph32k: periph32k {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_periph0>;
|
|
clock-mult = <2>;
|
|
clock-div = <36621>;
|
|
clock-output-names = "periph32k";
|
|
};
|
|
clk_pll_periph1x2: pll_periph1x2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_periph1>;
|
|
clock-mult = <2>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_periph1x2";
|
|
};
|
|
clk_pll_audiox4: pll_audiox4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_audio>;
|
|
clock-mult = <4>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_audiox4";
|
|
};
|
|
clk_pll_audiox2: pll_audiox2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_audio>;
|
|
clock-mult = <2>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_audiox2";
|
|
};
|
|
clk_pll_video0x4: pll_video0x4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_video0>;
|
|
clock-mult = <4>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_video0x4";
|
|
};
|
|
clk_pll_video1x4: pll_video1x4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_video1>;
|
|
clock-mult = <4>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_video1x4";
|
|
};
|
|
clk_hoscd2: hoscd2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_hosc>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
clock-output-names = "hoscd2";
|
|
};
|
|
clk_osc48md4: osc48md4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_osc48m>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
clock-output-names = "osc48md4";
|
|
};
|
|
clk_pll_periph0d6: pll_periph0d6 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_periph0>;
|
|
clock-mult = <1>;
|
|
clock-div = <6>;
|
|
clock-output-names = "pll_periph0d6";
|
|
};
|
|
|
|
/* register allwinner,periph-clock */
|
|
clk_cpu: cpu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "cpu";
|
|
};
|
|
clk_axi: axi {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "axi";
|
|
};
|
|
clk_cpuapb: cpuapb {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "cpuapb";
|
|
};
|
|
clk_psi: psi {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "psi";
|
|
};
|
|
clk_ahb1: ahb1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ahb1";
|
|
};
|
|
clk_ahb2: ahb2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ahb2";
|
|
};
|
|
clk_ahb3: ahb3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ahb3";
|
|
};
|
|
clk_apb1: apb1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "apb1";
|
|
};
|
|
clk_apb2: apb2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "apb2";
|
|
};
|
|
clk_mbus: mbus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "mbus";
|
|
};
|
|
clk_de: de {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <&clk_pll_de>;
|
|
assigned-clock-rates = <696000000>;
|
|
assigned-clocks = <&clk_de>;
|
|
clock-output-names = "de";
|
|
};
|
|
clk_di: di {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "di";
|
|
};
|
|
clk_gpu: gpu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "gpu";
|
|
};
|
|
clk_ce: ce {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ce";
|
|
};
|
|
clk_ve: ve {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ve";
|
|
};
|
|
clk_emce: emce {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "emce";
|
|
};
|
|
clk_vp9: vp9 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "vp9";
|
|
};
|
|
clk_dma: dma {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "dma";
|
|
};
|
|
clk_msgbox: msgbox {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "msgbox";
|
|
};
|
|
clk_hwspinlock_rst: hwspinlock_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "hwspinlock_rst";
|
|
};
|
|
clk_hwspinlock_bus: hwspinlock_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "hwspinlock_bus";
|
|
};
|
|
clk_hstimer: hstimer {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "hstimer";
|
|
};
|
|
clk_avs: avs {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "avs";
|
|
};
|
|
clk_dbgsys: dbgsys {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "dbgsys";
|
|
};
|
|
clk_pwm: pwm {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pwm";
|
|
};
|
|
clk_iommu: iommu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "iommu";
|
|
};
|
|
clk_sdram: sdram {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdram";
|
|
};
|
|
clk_nand0: nand0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "nand0";
|
|
};
|
|
clk_nand1: nand1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "nand1";
|
|
};
|
|
clk_sdmmc0_mod: sdmmc0_mod {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc0_mod";
|
|
};
|
|
clk_sdmmc0_bus: sdmmc0_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc0_bus";
|
|
};
|
|
clk_sdmmc0_rst: sdmmc0_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc0_rst";
|
|
};
|
|
clk_sdmmc1_mod: sdmmc1_mod {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc1_mod";
|
|
};
|
|
clk_sdmmc1_bus: sdmmc1_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc1_bus";
|
|
};
|
|
clk_sdmmc1_rst: sdmmc1_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc1_rst";
|
|
};
|
|
clk_sdmmc2_mod: sdmmc2_mod {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc2_mod";
|
|
};
|
|
clk_sdmmc2_bus: sdmmc2_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc2_bus";
|
|
};
|
|
clk_sdmmc2_rst: sdmmc2_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc2_rst";
|
|
};
|
|
clk_uart0: uart0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart0";
|
|
};
|
|
clk_uart1: uart1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart1";
|
|
};
|
|
clk_uart2: uart2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart2";
|
|
};
|
|
clk_uart3: uart3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart3";
|
|
};
|
|
clk_twi0: twi0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "twi0";
|
|
};
|
|
clk_twi1: twi1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "twi1";
|
|
};
|
|
clk_twi2: twi2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "twi2";
|
|
};
|
|
clk_twi3: twi3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "twi3";
|
|
};
|
|
clk_scr0: scr0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "scr0";
|
|
};
|
|
clk_scr1: scr1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "scr1";
|
|
};
|
|
clk_spi0: spi0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "spi0";
|
|
};
|
|
clk_spi1: spi1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "spi1";
|
|
};
|
|
clk_gmac: gmac {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "gmac";
|
|
};
|
|
clk_sata: sata {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sata";
|
|
};
|
|
clk_sata_24m: sata_24m {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sata_24m";
|
|
};
|
|
clk_ts: ts {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ts";
|
|
};
|
|
clk_irtx: irtx {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "irtx";
|
|
};
|
|
clk_ths: ths {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ths";
|
|
};
|
|
clk_i2s0: i2s0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "i2s0";
|
|
};
|
|
clk_i2s1: i2s1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "i2s1";
|
|
};
|
|
clk_i2s2: i2s2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "i2s2";
|
|
};
|
|
clk_i2s3: i2s3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "i2s3";
|
|
};
|
|
clk_spdif: spdif {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "spdif";
|
|
};
|
|
clk_dmic: dmic {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "dmic";
|
|
};
|
|
clk_ahub: ahub {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ahub";
|
|
};
|
|
clk_usbphy0: usbphy0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbphy0";
|
|
};
|
|
clk_usbphy1: usbphy1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbphy1";
|
|
};
|
|
clk_usbphy3: usbphy3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbphy3";
|
|
};
|
|
clk_usbohci0: usbohci0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbohci0";
|
|
};
|
|
clk_usbohci0_12m: usbohci0_12m {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbohci0_12m";
|
|
};
|
|
clk_usbohci3: usbohci3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbohci3";
|
|
};
|
|
clk_usbohci3_12m: usbohci3_12m {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbohci3_12m";
|
|
};
|
|
clk_usbehci0: usbehci0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbehci0";
|
|
};
|
|
clk_usbehci3: usbehci3 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbehci3";
|
|
};
|
|
clk_usb3_0_host: usb3_0_host {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usb3_0_host";
|
|
};
|
|
clk_usbotg: usbotg {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbotg";
|
|
};
|
|
clk_usbhsic: usbhsic {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbhsic";
|
|
};
|
|
clk_pcieref: pcieref {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pcieref";
|
|
};
|
|
clk_pciemaxi: pciemaxi {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <&clk_pciemaxi>;
|
|
assigned-clock-rates = <200000000>;
|
|
clock-output-names = "pciemaxi";
|
|
};
|
|
clk_pcieaux: pcieaux {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-rates = <1000000>;
|
|
assigned-clocks = <&clk_pcieaux>;
|
|
clock-output-names = "pcieaux";
|
|
};
|
|
clk_pcie_bus: pcie_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pcie_bus";
|
|
};
|
|
clk_pcie_power: pcie_power {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pcie_power";
|
|
};
|
|
clk_pcie_rst: pcie_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pcie_rst";
|
|
};
|
|
clk_hdmi: hdmi {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
|
assigned-clocks = <&clk_hdmi>;
|
|
clock-output-names = "hdmi";
|
|
};
|
|
clk_hdmi_slow: hdmi_slow {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <&clk_hdmi_slow>;
|
|
clock-output-names = "hdmi_slow";
|
|
};
|
|
clk_hdmi_cec: hdmi_cec {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <&clk_hdmi_cec>;
|
|
clock-output-names = "hdmi_cec";
|
|
};
|
|
clk_display_top: display_top {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "display_top";
|
|
};
|
|
clk_tcon_lcd: tcon_lcd {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "tcon_lcd";
|
|
};
|
|
clk_tcon_tv: tcon_tv {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
|
assigned-clocks = <&clk_tcon_tv>;
|
|
clock-output-names = "tcon_tv";
|
|
};
|
|
clk_csi_misc: csi_misc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "csi_misc";
|
|
};
|
|
clk_csi_top: csi_top {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "csi_top";
|
|
};
|
|
clk_csi_master0: csi_master0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "csi_master0";
|
|
};
|
|
clk_hdmi_hdcp: hdmi_hdcp {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <&clk_pll_periph1>;
|
|
assigned-clocks = <&clk_hdmi_hdcp>;
|
|
clock-output-names = "hdmi_hdcp";
|
|
};
|
|
clk_pio: pio {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pio";
|
|
};
|
|
|
|
/*cpus space clocks from PRCM-SPEC*/
|
|
clk_cpurcir: cpurcir {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurcir";
|
|
};
|
|
clk_losc_out: losc_out {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "losc_out";
|
|
};
|
|
/* clk below are read only , just to keep a clock tree */
|
|
clk_cpurcpus_pll: cpurcpus_pll {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurcpus_pll";
|
|
};
|
|
clk_cpurcpus: cpurcpus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurcpus";
|
|
};
|
|
clk_cpurahbs: cpurahbs {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurahbs";
|
|
};
|
|
clk_cpurapbs1: cpurapbs1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurapbs1";
|
|
};
|
|
clk_cpurapbs2_pll: cpurapbs2_pll {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurapbs2_pll";
|
|
};
|
|
clk_cpurapbs2: cpurapbs2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurapbs2";
|
|
};
|
|
clk_cpurpio: cpurpio {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "cpurpio";
|
|
};
|
|
clk_spwm: spwm {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "spwm";
|
|
};
|
|
clk_dcxo_out: dcxo_out {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-cpus-clock";
|
|
clock-output-names = "dcxo_out";
|
|
};
|
|
};
|
|
};
|