148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
/*
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* arch/arm/mach-sunxi/platsmp-v2.h
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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* http://www.allwinnertech.com
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*
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* Author: east_yang <yangdong@allwinnertech.com>
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*
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* sunxi smp ops header file for platform v2
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __PLATSMP_V2_H__
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#define __PLATSMP_V2_H__
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#define C0_RST_CTRL (0x00)
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#define C0_CTRL_REG0 (0x10)
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#define C0_CPU_STATUS (0X80)
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#define DBG_REG0 (0xc0)
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#define C0_CPUX_RESET_REG (0x40)
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#define C0_CPUX_PWROFF_GATING (0x44)
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#define C0_CPUX_PWR_SW(cpu) (0x50 + cpu * 4)
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#define CORE_RESET_OFFSET (0x00)
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#define C0_CPUX_RESET_OFFSET (0x00)
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#define L1_RST_DISABLE_OFFSET (0x00)
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#define POROFF_GATING_CPUX_OFFSET (0x00)
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#define C_DBGPWRDUP_OFFSET (0x00)
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#define STANDBYWFI_OFFSET (0x10)
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static inline int sunxi_is_wfi_mode(int cpu)
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{
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return readl(sunxi_cpucfg_base + C0_CPU_STATUS) &
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(1 << (STANDBYWFI_OFFSET + cpu));
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}
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static inline void sunxi_enable_cpu(int cpu)
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{
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unsigned int value;
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pr_debug("[%s]: start\n", __func__);
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/* assert cpu core reset low */
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value = readl(sunxi_cpucfg_base + C0_RST_CTRL);
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value &= (~(0x1 << (CORE_RESET_OFFSET + cpu)));
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writel(value, sunxi_cpucfg_base + C0_RST_CTRL);
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/* assert power on reset low */
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value = readl(sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
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value &= (~(0x1 << (C0_CPUX_RESET_OFFSET + cpu)));
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writel(value, sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
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/* L1RSTDISABLE hold low */
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value = readl(sunxi_cpucfg_base + C0_CTRL_REG0);
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value &= (~(0x1 << (L1_RST_DISABLE_OFFSET + cpu)));
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writel(value, sunxi_cpucfg_base + C0_CTRL_REG0);
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/* DBGPWRDUPx hold low */
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value = readl(sunxi_cpucfg_base + DBG_REG0);
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value &= (~(0x1 << (C_DBGPWRDUP_OFFSET + cpu)));
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writel(value, sunxi_cpucfg_base + DBG_REG0);
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/* hold power-off gating */
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value = readl(sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING);
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value |= ((0x1 << (POROFF_GATING_CPUX_OFFSET + cpu)));
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writel(value, (sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING));
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/* Release power switch */
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writel(0xFE, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(20);
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writel(0xFC, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(10);
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writel(0xF8, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(10);
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writel(0xF0, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(10);
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writel(0xC0, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(10);
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writel(0x00, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(20);
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while (readl(sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu)) != 0x00)
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;
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/* Clear power-off gating */
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value = readl(sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING);
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value &= (~(0x1 << (POROFF_GATING_CPUX_OFFSET + cpu)));
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writel(value, (sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING));
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udelay(20);
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/* Deassert power on reset high */
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value = readl(sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
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value |= (0x1 << (C0_CPUX_RESET_OFFSET + cpu));
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writel(value, sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
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/* Deassert core reset high */
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value = readl(sunxi_cpucfg_base + C0_RST_CTRL);
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value |= (0x1 << (CORE_RESET_OFFSET + cpu));
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writel(value, sunxi_cpucfg_base + C0_RST_CTRL);
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/* Assert DBGPWRDUPx high */
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value = readl(sunxi_cpucfg_base + DBG_REG0);
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value |= (0x1 << (C_DBGPWRDUP_OFFSET + cpu));
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writel(value, sunxi_cpucfg_base + DBG_REG0);
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pr_debug("[%s]: end\n", __func__);
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}
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static inline void sunxi_disable_cpu(int cpu)
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{
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unsigned int value;
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pr_debug("[%s]: start\n", __func__);
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/* assert cpu core reset */
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value = readl(sunxi_cpucfg_base + C0_RST_CTRL);
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value &= (~(0x1 << (CORE_RESET_OFFSET + cpu)));
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writel(value, sunxi_cpucfg_base + C0_RST_CTRL);
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/* Deassert DBGPWRDUPx low */
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value = readl(sunxi_cpucfg_base + DBG_REG0);
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value &= (~(0x1 << (C_DBGPWRDUP_OFFSET + cpu)));
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writel(value, sunxi_cpucfg_base + DBG_REG0);
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/* power gating off */
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value = readl(sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING);
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value |= (0x1 << (POROFF_GATING_CPUX_OFFSET + cpu));
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writel(value, (sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING));
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udelay(20);
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/* power switch off */
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writel(0xff, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
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udelay(30);
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while (readl(sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu)) != 0xff)
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;
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pr_debug("[%s]: end\n", __func__);
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}
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#endif /* __PLATSMP_V2_H__ */
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