173 lines
5.3 KiB
C
173 lines
5.3 KiB
C
/*
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* arch/arm/mach-sunxi/include/mach/sun8i/platsmp.h
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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* http://www.allwinnertech.com
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*
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* Author: liugang <liugang@allwinnertech.com>
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*
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* sun8i smp ops header file
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __SUN8I_PLAT_SMP_H
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#define __SUN8I_PLAT_SMP_H
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#ifdef CONFIG_ARCH_SUN8IW6P1
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#include <asm/smp_plat.h>
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#include <mach/sunxi-smc.h>
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static inline void enable_cpu(int cpu_nr)
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{
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unsigned int cluster;
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unsigned int cpu;
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unsigned int mpidr;
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unsigned int value;
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mpidr = cpu_logical_map(cpu_nr);
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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/* step1: power switch on */
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sunxi_smc_writel(0x00, SUNXI_R_PRCM_VBASE + SUNXI_CPU_PWR_CLAMP(cluster, cpu));
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while (0x00 != sunxi_smc_readl(SUNXI_R_PRCM_VBASE + SUNXI_CPU_PWR_CLAMP(cluster, cpu)))
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;
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mdelay(5);
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/* step2: power gating off */
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value = sunxi_smc_readl(SUNXI_R_PRCM_VBASE + SUNXI_CLUSTER_PWROFF_GATING(cluster));
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value &= (~(0x1<<cpu));
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sunxi_smc_writel(value, SUNXI_R_PRCM_VBASE + SUNXI_CLUSTER_PWROFF_GATING(cluster));
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mdelay(2);
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/* step3: clear reset */
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value = sunxi_smc_readl(SUNXI_R_CPUCFG_VBASE + SUNXI_CLUSTER_PWRON_RESET(cluster));
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value |= (1<<cpu);
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sunxi_smc_writel(value, SUNXI_R_CPUCFG_VBASE + SUNXI_CLUSTER_PWRON_RESET(cluster));
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/* step4: core reset */
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value = sunxi_smc_readl(SUNXI_CPUXCFG_VBASE + SUNXI_CPU_RST_CTRL(cluster));
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value |= (1<<cpu);
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sunxi_smc_writel(value, SUNXI_CPUXCFG_VBASE + SUNXI_CPU_RST_CTRL(cluster));
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}
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static inline void disable_cpu(int cpu_nr)
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{
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unsigned int cluster;
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unsigned int cpu;
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unsigned int mpidr;
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unsigned int value;
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mpidr = cpu_logical_map(cpu_nr);
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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/* step1: core deassert */
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value = sunxi_smc_readl(SUNXI_CPUXCFG_VBASE + SUNXI_CPU_RST_CTRL(cluster));
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value &= ~(1 << cpu);
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sunxi_smc_writel(value, SUNXI_CPUXCFG_VBASE + SUNXI_CPU_RST_CTRL(cluster));
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/* step2: deassert */
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value = sunxi_smc_readl(SUNXI_R_CPUCFG_VBASE + SUNXI_CLUSTER_PWRON_RESET(cluster));
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value &= ~(1 << cpu);
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sunxi_smc_writel(value, SUNXI_R_CPUCFG_VBASE + SUNXI_CLUSTER_PWRON_RESET(cluster));
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/* step3: enable power gating off */
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mdelay(2);
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value = sunxi_smc_readl(SUNXI_R_PRCM_VBASE + SUNXI_CLUSTER_PWROFF_GATING(cluster));
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value |= 0x1<<cpu;
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sunxi_smc_writel(value, SUNXI_R_PRCM_VBASE + SUNXI_CLUSTER_PWROFF_GATING(cluster));
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/* step1: power switch on */
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mdelay(5);
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sunxi_smc_writel(0xff, SUNXI_R_PRCM_VBASE + SUNXI_CPU_PWR_CLAMP(cluster, cpu));
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mdelay(1);
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}
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#else
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static inline void enable_cpu(int cpu)
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{
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u32 pwr_reg;
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/* step1: Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW.
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* Ensure DBGPWRDUP is held LOW to prevent any external
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* debug access to the processor.
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*/
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/* assert cpu core reset */
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sunxi_smc_writel(0, (void *)(SUNXI_R_CPUCFG_VBASE + CPUX_RESET_CTL(cpu)));
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/* L1RSTDISABLE hold low */
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pwr_reg = sunxi_smc_readl((void *)(SUNXI_R_CPUCFG_VBASE + SUNXI_CPUCFG_GENCTL));
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pwr_reg &= ~(1<<cpu);
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sunxi_smc_writel(pwr_reg, (void *)(SUNXI_R_CPUCFG_VBASE + SUNXI_CPUCFG_GENCTL));
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#ifdef CONFIG_ARCH_SUN8IW1
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/* step2: release power clamp */
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/* write bit3, bit4 to 0 */
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sunxi_smc_writel(0xe7, (void *)(SUNXI_R_PRCM_VBASE + SUNXI_CPUX_PWR_CLAMP(cpu)));
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while ((0xe7) != sunxi_smc_readl((void *)(SUNXI_R_CPUCFG_VBASE + SUNXI_CPUX_PWR_CLAMP_STATUS(cpu))))
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;
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/* write 012567 bit to 0 */
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sunxi_smc_writel(0x00, (void *)(SUNXI_R_PRCM_VBASE + SUNXI_CPUX_PWR_CLAMP(cpu)));
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while ((0x00) != sunxi_smc_readl((void *)(SUNXI_R_CPUCFG_VBASE + SUNXI_CPUX_PWR_CLAMP_STATUS(cpu))))
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;
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mdelay(2);
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#endif
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/* step3: clear power-off gating */
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pwr_reg = sunxi_smc_readl((void *)(SUNXI_R_PRCM_VBASE + SUNXI_CPU_PWROFF_REG));
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pwr_reg &= ~(0x00000001<<cpu);
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sunxi_smc_writel(pwr_reg, (void *)(SUNXI_R_PRCM_VBASE + SUNXI_CPU_PWROFF_REG));
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mdelay(1);
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/* step4: de-assert core reset */
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sunxi_smc_writel(3, (void *)(SUNXI_R_CPUCFG_VBASE + CPUX_RESET_CTL(cpu)));
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}
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static inline void disable_cpu(int cpu)
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{
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u32 pwr_reg;
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sunxi_smc_writel(0, (void *)(SUNXI_R_CPUCFG_VBASE + CPUX_RESET_CTL(cpu)));
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/* step9: set up power-off signal */
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pwr_reg = sunxi_smc_readl(IO_ADDRESS(SUNXI_R_PRCM_PBASE) + SUNXI_CPU_PWROFF_REG);
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pwr_reg |= (1<<cpu);
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sunxi_smc_writel(pwr_reg, IO_ADDRESS(SUNXI_R_PRCM_PBASE) + SUNXI_CPU_PWROFF_REG);
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usleep_range(1000, 1000);
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#ifdef CONFIG_ARCH_SUN8IW1
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/* step10: active the power output clamp */
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sunxi_smc_writel(0xff, IO_ADDRESS(SUNXI_R_PRCM_PBASE) + SUNXI_CPUX_PWR_CLAMP(cpu));
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#endif
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}
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#endif
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/*
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* set the sencodary cpu boot entry address.
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*/
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static inline void sunxi_set_secondary_entry(void *entry)
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{
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#ifdef CONFIG_ARCH_SUN8IW6P1
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writel((u32)entry, (void *)(SUNXI_R_CPUCFG_VBASE + PRIVATE_REG0));
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#else
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writel((u32)entry, (void *)(SUNXI_R_CPUCFG_VBASE + SUNXI_CPUCFG_P_REG0));
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#endif
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}
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/*
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* get the sencodary cpu boot entry address.
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*/
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static inline void *sunxi_get_secondary_entry(void)
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{
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#ifdef CONFIG_ARCH_SUN8IW6P1
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return (void *)sunxi_smc_readl((void *)(SUNXI_R_CPUCFG_VBASE + PRIVATE_REG0));
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#else
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return (void *)readl(SUNXI_R_CPUCFG_VBASE + SUNXI_CPUCFG_P_REG0);
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#endif
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}
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#endif /* __SUN8I_PLAT_SMP_H */
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