338 lines
7.8 KiB
C
338 lines
7.8 KiB
C
/*
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* Some macro and struct of SUNXI SecuritySystem controller.
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*
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* Copyright (C) 2013 Allwinner.
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*
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* Mintow <duanmintao@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef _SUNXI_SECURITY_SYSTEM_H_
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#define _SUNXI_SECURITY_SYSTEM_H_
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#include <crypto/aes.h>
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#include <crypto/sha.h>
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#include <crypto/hash.h>
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#include <crypto/algapi.h>
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#include <linux/scatterlist.h>
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#include <linux/interrupt.h>
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/* flag for sunxi_ss_t.flags */
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#define SS_FLAG_MODE_MASK 0xFF
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#define SS_FLAG_NEW_KEY BIT(0)
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#define SS_FLAG_NEW_IV BIT(1)
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#define SS_FLAG_INIT BIT(2)
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#define SS_FLAG_FAST BIT(3)
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#define SS_FLAG_BUSY BIT(4)
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#define SS_FLAG_TRNG BIT(8)
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/* flag for crypto_async_request.flags */
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#define SS_FLAG_AES BIT(16)
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#define SS_FLAG_HASH BIT(17)
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/* Define the capability of SS controller. */
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#ifdef CONFIG_ARCH_SUN8IW6
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#define SS_CTR_MODE_ENABLE 1
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#define SS_CTS_MODE_ENABLE 1
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#define SS_SHA224_ENABLE 1
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#define SS_SHA256_ENABLE 1
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#define SS_TRNG_ENABLE 1
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#define SS_TRNG_POSTPROCESS_ENABLE 1
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#define SS_RSA512_ENABLE 1
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#define SS_RSA1024_ENABLE 1
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#define SS_RSA2048_ENABLE 1
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#define SS_RSA3072_ENABLE 1
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#define SS_IDMA_ENABLE 1
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#define SS_MULTI_FLOW_ENABLE 1
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#define SS_SHA_SWAP_PRE_ENABLE 1 /* The initial IV need to be converted. */
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#define SS_DMA_BUF_SIZE SZ_8K
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#define SS_RSA_MIN_SIZE (512/8) /* in Bytes. 512 bits */
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#define SS_RSA_MAX_SIZE (3072/8) /* in Bytes. 3072 bits */
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#define SS_FLOW_NUM 2
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#endif
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#if defined(CONFIG_ARCH_SUN50I) || defined(CONFIG_ARCH_SUN8IW11) \
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|| defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN8IW15) \
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|| defined(CONFIG_ARCH_SUN8IW7)
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#define SS_CTR_MODE_ENABLE 1
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#define SS_CTS_MODE_ENABLE 1
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#define SS_SHA224_ENABLE 1
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#define SS_SHA256_ENABLE 1
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#define SS_HMAC_SHA1_ENABLE 1
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#define SS_HMAC_SHA256_ENABLE 1
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#define SS_RSA512_ENABLE 1
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#define SS_RSA1024_ENABLE 1
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#define SS_RSA2048_ENABLE 1
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#define SS_RSA3072_ENABLE 1
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#define SS_RSA4096_ENABLE 1
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#define SS_DH512_ENABLE 1
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#define SS_DH1024_ENABLE 1
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#define SS_DH2048_ENABLE 1
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#define SS_DH3072_ENABLE 1
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#define SS_DH4096_ENABLE 1
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#ifdef CONFIG_EVB_PLATFORM
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#define SS_TRNG_ENABLE 1
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#define SS_TRNG_POSTPROCESS_ENABLE 1
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#endif
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#define SS_SHA_SWAP_PRE_ENABLE 1 /* The initial IV need to be converted. */
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#define SS_RSA_MIN_SIZE (512/8) /* in Bytes. 512 bits */
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#ifdef CONFIG_ARCH_SUN8IW7
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#define SS_RSA_MAX_SIZE (4096/8) /*in Bytes. 4096 bits*/
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#else
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#define SS_RSA_MAX_SIZE (2048/8) /* in Bytes. 2048 bits */
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#endif
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#define SS_SCATTER_ENABLE 1
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#ifdef CONFIG_ARCH_SUN8IW7
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#define SS_FLOW_NUM 1
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#else
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#define SS_FLOW_NUM 4
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#endif
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#if defined(CONFIG_ARCH_SUN8IW7)
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#define SS_ECC_ENABLE 1
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#define SS_RSA_PREPROCESS_ENABLE 1
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#define SS_RSA_CLK_ENABLE 1
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#endif
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#endif /**/
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#if defined(CONFIG_ARCH_SUN8IW11) || defined(CONFIG_ARCH_SUN8IW12) \
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|| defined(CONFIG_ARCH_SUN8IW7)
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#define SS_CFB_MODE_ENABLE 1
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#define SS_OFB_MODE_ENABLE 1
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#define SS_SHA384_ENABLE 1
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#define SS_SHA512_ENABLE 1
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#define SS_SUPPORT_CE_V3_1 1
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#endif
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#if defined(CONFIG_ARCH_SUN50IW1) || defined(CONFIG_ARCH_SUN50IW2)
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#define SS_SUPPORT_CE_V3_1 1
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#endif
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#if defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN50IW6) || \
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defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW8)
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#define SS_XTS_MODE_ENABLE 1
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#define SS_CFB_MODE_ENABLE 1
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#define SS_OFB_MODE_ENABLE 1
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#define SS_HASH_HW_PADDING 1
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#define SS_HASH_HW_PADDING_ALIGN_CASE 1
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#define SS_SHA384_ENABLE 1
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#define SS_SHA512_ENABLE 1
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#define SS_HMAC_SHA256_ENABLE 1
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#define SS_RSA3072_ENABLE 1
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#define SS_RSA4096_ENABLE 1
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#define SS_DH3072_ENABLE 1
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#define SS_DH4096_ENABLE 1
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#define SS_DH_ENABLE 1
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#define SS_ECC_ENABLE 1
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#define SS_SUPPORT_CE_V3_2 1
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#undef SS_TRNG_POSTPROCESS_ENABLE
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#endif
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#if defined(SS_RSA512_ENABLE) || defined(SS_RSA1024_ENABLE) \
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|| defined(SS_RSA2048_ENABLE) || defined(SS_RSA3072_ENABLE) \
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|| defined(SS_RSA4096_ENABLE)
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#define SS_RSA_ENABLE 1
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#endif
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#if defined(SS_DH512_ENABLE) || defined(SS_DH1024_ENABLE) \
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|| defined(SS_DH2048_ENABLE) || defined(SS_DH3072_ENABLE) \
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|| defined(SS_DH4096_ENABLE)
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#define SS_DH_ENABLE 1
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#endif
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#define SS_PRNG_SEED_LEN (192/8) /* 192 bits */
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#define SS_RNG_MAX_LEN SZ_8K
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#define SUNXI_SS_DEV_NAME "ss"
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#if defined(SS_SHA384_ENABLE) || defined(SS_SHA512_ENABLE)
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#define SS_DIGEST_SIZE SHA512_DIGEST_SIZE
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#define SS_HASH_PAD_SIZE (SHA512_BLOCK_SIZE * 2)
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#else
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#define SS_DIGEST_SIZE SHA256_DIGEST_SIZE
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#define SS_HASH_PAD_SIZE (SHA1_BLOCK_SIZE * 2)
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#endif
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#ifdef CONFIG_EVB_PLATFORM
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#define SS_WAIT_TIME 2000 /* 2s, used in wait_for_completion_timeout() */
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#else
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#define SS_WAIT_TIME 40000 /* 40s, used in wait_for_completion_timeout() */
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#endif
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#define SS_ALG_PRIORITY 260
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/* For debug */
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#define SS_DBG(fmt, arg...) pr_debug("%s()%d - "fmt, __func__, __LINE__, ##arg)
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#define SS_ERR(fmt, arg...) pr_err("%s()%d - "fmt, __func__, __LINE__, ##arg)
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#define SS_EXIT() SS_DBG("%s\n", "Exit")
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#define SS_ENTER() SS_DBG("%s\n", "Enter ...")
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#define SS_FLOW_AVAILABLE 0
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#define SS_FLOW_UNAVAILABLE 1
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#define SS_RES_NS_INDEX 0
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#define SS_RES_S_INDEX 1
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#ifdef CONFIG_EVB_PLATFORM
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#define SS_RES_INDEX SS_RES_NS_INDEX
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#else
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#define SS_RES_INDEX SS_RES_NS_INDEX
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#endif
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#ifdef SS_SCATTER_ENABLE
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/* CE: Crypto Engine, start using CE from sun8iw7/sun8iw9 */
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#define CE_SCATTERS_PER_TASK 8
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typedef struct {
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u32 addr;
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u32 len; /* in word (4 bytes). Exception: in byte for AES_CTS */
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} ce_scatter_t;
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/* The descriptor of a CE task. */
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typedef struct ce_task_desc {
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u32 chan_id;
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u32 comm_ctl;
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u32 sym_ctl;
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u32 asym_ctl;
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u32 key_addr;
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u32 iv_addr;
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u32 ctr_addr;
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u32 data_len; /* in word(4 byte). Exception: in byte for AES_CTS */
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ce_scatter_t src[CE_SCATTERS_PER_TASK];
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ce_scatter_t dst[CE_SCATTERS_PER_TASK];
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struct ce_task_desc *next;
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u32 reserved[3];
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} ce_task_desc_t;
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#endif
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typedef struct {
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u32 dir;
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u32 nents;
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struct dma_chan *chan;
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struct scatterlist *sg;
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#ifdef SS_IDMA_ENABLE
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struct sg_table sgt_for_cp; /* Used to copy data from/to user space. */
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#endif
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#ifdef SS_SCATTER_ENABLE
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u32 has_padding;
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u8 *padding;
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struct scatterlist *last_sg;
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#endif
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} ss_dma_info_t;
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typedef struct {
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u32 dir;
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u32 type;
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u32 mode;
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#ifdef SS_CFB_MODE_ENABLE
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u32 bitwidth; /* the bitwidth of CFB mode */
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#endif
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struct completion done;
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ss_dma_info_t dma_src;
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ss_dma_info_t dma_dst;
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} ss_aes_req_ctx_t;
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/* The common context of AES and HASH */
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typedef struct {
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u32 flow;
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u32 flags;
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} ss_comm_ctx_t;
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typedef struct {
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ss_comm_ctx_t comm; /* must be in the front. */
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#ifdef SS_RSA_ENABLE
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u8 key[SS_RSA_MAX_SIZE];
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u8 iv[SS_RSA_MAX_SIZE];
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#else
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u8 key[AES_MAX_KEY_SIZE];
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u8 iv[AES_MAX_KEY_SIZE];
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#endif
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#ifdef SS_SCATTER_ENABLE
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u8 next_iv[AES_MAX_KEY_SIZE]; /* the next IV/Counter in continue mode */
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#endif
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u32 key_size;
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u32 iv_size;
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u32 cnt; /* in Byte */
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} ss_aes_ctx_t;
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typedef struct {
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ss_comm_ctx_t comm; /* must be in the front. */
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u8 md[SS_DIGEST_SIZE];
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u8 pad[SS_HASH_PAD_SIZE];
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u32 tail_len;
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u32 md_size;
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u32 cnt; /* in Byte */
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} ss_hash_ctx_t;
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typedef struct {
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#ifdef SS_IDMA_ENABLE
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char *buf_src;
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dma_addr_t buf_src_dma;
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char *buf_dst;
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dma_addr_t buf_dst_dma;
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#endif
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#ifdef SS_SCATTER_ENABLE
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ce_task_desc_t task;
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#endif
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struct completion done;
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u32 available;
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} ss_flow_t;
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typedef struct {
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struct platform_device *pdev;
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void __iomem *base_addr; /* for register */
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ss_flow_t flows[SS_FLOW_NUM];
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struct clk *mclk; /* module clock */
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u32 gen_clkrate;
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u32 rsa_clkrate;
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u32 irq;
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s8 dev_name[8];
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spinlock_t lock;
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s32 suspend;
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} sunxi_ss_t;
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/* Global variable */
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extern sunxi_ss_t *ss_dev;
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/* Inner functions declaration */
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void ss_dev_lock(void);
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void ss_dev_unlock(void);
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void __iomem *ss_membase(void);
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void ss_reset(void);
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void ss_clk_set(u32 rate);
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#endif /* end of _SUNXI_SECURITY_SYSTEM_H_ */
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