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SmartAudio/lichee/linux-4.9/arch/arm/boot/dts/sun8iw8p1-soc.dtsi

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/*
* Allwinner Technology CO., Ltd. sun8iw8p1 platform .dtsi
* modified by czy
* modify base on juno.dts & sun8iw10
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw8p1-clk.dtsi"
#include "sun8iw8p1-soc-pinctrl.dtsi"
/ {
model = "sun8iw8";
compatible = "allwinner,sun8iw8p1";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
twi0 = &twi0;
twi1 = &twi1;
spi0 = &spi0;
mmc0 = &sdc0;
mmc1 = &sdc1;
pwm = &pwm;
pwm0 = &pwm0;
pwm1 = &pwm1;
cci0 = &csi_cci0;
csi_res0 = &csi_res0;
mipi0 = &mipi0;
isp0 = &isp0;
vfe0 = &csi0;
global_timer0 = &soc_timer0;
disp = &disp;
lcd0 = &lcd0;
boot_disp = &boot_disp;
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x01c28800 loglevel=8 initcall_debug=1 console=ttyS2 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
cpus {
enable-method = "allwinner,sun8iw8p1";
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-latency = <2000000>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
/*cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;*/
};
};
opp_dvfs_table:opp_dvfs_table {
cluster_num = <1>;
opp_table_count = <1>;
cpu_opp_l_table0: opp_l_table0 {
compatible = "allwinner,opp_l_table0";
opp_count = <8>;
opp-shared;
opp00 {
opp-hz = /bits/ 64 <60000000>;
opp-microvolt = <1040000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp01 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <1040000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp02 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <1040000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp03 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1100000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp04 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1100000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp05 {
opp-hz = /bits/ 64 <912000000>;
opp-microvolt = <1200000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp06 {
opp-hz = /bits/ 64 <1080000000>;
opp-microvolt = <1200000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp07 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1320000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
};
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x4000000>; /* 64M*/
};
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg =
<0x0 0x01c81000 0 0x1000>,/*GIC Dist*/
<0x0 0x01c82000 0 0x2000>,/*GIC CPU*/
<0x0 0x01c84000 0 0x2000>,/*GIC VCPU Control*/
<0x0 0x01c86000 0 0x2000>;/*GIC VCPU*/
interrupts = <GIC_PPI 9 0xf04>;/*GIC Maintenence IRQ*/
};
timer_arch {
compatible = "arm,armv7-timer";
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
arm,cpu-registers-not-fw-configured;
};
wdt: watchdog@01c20ca0 {
compatible = "allwinner,sun8i-wdt";
reg = <0x0 0x01c20ca0 0 0x18>;
};
ion {
compatible = "allwinner,sunxi-ion";
heap_sys_user@0{
compatible = "allwinner,sys_user";
heap-name = "sys_user";
heap-id = <0x0>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_system";
};
heap_sys_contig@0{
compatible = "allwinner,sys_contig";
heap-name = "sys_contig";
heap-id = <0x1>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_contig";
};
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
heap_secure@0{
compatible = "allwinner,secure";
heap-name = "secure";
heap-id = <0x6>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_secure";
};
};
soc: soc@01c00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
device_type = "soc";
ranges;
dma0:dma-controller@01c02000 {
compatible = "allwinner,sun50i-dma";
reg = <0x0 0x01c02000 0x0 0x1000>;
interrupts = <0 50 4>;
clocks = <&clk_dma>;
#dma-cells = <1>;
};
rtc: rtc@01c20400 {
compatible = "allwinner,sun8i-rtc";
device_type = "rtc";
reg = <0x0 0x01c20400 0x0 0x1F0>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
gpr_offset = <0x100>;
gpr_len = <4>;
};
soc_timer0: timer@01c20c00 {
compatible = "allwinner,sunxi-timer";
device_type = "timer";
reg = <0x0 0x01c20c00 0x0 0x400>;
clock-frequency = <24000000>;
timer-prescale = <16>;
interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;/*timer0 src*/
};
uart0: uart@01c28000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart0";
reg = <0x0 0x01c28000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-1 = <&uart0_pins_b>;
uart0_port = <0>;
uart0_type = <2>;
status = "okay";
};
uart1: uart@01c28400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart1";
reg = <0x0 0x01c28400 0x0 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-1 = <&uart1_pins_b>;
uart1_port = <1>;
uart1_type = <2>;
/*status = "disabled";*/
status = "okay";
};
uart2: uart@01c28800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart2";
reg = <0x0 0x01c28800 0x0 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_a>;
pinctrl-1 = <&uart2_pins_b>;
uart2_port = <2>;
uart2_type = <2>;
status = "okay";
/*status = "okay";*/
};
twi0: twi@0x01c2ac00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi0";
reg = <0x0 0x01c2ac00 0x0 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";/*define in linux/pinctrl/pinctrl-state.h*/
pinctrl-0 = <&twi0_pins_a>;
pinctrl-1 = <&twi0_pins_b>;
status = "okay";
pmu0: pmu@0 {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
powerkey0: powerkey@0 {
status = "okay";
};
regulator0: regulator@0 {
status = "okay";
};
axp_gpio0: axp_gpio@0 {
gpio-controller;
#size-cells = <0>;
#gpio-cells = <6>;
status = "okay";
};
charger0: charger@0 {
status = "okay";
};
};
};
twi1: twi@0x01c2b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi1";
reg = <0x0 0x01c2b000 0x0 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi1_pins_a>;
pinctrl-1 = <&twi1_pins_b>;
status = "okay";
};
ve: ve@01c0e000 {
compatible = "allwinner,sunxi-cedar-ve";
reg = <0x0 0x01c0e000 0x0 0x1000>,
<0x0 0x01c00000 0x0 0x10>,
<0x0 0x01c20000 0x0 0x1000>;
interrupts = <GIC_SPI 58 4>;
clocks = <&clk_pll_ve>, <&clk_ve>;
};
spi0: spi@01c68000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi0";
reg = <0x0 0x01c68000 0x0 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
pinctrl-1 = <&spi0_pins_c >;
spi0_cs_number = <1>;
spi0_cs_bitmap = <1>;
/*status = "okay";*/
status = "disabled";
};
sdc0: sdmmc@0x01c0f000 {
compatible = "allwinner,sunxi-mmc-v4p00x";
device_type = "sdc0";
reg = <0x0 0x01c0f000 0x0 0x1000>;
interrupts = <GIC_SPI 60 0x0104>;
clocks =
<&clk_hosc>,<&clk_pll_periph1>,
<&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>,
<&clk_sdmmc0_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc0_pins_a>;
pinctrl-1 = <&sdc0_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
cd-gpios = <&pio PF 6 0 1 2 0>;
/*status = "okay";*/
status = "disabled";
};
sdc1: sdmmc@0x01c10000 {
compatible = "allwinner,sunxi-mmc-v4p00x";
device_type = "sdc1";
reg = <0x0 0x01c10000 0x0 0x1000>;
interrupts = <GIC_SPI 61 0x0104>;
clocks =
<&clk_hosc>,<&clk_pll_periph1>,
<&clk_sdmmc1_mod>,<&clk_sdmmc1_bus>,
<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*status = "okay";*/
status = "disabled";
};
disp: disp@01000000 {
compatible = "allwinner,sunxi-disp";
reg = <0x0 0x01000000 0x0 0x00200000>,/*de*/
<0x0 0x01c0c000 0x0 0x1000>;/*tcon0*/
interrupts = <GIC_SPI 86 0x0104>, /*tcon0*/
<GIC_SPI 95 0x0104>; /*de*/
clocks = <&clk_de>,
<&clk_tcon_lcd0>,
<&clk_lvds0>;
boot_disp = <0>;
fb_base = <0>;
dma-coherent;
status = "okay";
};
lcd0: lcd0@01c0c000 {
compatible = "allwinner,sunxi-lcd0";
pinctrl-names = "active","sleep";
status = "okay";
};
boot_disp: boot_disp {
compatible = "allwinner,boot_disp";
};
wifi:wifi {
device_type = "wifi_conf";
interrupts = <GIC_SPI 107 IRQ_TYPE_NONE>;
reset_pin = <&pio PE 23 1 1 1 0>;/*WL-RESTN*/
irq_pin = <&pio PB 5 6 1 1 0>;/*WL-WAKE-HOST*/
/*status = "okay";*/
status = "disabled";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <0>; /* 0: for device, 1: for host */
usb_detect_type = <1>;
usb_host_init_state = <0>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_luns = <1>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
status = "okay";
};
udc:udc-controller@0x01c19000 {
compatible = "allwinner,sunxi-udc";
reg =
<0x0 0x01c19000 0x0 0x1000>,/*udc base*/
<0x0 0x01c00000 0x0 0x100>;/*sram base*/
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg>;
status = "okay";
};
ehci0:ehci0-controller@0x01c1a000 {
compatible = "allwinner,sunxi-ehci0";
reg =
<0x0 0x01c1a000 0x0 0xFFF>,/*hci0 base*/
<0x0 0x01c00000 0x0 0x100>,/*sram base*/
<0x0 0x01c19000 0x0 0x1000>;/*otg base*/
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x01c1a400 {
compatible = "allwinner,sunxi-ohci0";
reg =
<0x0 0x01c1a000 0x0 0xFFF>,/*hci0 base*/
<0x0 0x01c00000 0x0 0x100>,/*sram base*/
<0x0 0x01c19000 0x0 0x1000>;/*otg base*/
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>,<&clk_usbohci0>;
hci_ctrl_no = <0>;
status = "okay";
};
codec:codec@0x01c22c00 {
compatible = "allwinner,sunxi-internal-codec";
reg =
<0x0 0x01c22c00 0x0 0x2bc>,/*digital baseadress*/
<0x0 0x01c23000 0x0 0x4>;/*analog baseadress*/
clocks = <&clk_pll_audio>,<&clk_adda>;
headphone_vol = <0x3b>;
spker_vol = <0x1b>;
audio_pa_ctrl = <&pio PB 9 1 1 1 1>;
main_mic_vol = <0x4>;
hp_dirused = <0x1>;
headset_mic_vol = <0x4>;
pa_sleep_time = <0x15e>;
status = "okay";
};
cpudai:cpudai0-controller@0x01c22c00 {
compatible = "allwinner,sunxi-internal-cpudai";
reg = <0x0 0x01c22c00 0x0 0x2bc>;/*digital baseadress*/
status = "okay";
};
sndcodec:sound@0 {
compatible = "allwinner,sunxi-codec-machine";
sunxi,cpudai-controller = <&cpudai>;
sunxi,audio-codec = <&codec>;
status = "okay";
};
daudio0:daudio@0x01c22000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x01c22000 0x0 0x58>;
clocks = <&clk_pll_audio>,<&clk_i2s0>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio0_pins_a>;
pinctrl-1 = <&daudio0_pins_b>;
pcm_lrck_period = <0x20>;
pcm_lrckr_period = <0x01>;
slot_width_select = <0x20>;
pcm_lsb_first = <0x0>;
tx_data_mode = <0x0>;
rx_data_mode = <0x0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x0>;
tdm_config = <0x01>;
mclk_div = <0x0>;
tdm_num = <0x0>;
status = "okay";
};
snddaudio0:sound@1{
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio0-controller = <&daudio0>;
status = "okay";
};
pwm: pwm@01c21400 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x01c21400 0x0 0x3c>;
pwm-number = <2>;
pwm-base = <0x0>;
pwms = <&pwm0>, <&pwm1>;
};
pwm0: pwm0@01c21400 {
compatible = "allwinner,sunxi-pwm0";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm0_pins_a>;
pinctrl-1 = <&pwm0_pins_b>;
reg_base = <0x01c21400>;
reg_busy_offset = <0x00>;
reg_busy_shift = <28>;
reg_enable_offset = <0x00>;
reg_enable_shift = <4>;
reg_clk_gating_offset = <0x00>;
reg_clk_gating_shift = <6>;
reg_bypass_offset = <0x00>;
reg_bypass_shift = <9>;
reg_pulse_start_offset = <0x00>;
reg_pulse_start_shift = <8>;
reg_mode_offset = <0x00>;
reg_mode_shift = <7>;
reg_polarity_offset = <0x00>;
reg_polarity_shift = <5>;
reg_period_offset = <0x04>;
reg_period_shift = <16>;
reg_period_width = <16>;
reg_active_offset = <0x04>;
reg_active_shift = <0>;
reg_active_width = <16>;
reg_prescal_offset = <0x00>;
reg_prescal_shift = <0>;
reg_prescal_width = <4>;
};
pwm1: pwm1@01c21400 {
compatible = "allwinner,sunxi-pwm1";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm1_pins_a>;
pinctrl-1 = <&pwm1_pins_b>;
reg_base = <0x01c21400>;
reg_busy_offset = <0x00>;
reg_busy_shift = <29>;
reg_enable_offset = <0x00>;
reg_enable_shift = <19>;
reg_clk_gating_offset = <0x00>;
reg_clk_gating_shift = <21>;
reg_bypass_offset = <0x00>;
reg_bypass_shift = <24>;
reg_pulse_start_offset = <0x00>;
reg_pulse_start_shift = <23>;
reg_mode_offset = <0x00>;
reg_mode_shift = <22>;
reg_polarity_offset = <0x00>;
reg_polarity_shift = <20>;
reg_period_offset = <0x08>;
reg_period_shift = <16>;
reg_period_width = <16>;
reg_active_offset = <0x08>;
reg_active_shift = <0>;
reg_active_width = <16>;
reg_prescal_offset = <0x00>;
reg_prescal_shift = <15>;
reg_prescal_width = <4>;
};
keyboard0:keyboard{
compatible = "allwinner,keyboard_2000mv";
reg = <0x0 0x01c22800 0x0 0x400>;
interrupts = <GIC_SPI 30 IRQ_TYPE_NONE>;
status = "okay";
key_cnt = <4>;
key0 = <190 115>;
key1 = <390 114>;
key2 = <600 119>;
key3 = <800 113>;
};
cryptoengine: ce@1c15000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x01c15000 0x0 0x210>;
interrupts = <GIC_SPI 80 0xff01>;
clock-frequency = <200000000>; /* 200 MHz */
clocks = <&clk_ss>, <&clk_pll_periph0>;
};
wlan:wlan {
compatible = "allwinner,sunxi-wlan";
clocks = "losc_out";
wlan_busnum = <1>;
status = "okay";
};
bt: bt {
compatible = "allwinner,sunxi-bt";
clocks = "losc_out";
status = "okay";
};
btlpm:btlpm {
compatible = "allwinner,sunxi-btlpm";
status = "okay";
};
csi_cci0:cci@0x01cb3000 {
compatible = "allwinner,sunxi-csi_cci";
reg = <0x0 0x01cb3000 0x0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
csi_res0:csi_res@0x01cb0000 {
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x01cb0000 0x0 0x1000>;
clocks = <&clk_csi_s>, <&clk_csi_m>, <&clk_csi_misc>,
<&clk_pll_isp>, <&clk_hosc>, <&clk_pll_periph1>;
clocks-index = <0 1 2 3 4 5>;
status = "okay";
};
mipi0:mipi@0x01cb1000 {
compatible = "allwinner,sunxi-mipi";
/*0x01cb1000--0x01cb2000*/
reg = <0x0 0x01cb1000 0x0 0x1000>;
clocks = <&clk_mipicsi>, <&clk_mipicsi>,
<&clk_pll_periph0>, <&clk_pll_periph0>;
clocks-index = <0xff 1 0xff 3>;/*0xff represent noclk*/
status = "okay";
};
isp0:isp@0x01cb8000 {
compatible = "allwinner,sunxi-isp";
/*0x01cb8000--0x01cb9000*/
reg = <0x0 0x01cb8000 0x0 0x1000>;
status = "okay";
};
csi0:vfe@0 {
device_type= "csi0";
compatible = "allwinner,sunxi-vfe";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default","sleep";
/* mipi don't need to configure the data pin */
/*pinctrl-0 = <&csi0_pins_a>;*/
/*pinctrl-1 = <&csi0_pins_b>;*/
cci_sel = <0>;
csi_sel = <0>;
mipi_sel = <0>;
isp_sel = <0>;
csi0_sensor_list = <0>;
/*PE20 mul_sel = 3, pull = 0, dirv_level = 1, data = 0*/
csi0_mck = <&pio PE 20 3 0 1 0>;
status = "okay";
csi0_dev0:dev@0{
csi0_dev0_mname = "hm2131";
csi0_dev0_twi_id = <1>;
csi0_dev0_twi_addr = <0x48>;
csi0_dev0_pos = "front";
csi0_dev0_isp_used = <1>;
csi0_dev0_fmt = <1>;
csi0_dev0_stby_mode = <0>;
csi0_dev0_vflip = <0>;
csi0_dev0_hflip = <0>;
csi0_dev0_iovdd = "";
csi0_dev0_iovdd_vol = <2800000>;
csi0_dev0_avdd = "";
csi0_dev0_avdd_vol = <2800000>;
csi0_dev0_dvdd = "";
csi0_dev0_dvdd_vol = <1500000>;
csi0_dev0_afvdd = "";
csi0_dev0_afvdd_vol = <>;
csi0_dev0_power_en = <>;
csi0_dev0_reset = <&pio PE 24 1 0 1 0>;
csi0_dev0_pwdn = <&pio PE 23 1 0 1 0>;
csi0_dev0_flash_used = <0>;
csi0_dev0_flash_type = <2>;
csi0_dev0_flash_en = <>;
csi0_dev0_flash_mode = <>;
csi0_dev0_flvdd = "";
csi0_dev0_flvdd_vol = <3300000>;
csi0_dev0_af_pwdn = <>;
csi0_dev0_act_used = <0>;
csi0_dev0_act_name = "ad5820_act";
csi0_dev0_act_slave = <0x18>;
status = "okay";
};
csi0_dev1:dev@1{
csi0_dev1_mname = "n3";
csi0_dev1_twi_addr = <0x60>;
csi0_dev1_pos = "rear";
csi0_dev1_isp_used = <0>;
csi0_dev1_fmt = <0>;
csi0_dev1_stby_mode = <0>;
csi0_dev1_vflip = <0>;
csi0_dev1_hflip = <0>;
csi0_dev1_iovdd = "iovdd-csi";
csi0_dev1_iovdd_vol = <2800000>;
csi0_dev1_avdd = "avdd-csi";
csi0_dev1_avdd_vol = <2800000>;
csi0_dev1_dvdd = "dvdd-csi-18";
csi0_dev1_dvdd_vol = <1500000>;
csi0_dev1_afvdd = "";
csi0_dev1_afvdd_vol = <>;
csi0_dev1_power_en = <>;
csi0_dev1_reset = <>;
csi0_dev1_pwdn = <>;
csi0_dev1_flash_used = <1>;
csi0_dev1_flash_type = <2>;
csi0_dev1_flash_en = <>;
csi0_dev1_flash_mode = <>;
csi0_dev1_flvdd = "vdd-csi-led";
csi0_dev1_flvdd_vol = <3300000>;
csi0_dev1_af_pwdn = <>;
csi0_dev1_act_used = <0>;
csi0_dev1_act_name = "ad5820_act";
csi0_dev1_act_slave = <0x18>;
status = "disabled";
};
};
};
};
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