347 lines
7.9 KiB
Plaintext
Executable File
347 lines
7.9 KiB
Plaintext
Executable File
/*
|
|
* Allwinner sun8iw8p1 clk config info.
|
|
* Modified by czy
|
|
*/
|
|
|
|
/{
|
|
clocks {
|
|
compatible = "allwinner,clk-init";
|
|
device_type = "clocks";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
reg = <0x0 0x01c20000 0x0 0x324>, /*cpux space*/
|
|
<0x0 0x01c20460 0x0 0x4>;
|
|
/* register fixed rate clock*/
|
|
clk_losc: losc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-clock";
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "losc";
|
|
};
|
|
|
|
clk_hosc: hosc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "hosc";
|
|
};
|
|
|
|
/* register allwinner,pll-clock */
|
|
clk_pll_cpu: pll_cpu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
assigned-clock-rates = <528000000>;
|
|
clock-output-names = "pll_cpu";
|
|
};
|
|
clk_pll_audio: pll_audio {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
clock-output-names = "pll_audio";
|
|
};
|
|
clk_adda: adda {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "adda";
|
|
};
|
|
|
|
clk_pll_video: pll_video {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
assigned-clock-rates = <297000000>;
|
|
clock-output-names = "pll_video";
|
|
};
|
|
|
|
clk_pll_isp: pll_isp {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
clock-output-names = "pll_isp";
|
|
};
|
|
clk_csi_s: csi_s {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "csi1_s";
|
|
};
|
|
clk_csi_m: csi_m {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "csi0_m";
|
|
};
|
|
clk_csi_misc: csi_misc {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "csi_misc";
|
|
};
|
|
clk_mipicsi: mipicsi {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "mipicsi";
|
|
};
|
|
|
|
clk_pll_ve: pll_ve {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
clock-output-names = "pll_ve";
|
|
};
|
|
|
|
clk_ve: ve {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ve";
|
|
};
|
|
|
|
clk_pll_ddr0: pll_ddr0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
assigned-clock-rates = <312000000>; /* 156MHZ */
|
|
clock-output-names = "pll_ddr0";
|
|
};
|
|
|
|
clk_pll_ddr1: pll_ddr1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
clock-output-names = "pll_ddr1";
|
|
};
|
|
|
|
clk_pll_periph0: pll_periph0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
clock-output-names = "pll_periph0";
|
|
};
|
|
|
|
clk_pll_periph1: pll_periph1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,pll-clock";
|
|
lock-mode = "old";
|
|
clock-output-names = "pll_periph1";
|
|
};
|
|
|
|
|
|
/* register fixed factor clock*/
|
|
clk_pll_audiox8: pll_audiox8 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_audio>;
|
|
clock-mult = <8>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_audiox8";
|
|
};
|
|
clk_pll_audiox4: pll_audiox4 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_audio>;
|
|
clock-mult = <8>;
|
|
clock-div = <2>;
|
|
clock-output-names = "pll_audiox4";
|
|
};
|
|
clk_pll_audiox2: pll_audiox2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_audio>;
|
|
clock-mult = <8>;
|
|
clock-div = <4>;
|
|
clock-output-names = "pll_audiox2";
|
|
};
|
|
clk_pll_videox2: pll_videox2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,fixed-factor-clock";
|
|
clocks = <&clk_pll_video>;
|
|
clock-mult = <2>;
|
|
clock-div = <1>;
|
|
clock-output-names = "pll_videox2";
|
|
};
|
|
|
|
/* register allwinner,periph-clock */
|
|
clk_cpu: cpu {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "cpu";
|
|
};
|
|
|
|
clk_axi: axi {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "axi";
|
|
};
|
|
|
|
|
|
clk_ahb0: ahb0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ahb0";
|
|
};
|
|
|
|
clk_apb0: apb0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "apb0";
|
|
};
|
|
|
|
clk_ahb1: ahb1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ahb1";
|
|
};
|
|
clk_apb1: apb1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "apb1";
|
|
};
|
|
clk_sdmmc0_mod: sdmmc0_mod {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc0_mod";
|
|
};
|
|
clk_sdmmc0_bus: sdmmc0_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc0_bus";
|
|
};
|
|
clk_sdmmc0_rst: sdmmc0_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc0_rst";
|
|
};
|
|
|
|
clk_sdmmc1_mod: sdmmc1_mod {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc1_mod";
|
|
};
|
|
clk_sdmmc1_bus: sdmmc1_bus {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc1_bus";
|
|
};
|
|
clk_sdmmc1_rst: sdmmc1_rst {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "sdmmc1_rst";
|
|
};
|
|
clk_ss: ss {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "ss";
|
|
};
|
|
clk_spi0: spi0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "spi0";
|
|
};
|
|
|
|
clk_dma: dma {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "dma";
|
|
};
|
|
|
|
clk_uart0: uart0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart0";
|
|
};
|
|
clk_uart1: uart1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart1";
|
|
};
|
|
clk_uart2: uart2 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "uart2";
|
|
};
|
|
clk_twi0: twi0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "twi0";
|
|
};
|
|
clk_twi1: twi1 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "twi1";
|
|
};
|
|
|
|
clk_pio: pio {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pio";
|
|
};
|
|
|
|
clk_usbphy0: usbphy0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbphy0";
|
|
};
|
|
|
|
clk_usbotg: usbotg {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbotg";
|
|
};
|
|
|
|
clk_usbehci0: usbehci0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbehci0";
|
|
};
|
|
|
|
clk_usbohci0: usbohci0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "usbohci0";
|
|
};
|
|
|
|
clk_de: de {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clock-parents = <&clk_pll_periph0>;
|
|
assigned-clock-rates = <300000000>;
|
|
assigned-clocks = <&clk_de>;
|
|
clock-output-names = "de";
|
|
};
|
|
|
|
clk_tcon_lcd0: tcon_lcd0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <&clk_tcon_lcd0>;
|
|
clock-output-names = "tcon";
|
|
};
|
|
|
|
clk_lvds0: lvds0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
assigned-clocks = <&clk_lvds0>;
|
|
clock-output-names = "lvds";
|
|
};
|
|
|
|
clk_pll_periphahb0: pll_periphahb0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "pll_periphahb0";
|
|
};
|
|
|
|
clk_i2s0: i2s0 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "i2s0";
|
|
};
|
|
|
|
clk_losc_out: losc_out {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,periph-clock";
|
|
clock-output-names = "losc_out";
|
|
};
|
|
|
|
|
|
|
|
};
|
|
};
|