507 lines
14 KiB
C
Executable File
507 lines
14 KiB
C
Executable File
/*
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* drivers/soc/sunxi/pm.c
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* (C) Copyright 2017-2023
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* fanqinghua <fanqinghua@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/suspend.h>
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#include <linux/sunxi-gpio.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/regulator/consumer.h>
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#include <linux/arisc/arisc.h>
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#include <asm/cpuidle.h>
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#include <asm/io.h>
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#include <asm/cacheflush.h>
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#include "pm.h"
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static unsigned long time_to_wakeup_ms;
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module_param_named(time_to_wakeup_ms, time_to_wakeup_ms,
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ulong, S_IRUGO | S_IWUSR);
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static super_standby_t *super_standby_para;
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static unsigned int standby_space_size;
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static DEFINE_SPINLOCK(data_lock);
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int enable_gpio_wakeup_src(int para)
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{
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spin_lock(&data_lock);
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super_standby_para->event |= CPUS_WAKEUP_GPIO;
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if (para >= AXP_PIN_BASE) {
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super_standby_para->gpio_enable_bitmap |=
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(WAKEUP_GPIO_AXP((para - AXP_PIN_BASE)));
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} else if (para >= SUNXI_PM_BASE) {
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super_standby_para->gpio_enable_bitmap |=
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(WAKEUP_GPIO_PM((para - SUNXI_PM_BASE)));
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} else if (para >= SUNXI_PL_BASE) {
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super_standby_para->gpio_enable_bitmap |=
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(WAKEUP_GPIO_PL((para - SUNXI_PL_BASE)));
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} else if (para >= SUNXI_PH_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('H'));
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} else if (para >= SUNXI_PG_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('G'));
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} else if (para >= SUNXI_PF_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('F'));
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} else if (para >= SUNXI_PE_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('E'));
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} else if (para >= SUNXI_PD_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('D'));
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} else if (para >= SUNXI_PC_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('C'));
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} else if (para >= SUNXI_PB_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('B'));
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} else if (para >= SUNXI_PA_BASE) {
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super_standby_para->cpux_gpiog_bitmap |=
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(WAKEUP_GPIO_GROUP('A'));
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} else {
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pr_info("cpux need care gpio %d. not support it.\n",
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para);
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}
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spin_unlock(&data_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(enable_gpio_wakeup_src);
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static int sunxi_suspend_valid(suspend_state_t state)
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{
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pr_debug("%s\n", __func__);
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if (!((state > PM_SUSPEND_ON) && (state < PM_SUSPEND_MAX))) {
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pr_err("state (%d) invalid!\n", state);
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return 0;
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}
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return 1;
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}
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static int __sunxi_suspend_enter(void)
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{
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super_standby_para->event |= CPUS_MEM_WAKEUP;
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if (time_to_wakeup_ms > 0) {
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super_standby_para->event |= CPUS_WAKEUP_TIMEOUT;
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super_standby_para->timeout = time_to_wakeup_ms;
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}
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#ifdef CONFIG_AW_AXP
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if (unlikely(axp_regulator_debug & 0x02)) {
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printk(KERN_INFO "power status as follow:");
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axp_regulator_dump();
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}
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#endif
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pr_info("enter standby, wakesrc:0x%x, timeout: %d\n",
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super_standby_para->event,
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super_standby_para->timeout);
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__dma_flush_area(super_standby_para, standby_space_size);
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arm_cpuidle_suspend(3);
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return 0;
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}
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static int sunxi_suspend_enter(suspend_state_t state)
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{
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/*
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* This local variable may be calculated with virt_to_phys
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* in the function of arisc_query_wakeup_source,so it must
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* be located in data section.
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*/
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static unsigned int wakeup_events;
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if (__sunxi_suspend_enter()) {
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pr_err("sunxi suspend failed, need to resume");
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return -1;
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}
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arisc_query_wakeup_source(&wakeup_events);
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pr_info("platform wakeup, standby wakesource is:0x%x\n",
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wakeup_events);
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return 0;
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}
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static const struct platform_suspend_ops sunxi_suspend_ops = {
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.valid = sunxi_suspend_valid,
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.enter = sunxi_suspend_enter,
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};
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static extended_standby_t sun50iw1_superstandby = {
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.id = 0x8,
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en = 0x0,
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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.cpux_clk_state.exit_pll_en = 0x0,
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.cpux_clk_state.pll_change = 0x0,
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.cpux_clk_state.bus_change = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x1,
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.soc_io_state.io_state[0] = {0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_io_state.io_state[1] = {0x01c208b4, 0x000f0f00, 0x00070700},
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};
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static extended_standby_t sun50iw1_usbstandby = {
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.id = 0x2,
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VDD_SYS_BIT) |
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BIT(VCC_IO_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.soc_pwr_dm_state.volt[VDD_SYS_BIT] = 980,
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.soc_pwr_dm_state.volt[VCC_PLL_BIT] = 2500,
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.soc_pwr_dm_state.volt[VCC_IO_BIT] = 3000,
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.cpux_clk_state.osc_en = BIT(OSC_LOSC_BIT),
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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.cpux_clk_state.exit_pll_en = 0x0,
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.cpux_clk_state.pll_change = 0x0,
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.cpux_clk_state.pll_factor[PM_PLL_PERIPH] = {
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.factor1 = 1,
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.factor2 = 1,
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.factor3 = 0,
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},
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.cpux_clk_state.bus_change =
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BIT(BUS_AHB1) |
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BIT(BUS_AHB2) |
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BIT(BUS_APB1) |
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BIT(BUS_APB2),
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.cpux_clk_state.bus_factor[BUS_AHB1] = {
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.src = CLK_SRC_LOSC,
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.pre_div = 0,
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.div_ratio = 0,
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},
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.cpux_clk_state.bus_factor[BUS_AHB2] = {
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.src = CLK_SRC_AHB1,
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.pre_div = 0,
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.div_ratio = 0,
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},
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.cpux_clk_state.bus_factor[BUS_APB1] = {
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.src = CLK_SRC_AHB1,
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.pre_div = 0,
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.div_ratio = 0,
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},
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.cpux_clk_state.bus_factor[BUS_APB2] = {
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.src = CLK_SRC_LOSC,
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.n = 0,
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.m = 0,
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},
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x0,
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.soc_io_state.io_state[0] = {0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_io_state.io_state[1] = {0x01c208b4, 0x000f0f00, 0x00070700},
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};
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static extended_standby_t sun50iw3_superstandby = {
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.id = 0x8,
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en = 0x0,
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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.cpux_clk_state.exit_pll_en = 0x0,
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.cpux_clk_state.pll_change = 0x0,
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.cpux_clk_state.bus_change = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x1,
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/* for pf port: set the io to disable state.; */
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.soc_io_state.io_state[0] = {0xd300b0b4, 0x00f0f0ff, 0x00707077},
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.soc_io_state.io_state[1] = {0xd300b0b4, 0x000f0f00, 0x00070700},
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};
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static extended_standby_t sun50iw3_usbstandby = {
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.id = 0x2,
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/* note: vcc_io for phy; */
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VDD_SYS_BIT) |
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BIT(VCC_IO_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en =
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BIT(OSC_LOSC_BIT) |
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BIT(OSC_HOSC_BIT) |
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BIT(OSC_LDO0_BIT) |
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BIT(OSC_LDO1_BIT),
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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/* mean PLL_DRAM is shutdowned & open by dram driver. */
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/* hsic pll can be disabled,
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* cpus can change cci400 clk from hsic_pll.
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*/
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.cpux_clk_state.exit_pll_en = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x0,
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/* for pf port: set the io to disable state.; */
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.soc_io_state.io_state[0] = {0xd300b0b4, 0x00f0f0ff, 0x00707077},
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.soc_io_state.io_state[1] = {0xd300b0b4, 0x000f0f00, 0x00070700},
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};
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static extended_standby_t sun50iw6_superstandby = {
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.id = 0x8,
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VDD_SYS_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en = 0x0,
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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.cpux_clk_state.exit_pll_en = 0x0,
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.cpux_clk_state.pll_change = 0x0,
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.cpux_clk_state.bus_change = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x1,
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/* for pf port: set the io to disable state.; */
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.soc_io_state.io_state[0] = {0x0300b074, 0x0ffff000, 0x07777000},
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.soc_io_state.io_state[1] = {0x0300b074, 0x00000000, 0x00000000},
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};
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static extended_standby_t sun50iw6_usbstandby = {
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.id = 0x2,
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/* note: vcc_io for phy; */
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VDD_SYS_BIT) |
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BIT(VCC_IO_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en =
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BIT(OSC_LOSC_BIT) |
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BIT(OSC_HOSC_BIT) |
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BIT(OSC_LDO0_BIT) |
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BIT(OSC_LDO1_BIT),
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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/* mean PLL_DRAM is shutdowned & open by dram driver. */
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/* hsic pll can be disabled,
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* cpus can change cci400 clk from hsic_pll.
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*/
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.cpux_clk_state.exit_pll_en = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x0,
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/* for pf port: set the io to disable state.; */
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.soc_io_state.io_state[0] = {0x0300b074, 0x0ffff000, 0x07777000},
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.soc_io_state.io_state[1] = {0x0300b074, 0x00000000, 0x00000000},
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};
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static extended_standby_t sun8iw15_superstandby = {
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.id = 0x8,
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en = 0x0,
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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.cpux_clk_state.exit_pll_en = 0x0,
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.cpux_clk_state.pll_change = 0x0,
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.cpux_clk_state.bus_change = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x1,
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};
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static extended_standby_t sun8iw15_usbstandby = {
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.id = 0x2,
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/* note: vcc_io for phy; */
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VDD_SYS_BIT) |
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BIT(VCC_IO_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en =
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BIT(OSC_LOSC_BIT) |
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BIT(OSC_HOSC_BIT) |
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BIT(OSC_LDO0_BIT) |
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BIT(OSC_LDO1_BIT),
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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/* mean PLL_DRAM is shutdowned & open by dram driver. */
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/* hsic pll can be disabled,
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* cpus can change cci400 clk from hsic_pll.
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*/
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.cpux_clk_state.exit_pll_en = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x0,
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};
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static extended_standby_t sun8iw17_superstandby = {
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.id = 0x8,
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en = 0x0,
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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.cpux_clk_state.exit_pll_en = 0x0,
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.cpux_clk_state.pll_change = 0x0,
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.cpux_clk_state.bus_change = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x1,
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};
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static extended_standby_t sun8iw17_usbstandby = {
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.id = (1<<0xe), //USB3_STANDBY_FLAG
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/* note: vcc_io for phy; */
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.soc_pwr_dm_state.state =
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BIT(VCC_DRAM_BIT) |
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BIT(VDD_CPUS_BIT) |
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BIT(VCC_LPDDR_BIT) |
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BIT(VCC_PL_BIT) |
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BIT(VDD_SYS_BIT) |
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BIT(VCC_IO_BIT) |
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BIT(VCC_PLL_BIT),
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.soc_pwr_dm_state.volt[0] = 0x0,
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.cpux_clk_state.osc_en =
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BIT(OSC_LOSC_BIT) |
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BIT(OSC_HOSC_BIT) |
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BIT(OSC_LDO0_BIT) |
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BIT(OSC_LDO1_BIT),
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.cpux_clk_state.init_pll_dis = BIT(PM_PLL_DRAM),
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/* mean PLL_DRAM is shutdowned & open by dram driver. */
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/* hsic pll can be disabled,
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* cpus can change cci400 clk from hsic_pll.
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*/
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.cpux_clk_state.exit_pll_en = 0x0,
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.soc_dram_state.selfresh_flag = 0x1,
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.soc_io_state.hold_flag = 0x0,
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};
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static const struct of_device_id pm_of_match[] __initconst = {
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{
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.compatible = "allwinner,sun50iw1-superstandby",
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.data = (extended_standby_t *)&sun50iw1_superstandby,
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},
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{
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.compatible = "allwinner,sun50iw1-usbstandby",
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.data = (extended_standby_t *)&sun50iw1_usbstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50iw3-superstandby",
|
|
.data = (extended_standby_t *)&sun50iw3_superstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50iw3-usbstandby",
|
|
.data = (extended_standby_t *)&sun50iw3_usbstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50iw6-superstandby",
|
|
.data = (extended_standby_t *)&sun50iw6_superstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50iw6-usbstandby",
|
|
.data = (extended_standby_t *)&sun50iw6_usbstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8iw15-superstandby",
|
|
.data = (extended_standby_t *)&sun8iw15_superstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8iw15-usbstandby",
|
|
.data = (extended_standby_t *)&sun8iw15_usbstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8iw17-superstandby",
|
|
.data = (extended_standby_t *)&sun8iw17_superstandby,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8iw17-usbstandby",
|
|
.data = (extended_standby_t *)&sun8iw17_usbstandby,
|
|
},
|
|
{},
|
|
};
|
|
|
|
static int __init sunxi_suspend_init(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *matched_np;
|
|
const extended_standby_t *extended_standby_info;
|
|
extended_standby_t *extend_standby_para;
|
|
int ret = 0;
|
|
unsigned int value[3] = { 0, 0, 0 };
|
|
|
|
pr_debug("%s\n", __func__);
|
|
|
|
np = of_find_matching_node_and_match(NULL, pm_of_match,
|
|
&matched_np);
|
|
if (IS_ERR_OR_NULL(np)) {
|
|
pr_err("get [allwinner,standby_space] device node error\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
extended_standby_info = (extended_standby_t *)matched_np->data;
|
|
|
|
ret = of_property_read_u32_array(np, "space1", value,
|
|
ARRAY_SIZE(value));
|
|
if (ret) {
|
|
pr_err("get standby_space1 err.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pr_err("%s, 0x%x, 0x%x, 0x%x\n", __FUNCTION__,
|
|
value[0], value[1], value[2]);
|
|
super_standby_para = (super_standby_t *)phys_to_virt(value[0]);
|
|
super_standby_para->pextended_standby = value[0] + 0x400;
|
|
extend_standby_para =
|
|
(extended_standby_t *)((char *)super_standby_para + 0x400);
|
|
*extend_standby_para = *extended_standby_info;
|
|
extend_standby_para->soc_pwr_dm_state.sys_mask = (1 << DM_CPUA) |
|
|
(1 << DM_DRAM) |
|
|
(1 << DM_SYS) |
|
|
(1 << DM_CPUS) |
|
|
(1 << DM_LPDDR) |
|
|
(1 << DM_PL) |
|
|
(1 << DM_PLL) |
|
|
(1 << DM_IO);
|
|
standby_space_size = value[2];
|
|
super_standby_para->event = 0;
|
|
suspend_set_ops(&sunxi_suspend_ops);
|
|
|
|
arisc_set_wakeup_source(SET_WAKEUP_TIME_MS(time_to_wakeup_ms));
|
|
|
|
return ret;
|
|
}
|
|
module_init(sunxi_suspend_init);
|
|
|
|
static void __exit sunxi_suspend_exit(void)
|
|
{
|
|
pr_debug("%s\n", __func__);
|
|
suspend_set_ops(NULL);
|
|
}
|
|
module_exit(sunxi_suspend_exit);
|