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SmartAudio/lichee/brandy/u-boot-2011.09/include/mmc.h

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/*
* Copyright 2008,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based (loosely) on the Linux code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MMC_H_
#define _MMC_H_
#include <linux/list.h>
#define SD_VERSION_SD 0x20000
#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
#define MMC_VERSION_MMC 0x10000
#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x41)
#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x42)
#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x43)
#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x44)
#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x45)
#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x50)
#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x501)
#define MMC_VERSION_NEW_VER (MMC_VERSION_MMC | 0xFFF)
#define MMC_MODE_HS 0x001
#define MMC_MODE_DDR_52MHz 0x002
#define MMC_MODE_HS_52MHz 0x010
#define MMC_MODE_4BIT 0x100
#define MMC_MODE_8BIT 0x200
#define MMC_MODE_SPI 0x400
#define MMC_MODE_HC 0x800
#define SD_DATA_4BIT 0x00040000
#define IS_SD(x) (x->version & SD_VERSION_SD)
#define MMC_DATA_READ 1
#define MMC_DATA_WRITE 2
#define MMC_CMD_MANUAL 1//add by sunxi.not sent stop when read/write multi block,and sent stop when sent cmd12
#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
#define UNUSABLE_ERR -17 /* Unusable Card */
#define COMM_ERR -18 /* Communications Error */
#define TIMEOUT -19
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RELATIVE_ADDR 3
#define MMC_CMD_SET_DSR 4
#define MMC_CMD_SWITCH 6
#define MMC_CMD_SELECT_CARD 7
#define MMC_CMD_SEND_EXT_CSD 8
#define MMC_CMD_SEND_CSD 9
#define MMC_CMD_SEND_CID 10
#define MMC_CMD_STOP_TRANSMISSION 12
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_ERASE_GROUP_START 35
#define MMC_CMD_ERASE_GROUP_END 36
#define MMC_CMD_ERASE 38
#define MMC_CMD_APP_CMD 55
#define MMC_CMD_SPI_READ_OCR 58
#define MMC_CMD_SPI_CRC_ON_OFF 59
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
#define SD_CMD_SEND_IF_COND 8
#define SD_CMD_APP_SET_BUS_WIDTH 6
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51
/* MMC erase/trim/discard/sanitize/secure erase/secure trim argument */
#define MMC_ERASE_ARG 0x00000000
#define MMC_SECURE_ERASE_ARG 0x80000000
#define MMC_TRIM_ARG 0x00000001
#define MMC_DISCARD_ARG 0x00000003
#define MMC_SECURE_TRIM1_ARG 0x80000001
#define MMC_SECURE_TRIM2_ARG 0x80008000
#define MMC_SECURE_ARGS 0x80000000
#define MMC_TRIM_ARGS 0x00008001
/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
#define MMC_HS_TIMING 0x00000100
#define MMC_HS_52MHZ 0x2
#define MMC_DDR_52MHZ 0x4
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
#define SECURE_ERASE 0x80000000
#define MMC_STATUS_MASK (~0x0206BF7F)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE (0xf << 9)
#define MMC_STATUS_ERROR (1 << 19)
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
addressed by index which are
1 in value field */
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
addressed by index, which are
1 in value field */
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
#define SD_SWITCH_CHECK 0
#define SD_SWITCH_SWITCH 1
/*
* EXT_CSD fields
*/
#define EXT_CSD_BOOT_BUS_COND 177 /* R/W */
#define EXT_CSD_PART_CONF 179 /* R/W */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_SECURE_REMOAL_TYPE 16 /* R/W */
#define EXT_CSD_FLUSH_CACHE 32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
#define EXT_CSD_HPI_MGMT 161 /* R/W */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
#define EXT_CSD_BKOPS_EN 163 /* R/W */
#define EXT_CSD_BKOPS_START 164 /* W */
#define EXT_CSD_SANITIZE_START 165 /* W */
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_BOOT_WP 173 /* R/W */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_PART_CONFIG 179 /* R/W */
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_POWER_CLASS 187 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_STRUCTURE 194 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
#define EXT_CSD_TRIM_MULT 232 /* RO */
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
#define EXT_CSD_HPI_FEATURES 503 /* RO */
/*
* EXT_CSD field definitions
*/
#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
#define EXT_CSD_CMD_SET_SECURE (1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_BUS_DDR_4 5 /* Card is in 4 bit ddr mode */
#define EXT_CSD_BUS_DDR_8 6 /* Card is in 8 bit ddr mode */
/*
* EXT_CSD[231]
*/
#define EXT_CSD_SEC_ER_EN (1U << 0)
#define EXT_CSD_SEC_BD_BLK_EN (1U << 2)
#define EXT_CSD_SEC_GB_CL_EN (1U << 4)
#define EXT_CSD_SEC_SANITIZE (1U << 6) /* v4.5 only */
#define EXT_CSD_RST_N_ENABLE (0x1)
/* MMC_SWITCH boot modes */
#define MMC_SWITCH_MMCPART_NOAVAILABLE (0xff)
#define MMC_SWITCH_PART_ACCESS_MASK (0x7)
#define MMC_SWITCH_PART_SUPPORT (0x1)
#define MMC_SWITCH_PART_BOOT_PART_MASK (0x7 << 3)
#define MMC_SWITCH_PART_BOOT_PART_NONE (0x0)
#define MMC_SWITCH_PART_BOOT_PART_1 (0x1)
#define MMC_SWITCH_PART_BOOT_PART_2 (0x2)
#define MMC_SWITCH_PART_BOOT_USER (0x7)
#define MMC_SWITCH_PART_BOOT_ACK_MASK (0x1 << 6)
#define MMC_SWITCH_PART_BOOT_ACK_ENB (0x1)
/* MMC_SWITCH boot condition */
#define MMC_SWITCH_MMCBOOT_BUS_NOAVAILABLE (0xff)
#define MMC_SWITCH_BOOT_MODE_MASK (0x3 << 3)
#define MMC_SWITCH_BOOT_SDR_NORMAL (0x0)
#define MMC_SWITCH_BOOT_SDR_HS (0x1)
#define MMC_SWITCH_BOOT_DDR (0x2)
#define MMC_SWITCH_BOOT_RST_BUS_COND_MASK (0x1 << 2)
#define MMC_SWITCH_BOOT_RST_BUS_COND (0x0)
#define MMC_SWITCH_BOOT_RETAIN_BUS_COND (0x1)
#define MMC_SWITCH_BOOT_BUS_WIDTH_MASK (0x3 << 0)
#define MMC_SWITCH_BOOT_BUS_SDRx1_DDRx4 (0x0)
#define MMC_SWITCH_BOOT_BUS_SDRx4_DDRx4 (0x1)
#define MMC_SWITCH_BOOT_BUS_SDRx8_DDRx8 (0x2)
/*MMC HOST FUNC*/
#define MMC_HOST_2XMODE_FUNC (0x1 << 0)
#define MMC_NO_FUNC (0)
/* MMC TEST */
#define MMC_ITEST_RWC (0x1 << 0)
#define MMC_ITEST_MEMCPY (0x1 << 1)
#define MMC_ITEST_SEQ_W_SPD (0x1 << 2)
#define MMC_ITEST_WHEN_BOOT (0x1 << 30)
#define MMC_ITEST_WHEN_PRODUCT (0x1 << 31)
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMCPART_NOAVAILABLE (0xff)
#define PART_ACCESS_MASK (0x7)
#define PART_SUPPORT (0x1)
#define USER_PART 0
#define BOOT1_PART 1
#define BOOT2_PART 2
struct mmc_cid {
unsigned long psn;
unsigned short oid;
unsigned char mid;
unsigned char prv;
unsigned char mdt;
char pnm[7];
};
/*
* WARNING!
*
* This structure is used by atmel_mci.c only.
* It works for the AVR32 architecture but NOT
* for ARM/AT91 architectures.
* Its use is highly depreciated.
* After the atmel_mci.c driver for AVR32 has
* been replaced this structure will be removed.
*/
struct mmc_csd
{
u8 csd_structure:2,
spec_vers:4,
rsvd1:2;
u8 taac;
u8 nsac;
u8 tran_speed;
u16 ccc:12,
read_bl_len:4;
u64 read_bl_partial:1,
write_blk_misalign:1,
read_blk_misalign:1,
dsr_imp:1,
rsvd2:2,
c_size:12,
vdd_r_curr_min:3,
vdd_r_curr_max:3,
vdd_w_curr_min:3,
vdd_w_curr_max:3,
c_size_mult:3,
sector_size:5,
erase_grp_size:5,
wp_grp_size:5,
wp_grp_enable:1,
default_ecc:2,
r2w_factor:3,
write_bl_len:4,
write_bl_partial:1,
rsvd3:5;
u8 file_format_grp:1,
copy:1,
perm_write_protect:1,
tmp_write_protect:1,
file_format:2,
ecc:2;
u8 crc:7;
u8 one:1;
};
struct mmc_ext_csd {
u8 rev;
u8 erase_group_def;
u8 sec_feature_support;
u8 rel_sectors;
u8 rel_param;
u8 part_config;
u8 cache_ctrl;
u8 rst_n_function;
u8 max_packed_writes;
u8 max_packed_reads;
u8 packed_event_en;
unsigned int part_time; /* Units: ms */
unsigned int sa_timeout; /* Units: 100ns */
unsigned int generic_cmd6_time; /* Units: 10ms */
unsigned int power_off_longtime; /* Units: ms */
u8 power_off_notification; /* state */
unsigned int hs_max_dtr;
unsigned int hs200_max_dtr;
#define MMC_HIGH_26_MAX_DTR 26000000
#define MMC_HIGH_52_MAX_DTR 52000000
#define MMC_HIGH_DDR_MAX_DTR 52000000
#define MMC_HS200_MAX_DTR 200000000
unsigned int sectors;
unsigned int hc_erase_size; /* In sectors */
unsigned int hc_erase_timeout; /* In milliseconds */
unsigned int sec_trim_mult; /* Secure trim multiplier */
unsigned int sec_erase_mult; /* Secure erase multiplier */
unsigned int trim_timeout; /* In milliseconds */
u8 enhanced_area_en; /* enable bit */
unsigned long long enhanced_area_offset; /* Units: Byte */
unsigned int enhanced_area_size; /* Units: KB */
unsigned int cache_size; /* Units: KB */
u8 hpi_en; /* HPI enablebit */
u8 hpi; /* HPI support bit */
unsigned int hpi_cmd; /* cmd used as HPI */
u8 bkops; /* background support bit */
u8 bkops_en; /* background enable bit */
unsigned int data_sector_size; /* 512 bytes or 4KB */
unsigned int data_tag_unit_size; /* DATA TAG UNIT size */
unsigned int boot_ro_lock; /* ro lock support */
u8 boot_ro_lockable;
u8 raw_exception_status; /* 54 */
u8 raw_partition_support; /* 160 */
u8 raw_rpmb_size_mult; /* 168 */
u8 raw_erased_mem_count; /* 181 */
u8 raw_ext_csd_structure; /* 194 */
u8 raw_card_type; /* 196 */
u8 out_of_int_time; /* 198 */
u8 raw_pwr_cl_52_195; /* 200 */
u8 raw_pwr_cl_26_195; /* 201 */
u8 raw_pwr_cl_52_360; /* 202 */
u8 raw_pwr_cl_26_360; /* 203 */
u8 raw_s_a_timeout; /* 217 */
u8 raw_hc_erase_gap_size; /* 221 */
u8 raw_erase_timeout_mult; /* 223 */
u8 raw_hc_erase_grp_size; /* 224 */
u8 raw_sec_trim_mult; /* 229 */
u8 raw_sec_erase_mult; /* 230 */
u8 raw_sec_feature_support;/* 231 */
u8 raw_trim_mult; /* 232 */
u8 raw_pwr_cl_200_195; /* 236 */
u8 raw_pwr_cl_200_360; /* 237 */
u8 raw_pwr_cl_ddr_52_195; /* 238 */
u8 raw_pwr_cl_ddr_52_360; /* 239 */
u8 raw_pwr_cl_ddr_200_360; /* 253 */
u8 raw_bkops_status; /* 246 */
u8 raw_sectors[4]; /* 212 - 4 bytes */
unsigned int feature_support;
#define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */
};
struct mmc_cmd {
ushort cmdidx;
uint resp_type;
uint cmdarg;
uint response[4];
uint flags;
};
struct mmc_data {
union {
char *dest;
const char *src; /* src buffers don't get written to */
};
uint flags;
uint blocks;
uint blocksize;
};
struct tuning_sdly{
//u8 sdly_400k;
u8 sdly_25M;
u8 sdly_50M;
u8 sdly_100M;
u8 sdly_200M;
};//size can not over 256 now
struct mmc_func_en{
u32 ddr_func_en :1,
rsvd:30;
};
struct mmc {
struct list_head link;
char name[32];
void *priv;
uint voltages;
uint version;
uint has_init;
uint control_num;
uint f_min;
uint f_max;
int high_capacity;
uint bus_width;
uint clock;
uint clock_after_init;
uint io_mode;
uint card_caps;
uint host_caps;
uint ocr;
uint scr[2];
uint csd[4];
uint cid[4];
ushort rca;
char part_config;
char part_num;
char part_support;
char boot_support;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
uint drv_wipe_feature;
uint drv_erase_feature;
uint drv_hwrst_feature;
uint erase_grp_size;
uint erase_timeout; /*default erasetimeout or hc_erase_timeout*/
uint trim_discard_timeout;
uint secure_erase_timeout;
uint secure_trim_timeout;
u64 capacity;
block_dev_desc_t block_dev;
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
int (*update_phase)(struct mmc *mmc);
int (*set_phase)(struct mmc *mmc, u32 tx_phase, u32 rx_phase);
/*
add these members to impliment sample point auto-adaption
*/
int (*decide_retry)(struct mmc *mmc,int err_no ,uint reset_count);
int (*update_sdly)(struct mmc *mmc,uint sdly);
int (*get_detail_errno)(struct mmc *mmc);
struct tuning_sdly sdly_tuning;
u32 sample_mode;
u32 pll_clock;
unsigned char secure_feature; // extcsd[231]
unsigned char secure_removal_type; //extcsd[16]
uint b_max;
unsigned lba; /* number of blocks */
unsigned user_lba;
unsigned boot1_lba;
unsigned boot2_lba;
unsigned blksz; /* block size */
unsigned char boot_bus_cond;
unsigned host_func;
struct mmc_func_en mmc_func_en;
unsigned mmc_test;
};
/* struct mmc/drv_wipe_feature, define for driver secure wipe opeation */
#define DRV_PARA_DISABLE_SECURE_WIPE (1U<<0) //disable all secure wipe operation
#define DRV_PARA_DISABLE_EMMC_SANITIZE (1U<<1)
#define DRV_PARA_DISABLE_EMMC_SECURE_PURGE (1U<<2)
#define DRV_PARA_DISABLE_EMMC_TRIM (1U<<3)
/*struct mmc/drv_erase_feature, define for drvier erase operation*/
#define DRV_PARA_DISABLE_EMMC_ERASE (1U<<0)
#define DRV_PARA_ENABLE_EMMC_SANITIZE_WHEN_ERASE (1U<<1)
/*struct drv_hwrst_feature, define for drvier hw reset operation*/
#define DRV_PARA_ENABLE_EMMC_HWRST (1U<<0)
int mmc_register(struct mmc *mmc);
int mmc_unregister(int sdc_no);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
int mmc_exit(void);
//int sunxi_mmc_exit(int sdc_no);
int mmc_switch_boot_bus_cond(int dev_num, u32 boot_mode, u32 rst_bus_cond, u32 bus_width);
int mmc_switch_boot_part(int dev_num, u32 boot_ack, u32 boot_part);
void print_mmc_devices(char separator);
int get_mmc_num(void);
int board_mmc_getcd(u8 *cd, struct mmc *mmc);
int mmc_switch_part(int dev_num, unsigned int part_num);
#ifdef CONFIG_GENERIC_MMC
int atmel_mci_init(void *regs);
#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
#else
int mmc_legacy_init(int verbose);
#endif
#endif /* _MMC_H_ */
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