754 lines
18 KiB
C
Executable File
754 lines
18 KiB
C
Executable File
/*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/twi.h>
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#include <sys_config.h>
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#include <asm/arch/timer.h>
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#include <asm/io.h>
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#include <asm/arch/platform.h>
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_OK 0
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#define I2C_NOK 1
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#define I2C_NACK 2
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#define I2C_NOK_LA 3 /* Lost arbitration */
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#define I2C_NOK_TOUT 4 /* time out */
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#define I2C_START_TRANSMIT 0x08
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#define I2C_RESTART_TRANSMIT 0x10
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#define I2C_ADDRWRITE_ACK 0x18
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#define I2C_ADDRREAD_ACK 0x40
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#define I2C_DATAWRITE_ACK 0x28
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#define I2C_READY 0xf8
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#define I2C_DATAREAD_NACK 0x58
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#define I2C_DATAREAD_ACK 0x50
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/* status or interrupt source */
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/*------------------------------------------------------------------------------
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* Code Status
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* 00h Bus error
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* 08h START condition transmitted
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* 10h Repeated START condition transmitted
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* 18h Address + Write bit transmitted, ACK received
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* 20h Address + Write bit transmitted, ACK not received
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* 28h Data byte transmitted in master mode, ACK received
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* 30h Data byte transmitted in master mode, ACK not received
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* 38h Arbitration lost in address or data byte
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* 40h Address + Read bit transmitted, ACK received
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* 48h Address + Read bit transmitted, ACK not received
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* 50h Data byte received in master mode, ACK transmitted
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* 58h Data byte received in master mode, not ACK transmitted
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* 60h Slave address + Write bit received, ACK transmitted
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* 68h Arbitration lost in address as master, slave address + Write bit received, ACK transmitted
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* 70h General Call address received, ACK transmitted
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* 78h Arbitration lost in address as master, General Call address received, ACK transmitted
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* 80h Data byte received after slave address received, ACK transmitted
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* 88h Data byte received after slave address received, not ACK transmitted
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* 90h Data byte received after General Call received, ACK transmitted
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* 98h Data byte received after General Call received, not ACK transmitted
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* A0h STOP or repeated START condition received in slave mode
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* A8h Slave address + Read bit received, ACK transmitted
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* B0h Arbitration lost in address as master, slave address + Read bit received, ACK transmitted
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* B8h Data byte transmitted in slave mode, ACK received
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* C0h Data byte transmitted in slave mode, ACK not received
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* C8h Last byte transmitted in slave mode, ACK received
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* D0h Second Address byte + Write bit transmitted, ACK received
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* D8h Second Address byte + Write bit transmitted, ACK not received
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* F8h No relevant status information or no interrupt
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*-----------------------------------------------------------------------------*/
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//static struct sunxi_twi_reg *i2c[SUNXI_I2C_CONTROLLER] =
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//{
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// (struct sunxi_twi_reg *)(SUNXI_TWI0_BASE),
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// (struct sunxi_twi_reg *)(SUNXI_TWI1_BASE),
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// (struct sunxi_twi_reg *)(SUNXI_TWI2_BASE)
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//};
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#ifndef CONFIG_CPUS_I2C
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static int bus_num __attribute__((section(".data")))= 0;
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static struct sunxi_twi_reg *i2c =(struct sunxi_twi_reg *)SUNXI_TWI0_BASE;
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#else
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static struct sunxi_twi_reg *i2c=(struct sunxi_twi_reg *)SUNXI_CPUS_TWI_BASE;
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#endif
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/*
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**********************************************************************************************************************
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* sw_iic_exit
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*
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* Description: ͨ<><CDA8>IIC<49><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡIIC<49>豸һ<E8B1B8><D2BB><EFBFBD>ֽڣ<D6BD><DAA3><EFBFBD>ʱֻ֧<D6BB>ֱ<EFBFBD><EFBFBD><D7BC><EFBFBD>豸
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*
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* Arguments :
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*
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* Returns : <20><>ȡ<EFBFBD>ɹ<EFBFBD><C9B9><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD> -1
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_sendstart(void)
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{
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__s32 time = 0xfffff;
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__u32 tmp_val;
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i2c->eft = 0;
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i2c->srst = 1;
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i2c->ctl |= 0x20;
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while((time--)&&(!(i2c->ctl & 0x08)));
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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tmp_val = i2c->status;
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if(tmp_val != I2C_START_TRANSMIT)
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{
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return -I2C_START_TRANSMIT;
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}
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return I2C_OK;
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}
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/*
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**********************************************************************************************************************
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* TWIC_SendReStart
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*
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* Description:
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*
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* Arguments :
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*
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* Returns :
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*
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* Notes :
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_sendRestart(void)
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{
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__s32 time = 0xffff;
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__u32 tmp_val;
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#if defined(CONFIG_ARCH_SUN7I) | defined(CONFIG_ARCH_SUN5I)
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tmp_val = i2c->ctl & 0xC0;
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#else
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tmp_val = i2c->ctl;
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#endif
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tmp_val |= 0x20;
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i2c->ctl = tmp_val;
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while( (time--) && (!(i2c->ctl & 0x08)) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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tmp_val = i2c->status;
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if(tmp_val != I2C_RESTART_TRANSMIT)
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{
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return -I2C_RESTART_TRANSMIT;
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}
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return I2C_OK;
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}
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/*
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**********************************************************************************************************************
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* TWIC_SendSlaveAddr
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*
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* Description:
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*
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* Arguments :
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*
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* Returns : EPDK_OK = successed; EPDK_FAIL = failed
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_sendslaveaddr(__u32 saddr, __u32 rw)
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{
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__s32 time = 0xffff;
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__u32 tmp_val;
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rw &= 1;
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i2c->data = ((saddr & 0xff) << 1)| rw;
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#if defined(CONFIG_ARCH_SUN5I) || defined(CONFIG_ARCH_SUN7I)
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i2c->ctl &= 0xF7; //write 0 to clean int flag
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#else
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i2c->ctl |= (0x01<<3);//write 1 to clean int flag
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#endif
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while(( time-- ) && (!( i2c->ctl & 0x08 )));
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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tmp_val = i2c->status;
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if(rw == I2C_WRITE)//+write
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{
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if(tmp_val != I2C_ADDRWRITE_ACK)
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{
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return -I2C_ADDRWRITE_ACK;
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}
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}
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else//+read
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{
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if(tmp_val != I2C_ADDRREAD_ACK)
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{
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return -I2C_ADDRREAD_ACK;
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}
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}
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return I2C_OK;
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}
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/*
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**********************************************************************************************************************
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* i2c_SendByteAddr
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*
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* Description:
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*
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* Arguments :
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*
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* Returns : EPDK_OK = successed; EPDK_FAIL = failed
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_sendbyteaddr(__u32 byteaddr)
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{
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__s32 time = 0xffff;
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__u32 tmp_val;
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i2c->data = byteaddr & 0xff;
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#if defined(CONFIG_ARCH_SUN5I)||defined(CONFIG_ARCH_SUN7I)
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i2c->ctl &= 0xF7; //write 0 to clean int flag
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#else
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i2c->ctl |= (0x01<<3);//write 1 to clean int flag
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#endif
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while( (time--) && (!(i2c->ctl & 0x08)) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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tmp_val = i2c->status;
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if(tmp_val != I2C_DATAWRITE_ACK)
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{
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return -I2C_DATAWRITE_ACK;
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}
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return I2C_OK;
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}
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/*
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**********************************************************************************************************************
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* TWIC_GetData
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*
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* Description:
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*
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* Arguments :
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*
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* Returns : EPDK_OK = successed; EPDK_FAIL = failed
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_getdata(__u8 *data_addr, __u32 data_count)
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{
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__s32 time = 0xffff;
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__u32 tmp_val;
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__u32 i;
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if(data_count == 1)
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{
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#if defined(CONFIG_ARCH_SUN5I)||defined(CONFIG_ARCH_SUN7I)
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i2c->ctl &= 0xF7;
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#else
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i2c->ctl |= (0x01<<3);
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#endif
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while( (time--) && (!(i2c->ctl & 0x08)) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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for(time=0;time<100;time++);
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*data_addr = i2c->data;
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tmp_val = i2c->status;
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if(tmp_val != I2C_DATAREAD_NACK)
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{
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return -I2C_DATAREAD_NACK;
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}
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}
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else
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{
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for(i=0; i< data_count - 1; i++)
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{
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time = 0xffff;
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tmp_val = i2c->ctl | (0x01<<2);//<2F><><EFBFBD>Ͷ<EFBFBD><CDB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ÿ<EFBFBD>δ<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>һ<EFBFBD><D2BB>ack
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#if defined(CONFIG_ARCH_SUN5I)||defined(CONFIG_ARCH_SUN7I)
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tmp_val = i2c->ctl & (0xf7);
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#else
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tmp_val = i2c->ctl | (0x01<<3);
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#endif
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tmp_val |= 0x04;
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i2c->ctl = tmp_val;
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//i2c->ctl |=(0x01<<3);
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while( (time--) && (!(i2c->ctl & 0x08)) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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for(time=0;time<100;time++);
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time = 0xffff;
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data_addr[i] = i2c->data;
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while( (time--) && (i2c->status != I2C_DATAREAD_ACK) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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}
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time = 0xffff;
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i2c->ctl &= 0xFb; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>ʱ<EFBFBD>ͽ<F2A3ACBE><CDBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD>㣬<EFBFBD><E3A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӻ<EFBFBD>ack<63><6B>Ĭ<EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#if defined(CONFIG_ARCH_SUN5I)||defined(CONFIG_ARCH_SUN7I)
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i2c->ctl &= 0xf7;
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#else
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i2c->ctl |= (0x01<<3);
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#endif
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while( (time--) && (!(i2c->ctl & 0x08)) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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for(time=0;time<100;time++);
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data_addr[data_count - 1] = i2c->data;
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while( (time--) && (i2c->status != I2C_DATAREAD_NACK) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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}
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return I2C_OK;
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}
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/*
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**********************************************************************************************************************
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* i2c_SendData
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*
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* Description:
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*
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* Arguments :
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*
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* Returns : EPDK_OK = successed; EPDK_FAIL = failed
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_senddata(__u8 *data_addr, __u32 data_count)
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{
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__s32 time = 0xffff;
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__u32 i;
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for(i=0; i< data_count; i++)
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{
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time = 0xffff;
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i2c->data = data_addr[i];
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#if defined(CONFIG_ARCH_SUN5I)|defined(CONFIG_ARCH_SUN7I)
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i2c->ctl &= 0xF7;
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#else
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i2c->ctl |= (0x01<<3);
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#endif
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while( (time--) && (!(i2c->ctl & 0x08)) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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time = 0xffff;
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while( (time--) && (i2c->status != I2C_DATAWRITE_ACK) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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}
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return I2C_OK;
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}
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/*
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**********************************************************************************************************************
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* i2c_Stop
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*
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* Description:
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*
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* Arguments :
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*
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* Returns : EPDK_OK = successed; EPDK_FAIL = failed
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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static __s32 i2c_stop(void)
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{
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__s32 time = 0xffff;
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__u32 tmp_val;
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// tmp_val = (i2c->ctl & 0xC0) | 0x10;
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// i2c->ctl = tmp_val;
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i2c->ctl |= (0x01 << 4);
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#if defined(CONFIG_ARCH_SUN5I)|defined(CONFIG_ARCH_SUN7I)
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i2c->ctl &= 0xf7;
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#else
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i2c->ctl |= (0x01 << 3);
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#endif
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while( (time--) && (i2c->ctl & 0x10) );
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if(time <= 0)
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{
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return -I2C_NOK_TOUT;
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}
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time = 0xffff;
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while( (time--) && (i2c->status != I2C_READY) );
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tmp_val = i2c->status;
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if(tmp_val != I2C_READY)
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{
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return -I2C_NOK_TOUT;
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}
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return I2C_OK;
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}
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#ifndef CONFIG_CPUS_I2C
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void set_i2c_clock(void)
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{
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struct sunxi_ccm_reg *ccm_reg = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int reg_value = 0;
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#if !defined(CONFIG_ARCH_SUN5I)||!defined(CONFIG_ARCH_SUN7I)
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/* reset i2c clock */
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/* reset apb2 twi0*/
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reg_value = readl(SUNXI_CCM_BASE + 0x2d8);
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reg_value |= 0x01 << bus_num;
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writel(reg_value, SUNXI_CCM_BASE + 0x2d8);
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__msdelay(1);
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#endif
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ccm_reg->apb1_gate &= ~(1<<bus_num);
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__msdelay(1);
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ccm_reg->apb1_gate |= 1 << bus_num;
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}
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#else
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void set_cpus_i2c_clock(void)
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{
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int reg_value = 0;
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reg_value = readl(R_PRCE_APB0_RESET);
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reg_value |= 0x01 << 6;
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writel(reg_value,R_PRCE_APB0_RESET);
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__msdelay(1);
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reg_value = readl(R_PRCM_APB0_GATING);
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reg_value |= 0x01 << 6;
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writel(reg_value,R_PRCM_APB0_GATING);
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__msdelay(1);
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}
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#endif
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/*
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**********************************************************************************************************************
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* i2c_init
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*
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* Description:
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*
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* Arguments :
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*
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* Returns : none
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*
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* Notes : none
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*
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**********************************************************************************************************************
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*/
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void i2c_init(int speed, int slaveaddr)
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{
|
||
int i, clk_n, clk_m;
|
||
|
||
/*set gpio and clock*/
|
||
#ifndef CONFIG_CPUS_I2C
|
||
if(script_parser_fetch("twi_para","twi_port",&bus_num,1))
|
||
{
|
||
printf("can not get i2c bus num \n");
|
||
return ;
|
||
}
|
||
if(bus_num > SUNXI_I2C_CONTROLLER)
|
||
{
|
||
printf("can not support i2c bus num %d \n",bus_num);
|
||
return ;
|
||
}
|
||
set_i2c_clock();
|
||
gpio_request_simple("twi_para",NULL);
|
||
i2c = (struct sunxi_twi_reg *)(SUNXI_TWI0_BASE + (bus_num * TWI_CONTROL_OFFSET));
|
||
#else
|
||
set_cpus_i2c_clock();
|
||
#ifdef CONFIG_ARCH_SUN8IW7P1
|
||
gpio_request_simple("s_rsb0",NULL);
|
||
#else
|
||
gpio_request_simple("s_twi0",NULL);
|
||
#endif
|
||
#endif
|
||
/* reset i2c control */
|
||
i = 0xffff;
|
||
i2c->srst = 1;
|
||
while((i2c->srst) && (i))
|
||
{
|
||
i --;
|
||
}
|
||
if((i2c->lcr & 0x30) != 0x30 )
|
||
{
|
||
/* toggle I2CSCL until bus idle */
|
||
i2c->lcr = 0x05;
|
||
__usdelay(500);
|
||
i = 10;
|
||
while ((i > 0) && ((i2c->lcr & 0x02) != 2))
|
||
{
|
||
i2c->lcr |= 0x08;
|
||
__usdelay(1000);
|
||
i2c->lcr &= ~0x08;
|
||
__usdelay(1000);
|
||
i--;
|
||
}
|
||
i2c->lcr = 0x0;
|
||
__usdelay(500);
|
||
}
|
||
|
||
if(speed < 100)
|
||
{
|
||
speed = 100;
|
||
}
|
||
else if(speed > 400)
|
||
{
|
||
speed = 400;
|
||
}
|
||
clk_n = 1;
|
||
clk_m = (24000/10)/((2^clk_n) * speed) - 1;
|
||
|
||
i2c->clk = (clk_m<<3) | clk_n;
|
||
i2c->ctl = 0x40;
|
||
i2c->eft = 0;
|
||
return ;
|
||
}
|
||
/*
|
||
**********************************************************************************************************************
|
||
* i2c_init
|
||
*
|
||
* Description:
|
||
*
|
||
* Arguments :
|
||
*
|
||
* Returns : none
|
||
*
|
||
* Notes : none
|
||
*
|
||
**********************************************************************************************************************
|
||
*/
|
||
void i2c_exit(void)
|
||
{
|
||
#ifndef CONFIG_CPUS_I2C
|
||
struct sunxi_ccm_reg *ccm_reg = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||
/* close i2c clock */
|
||
ccm_reg->apb1_gate &= ~1;
|
||
#else
|
||
|
||
int reg_value = 0;
|
||
reg_value = *((unsigned int *)(R_PRCE_APB0_RESET));
|
||
reg_value &= ~(0x01 << 6);
|
||
*((unsigned int *)(R_PRCE_APB0_RESET)) = reg_value;
|
||
__msdelay(1);
|
||
reg_value = *((unsigned int *)(R_PRCM_APB0_GATING));
|
||
reg_value &= ~(0x01 << 6);
|
||
*((unsigned int *)(R_PRCM_APB0_GATING)) = reg_value;
|
||
__msdelay(1);
|
||
|
||
#endif
|
||
|
||
return ;
|
||
}/*
|
||
****************************************************************************************************
|
||
*
|
||
* i2c_read
|
||
*
|
||
* Description:
|
||
*
|
||
*
|
||
* Parameters:
|
||
*
|
||
* Return value:
|
||
*
|
||
* Read/Write interface:
|
||
* chip: I2C slave chip address, range 0..127
|
||
* addr: Memory (register) address within the chip
|
||
* alen: Number of bytes to use for addr (
|
||
* 0, 1: addr len = 8bit
|
||
* 2: addr len = 16bit
|
||
* 3, 4: addr len = 32bit
|
||
*
|
||
* buffer: Where to read/write the data
|
||
* len: How many bytes to read/write
|
||
*
|
||
* Returns: 0 on success, not 0 on failure
|
||
*
|
||
****************************************************************************************************
|
||
*/
|
||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||
{
|
||
int i, ret, ret0, addrlen;
|
||
char *slave_reg;
|
||
|
||
ret0 = -1;
|
||
ret = i2c_sendstart();
|
||
if(ret)
|
||
{
|
||
goto i2c_read_err_occur;
|
||
}
|
||
|
||
ret = i2c_sendslaveaddr(chip, I2C_WRITE);
|
||
if(ret)
|
||
{
|
||
goto i2c_read_err_occur;
|
||
}
|
||
//send byte address
|
||
if(alen >= 3)
|
||
{
|
||
addrlen = 2;
|
||
}
|
||
else if(alen <= 1)
|
||
{
|
||
addrlen = 0;
|
||
}
|
||
else
|
||
{
|
||
addrlen = 1;
|
||
}
|
||
slave_reg = (char *)&addr;
|
||
for (i = addrlen; i>=0; i--)
|
||
{
|
||
ret = i2c_sendbyteaddr(slave_reg[i] & 0xff);
|
||
if(ret)
|
||
{
|
||
goto i2c_read_err_occur;
|
||
}
|
||
}
|
||
ret = i2c_sendRestart();
|
||
if(ret)
|
||
{
|
||
goto i2c_read_err_occur;
|
||
}
|
||
ret = i2c_sendslaveaddr(chip, I2C_READ);
|
||
if(ret)
|
||
{
|
||
goto i2c_read_err_occur;
|
||
}
|
||
//get data
|
||
ret = i2c_getdata(buffer, len);
|
||
if(ret)
|
||
{
|
||
goto i2c_read_err_occur;
|
||
}
|
||
ret0 = 0;
|
||
|
||
i2c_read_err_occur:
|
||
i2c_stop();
|
||
|
||
return ret0;
|
||
}
|
||
/*
|
||
****************************************************************************************************
|
||
*
|
||
* TWIC_Write
|
||
*
|
||
* Description:
|
||
* DRV_MOpen
|
||
*
|
||
* Parameters:
|
||
*
|
||
* Return value:
|
||
* EPDK_OK
|
||
* EPDK_FAIL
|
||
****************************************************************************************************
|
||
*/
|
||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||
{
|
||
int i, ret, ret0, addrlen;
|
||
char *slave_reg;
|
||
|
||
ret0 = -1;
|
||
ret = i2c_sendstart();
|
||
if(ret)
|
||
{
|
||
goto i2c_write_err_occur;
|
||
}
|
||
|
||
ret = i2c_sendslaveaddr(chip, I2C_WRITE);
|
||
if(ret)
|
||
{
|
||
goto i2c_write_err_occur;
|
||
}
|
||
//send byte address
|
||
if(alen >= 3)
|
||
{
|
||
addrlen = 2;
|
||
}
|
||
else if(alen <= 1)
|
||
{
|
||
addrlen = 0;
|
||
}
|
||
else
|
||
{
|
||
addrlen = 1;
|
||
}
|
||
slave_reg = (char *)&addr;
|
||
for (i = addrlen; i>=0; i--)
|
||
{
|
||
ret = i2c_sendbyteaddr(slave_reg[i] & 0xff);
|
||
if(ret)
|
||
{
|
||
goto i2c_write_err_occur;
|
||
}
|
||
}
|
||
|
||
ret = i2c_senddata(buffer, len);
|
||
if(ret)
|
||
{
|
||
goto i2c_write_err_occur;
|
||
}
|
||
ret0 = 0;
|
||
|
||
i2c_write_err_occur:
|
||
i2c_stop();
|
||
|
||
return ret0;
|
||
}
|
||
|