639 lines
16 KiB
C
Executable File
639 lines
16 KiB
C
Executable File
/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dma_i.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/intc.h>
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#define SUNXI_DMA_MAX (CFG_SW_DMA_NORMAL_MAX + CFG_SW_DMA_DEDICATE_MAX)
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#define SUNXI_DMA_CHANANL_SIZE (0x20)
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#define DMA_PKG_HALF_INT (1<<0)
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#define DMA_PKG_END_INT (1<<1)
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#define DMA_QUEUE_END_INT (1<<2)
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typedef struct
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{
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unsigned int irq_en;
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unsigned int irq_pend;
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unsigned int status;
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}
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sunxi_dma_int_set;
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typedef struct sunxi_dma_channal_set_t
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{
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volatile unsigned int enable;
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volatile unsigned int pause;
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volatile unsigned int start_addr; //起始地址
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volatile unsigned int config;
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volatile unsigned int cur_src_addr; //当前传输地址
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volatile unsigned int cur_dst_addr;
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volatile unsigned int left_bytes; //剩余未传字节数
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volatile unsigned int parameters; //参数
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}
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sunxi_dma_channal_set;
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typedef struct sunxi_dma_source_t
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{
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unsigned int used;
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unsigned int channal_count;
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sunxi_dma_channal_set *channal;
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unsigned int reserved;
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volatile sunxi_dma_start_t config;
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struct dma_irq_handler dma_func;
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}
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sunxi_dma_source;
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static int dma_int_count = 0;
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sw_dma_channal_set_t dma_channal[CFG_SW_DMA_NORMAL_MAX + CFG_SW_DMA_DEDICATE_MAX] =
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{
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL0 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL1 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL2 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL3 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL4 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL5 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL6 , 0 },
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{0, -1, (sw_dma_t)CFS_SW_DMA_NORMAL7 , 0 },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE0, (sw_dma_other_t)CFG_SW_DMA_DEDICATE0_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE1, (sw_dma_other_t)CFG_SW_DMA_DEDICATE1_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE2, (sw_dma_other_t)CFG_SW_DMA_DEDICATE2_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE3, (sw_dma_other_t)CFG_SW_DMA_DEDICATE3_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE4, (sw_dma_other_t)CFG_SW_DMA_DEDICATE4_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE5, (sw_dma_other_t)CFG_SW_DMA_DEDICATE5_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE6, (sw_dma_other_t)CFG_SW_DMA_DEDICATE6_OTHER },
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{0, -1, (sw_dma_t)CFG_SW_DMA_DEDICATE7, (sw_dma_other_t)CFG_SW_DMA_DEDICATE7_OTHER }
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};
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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static void sunxi_dma_int_func(void *p)
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{
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int i;
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uint pending;
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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for(i=0; i<SUNXI_DMA_MAX; i++)
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{
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if(dma_channal[i].dma_func.m_func)
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{
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pending = (DMA_PKG_END_INT << (i * 2));
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if(dma_int->irq_pend & pending)
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{
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dma_int->irq_pend = pending;
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dma_channal[i].dma_func.m_func(dma_channal[i].dma_func.m_data);
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}
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}
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}
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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void sunxi_dma_init(void)
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{
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int i;
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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dma_int->irq_en = 0;
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dma_int->irq_pend = 0xffffffff;
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for(i=0;i<SUNXI_DMA_MAX;i++){
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memset((void*)(&dma_channal[i].dma_func), 0, sizeof(struct dma_irq_handler));
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}
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dma_int_count = 0;
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irq_install_handler(AW_IRQ_DMA, sunxi_dma_int_func, 0);
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return ;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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void sunxi_dma_exit(void)
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{
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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dma_int->irq_en = 0;
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dma_int->irq_pend = 0xffffffff;
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irq_free_handler(AW_IRQ_DMA);
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}
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/*
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****************************************************************************************************
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*
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* DMAC_RequestDma
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*
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* Description:
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* request dma
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*
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* Parameters:
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* type 0: normal timer
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* 1: special timer
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* Return value:
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* dma handler
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* if 0, fail
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****************************************************************************************************
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*/
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uint sunxi_dma_request(uint dmatype)
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{
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uint i;
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if(dmatype == DMAC_DMATYPE_NORMAL)
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{
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for(i=0;i<CFG_SW_DMA_NORMAL_MAX;i++)
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{
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if(!dma_channal[i].used)
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{
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dma_channal[i].used = 1;
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dma_channal[i].channalNo = i;
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return (uint)&dma_channal[i];
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}
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}
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}
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else if(dmatype == DMAC_DMATYPE_DEDICATED)
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{
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for(i=CFG_SW_DMA_NORMAL_MAX;i<CFG_SW_DMA_NORMAL_MAX + CFG_SW_DMA_DEDICATE_MAX;i++)
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{
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if(!dma_channal[i].used)
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{
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dma_channal[i].used = 1;
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dma_channal[i].channalNo = i;
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return (uint)&dma_channal[i];
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}
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}
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}
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return 0;
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}
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/*
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****************************************************************************************************
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*
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* DMAC_ReleaseDma
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*
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* Description:
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* release dma
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*
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* Parameters:
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* hDma dma handler
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*
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* Return value:
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* EPDK_OK/FAIL
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****************************************************************************************************
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*/
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int sunxi_dma_release(uint hDma)
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{
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sw_dma_channal_set_t *dma_channal = (sw_dma_channal_set_t *)hDma;
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sunxi_dma_disable_int(hDma);
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sunxi_dma_free_int(hDma);
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/* stop dma */
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dma_channal->channal->config &= 0x7fffffff; /* stop dma */
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/* free dma handle */
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dma_channal->used = 0;
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dma_channal->channalNo = -1;
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return 0;
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}
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/*
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****************************************************************************************************
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*
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* TMRC_SettingDMA
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*
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* Description:
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* start interrupt
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*
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* Parameters:
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* hTmr timer handler
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* pArg *(pArg + 0) ctrl
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* *(pArg + 1) page size
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* *(pArg + 2) page step
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* *(pArg + 3) comity & block count
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*
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* Return value:
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* EPDK_OK/FAIL
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_setting(uint hDMA, sunxi_dma_setting_t *cfg)
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{
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sw_dma_channal_set_t * pDma = (sw_dma_channal_set_t *)hDMA;
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sunxi_dma_setting_t * arg = (sunxi_dma_setting_t *)cfg;
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uint value;
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uint *tmp = NULL;
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if(pDma->other)
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{
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__ddma_config_t ddma_arg = {0};
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tmp = (uint *)&ddma_arg;
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ddma_arg.src_drq_type = arg->cfg.src_drq_type;
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ddma_arg.src_addr_type = arg->cfg.src_addr_type;
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ddma_arg.src_burst_length = arg->cfg.src_burst_length;
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ddma_arg.src_data_width = arg->cfg.src_data_width;
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ddma_arg.dst_drq_type = arg->cfg.dst_drq_type;
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ddma_arg.dst_addr_type = arg->cfg.dst_addr_type;
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ddma_arg.dst_burst_length = arg->cfg.dst_burst_length;
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ddma_arg.dst_data_width = arg->cfg.dst_data_width;
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ddma_arg.continuous_mode = arg->cfg.continuous_mode;
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value = *tmp;
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pDma->channal->config = value & (~0x80000000);
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pDma->other->src_wait_cyc = arg->wait_cyc;
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pDma->other->src_data_block_size = arg->data_block_size;
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pDma->other->dst_wait_cyc = arg->wait_cyc;
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pDma->other->dst_data_block_size = arg->data_block_size;
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}
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else
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{
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__ndma_config_t ndma_arg = {0};
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tmp = (uint *)&ndma_arg;
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ndma_arg.src_drq_type = arg->cfg.src_drq_type;
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ndma_arg.src_addr_type = arg->cfg.src_addr_type;
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ndma_arg.src_burst_length = arg->cfg.src_burst_length;
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ndma_arg.src_data_width = arg->cfg.src_data_width;
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ndma_arg.dst_drq_type = arg->cfg.dst_drq_type;
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ndma_arg.dst_addr_type = arg->cfg.dst_addr_type;
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ndma_arg.dst_burst_length = arg->cfg.dst_burst_length;
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ndma_arg.dst_data_width = arg->cfg.dst_data_width;
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ndma_arg.continuous_mode = arg->cfg.continuous_mode;
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ndma_arg.wait_state = arg->cfg.wait_state;
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value = *tmp;
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pDma->channal->config = value & (~0x80000000);
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}
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* TMRC_StartTmr
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*
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* Description:
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* start interrupt
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*
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* Parameters:
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* hTmr timer handler
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*
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* Return value:
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* EPDK_OK/FAIL
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*
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****************************************************************************************************
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*/
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int sunxi_dma_start(uint hDMA, uint saddr, uint daddr, uint bytes)
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{
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sw_dma_channal_set_t * pDma = (sw_dma_channal_set_t *)hDMA;
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pDma->channal->src_addr = saddr;
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pDma->channal->dst_addr = daddr;
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pDma->channal->bytes = bytes;
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pDma->channal->config |= 0x80000000; /* start dma */
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* DMAC_StopDma
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*
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* Description:
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* stop dma
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*
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* Parameters:
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* hDma dma handler
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*
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* Return value:
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* EPDK_OK/FAIL
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_stop(uint hDma)
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{
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sw_dma_channal_set_t * pDma = (sw_dma_channal_set_t *)hDma;
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pDma->channal->config &= 0x7fffffff; /* stop dma */
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* eGon2_RestartDMA
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*
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* Description:
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* restart dma
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*
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* Parameters:
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* hDma dma handler
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*
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* Return value:
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* EPDK_OK/FAIL
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_restart(uint hDma)
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{
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sw_dma_channal_set_t * pDma = (sw_dma_channal_set_t *)hDma;
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pDma->channal->config |= 0x80000000;
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* eGon2_QueryDMAStatus
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*
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* Description:
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*
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*
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* Parameters:
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* hDma dma handler
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*
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* Return value:
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* EPDK_OK/FAIL
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_querystatus(uint hDma)
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{
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sw_dma_channal_set_t * pDma = (sw_dma_channal_set_t *)hDma;
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return (pDma->channal->config >> 31) & 0x01;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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int sunxi_dma_install_int(uint hdma, interrupt_handler_t dma_int_func, void *p)
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{
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sw_dma_channal_set_t *dma_channal = (sw_dma_channal_set_t *)hdma;
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sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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uint channal_count;
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if(!dma_channal->used)
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{
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return -1;
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}
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channal_count = dma_channal->channalNo;
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//clear half pending and end pending.
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dma_status->irq_pend = (0x3 << (channal_count*2));
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if(!dma_channal->dma_func.m_func)
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{
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dma_channal->dma_func.m_func = dma_int_func;
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dma_channal->dma_func.m_data = p;
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}
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else
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{
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printf("dma 0x%x int is used already, you have to free it first\n", hdma);
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return -1;
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}
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return 0;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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int sunxi_dma_enable_int(uint hdma)
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{
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sw_dma_channal_set_t *dma_channal = (sw_dma_channal_set_t *)hdma;
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sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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uint channal_count;
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if(!dma_channal->used)
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{
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return -1;
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}
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channal_count = dma_channal->channalNo;
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//enable the ending irq.
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dma_status->irq_en = (0x2 << (channal_count*2));
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if(!dma_int_count)
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{
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irq_enable(AW_IRQ_DMA);
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}
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dma_int_count ++;
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return 0;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
|
|
* parmeters :
|
|
*
|
|
* return :
|
|
*
|
|
* note :
|
|
*
|
|
*
|
|
************************************************************************************************************
|
|
*/
|
|
int sunxi_dma_disable_int(uint hdma)
|
|
{
|
|
sw_dma_channal_set_t *dma_channal = (sw_dma_channal_set_t *)hdma;
|
|
sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
|
|
uint channal_count;
|
|
|
|
if(!dma_channal->used)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
channal_count = dma_channal->channalNo;
|
|
dma_status->irq_en &= ~(0x2 << (channal_count*2));
|
|
//disable golbal int
|
|
if(dma_int_count > 0)
|
|
{
|
|
dma_int_count --;
|
|
}
|
|
if(!dma_int_count)
|
|
{
|
|
irq_disable(AW_IRQ_DMA);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
************************************************************************************************************
|
|
*
|
|
* function
|
|
*
|
|
* name :
|
|
*
|
|
* parmeters :
|
|
*
|
|
* return :
|
|
*
|
|
* note :
|
|
*
|
|
*
|
|
************************************************************************************************************
|
|
*/
|
|
int sunxi_dma_free_int(uint hdma)
|
|
{
|
|
sw_dma_channal_set_t *dma_channal = (sw_dma_channal_set_t *)hdma;
|
|
sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
|
|
uint channal_count;
|
|
|
|
if(!dma_channal->used)
|
|
{
|
|
return -1;
|
|
}
|
|
channal_count = dma_channal->channalNo;
|
|
|
|
//enable the ending irq.
|
|
dma_status->irq_pend= (0x3 << (channal_count*2));
|
|
if(dma_channal->dma_func.m_func)
|
|
{
|
|
dma_channal->dma_func.m_func = NULL;
|
|
dma_channal->dma_func.m_data = NULL;
|
|
}
|
|
else
|
|
{
|
|
printf("dma 0x%x int is free, you do not need to free it again\n", hdma);
|
|
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
**********************************************************************************************************************
|
|
*
|
|
* eGon2_QueryDMAChannalNo
|
|
*
|
|
* Description:
|
|
*
|
|
*
|
|
* Parameters:
|
|
* hDma dma handler
|
|
*
|
|
* Return value:
|
|
* dma channael no.
|
|
*
|
|
**********************************************************************************************************************
|
|
*/
|
|
int sunxi_dma_querychannalno(uint hDma)
|
|
{
|
|
sw_dma_channal_set_t * pDma = (sw_dma_channal_set_t *)hDma;
|
|
|
|
return pDma->channalNo;
|
|
}
|
|
|
|
|
|
|
|
|