545 lines
15 KiB
C
545 lines
15 KiB
C
/*
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* SUNXI EMMC/SD driver
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*
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* Copyright (C) 2015 AllWinnertech Ltd.
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* Author: lijuan <lijuan@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk/sunxi.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/slot-gpio.h>
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#include "sunxi-mmc.h"
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#include "sunxi-mmc-v4p10x.h"
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#include "sunxi-mmc-export.h"
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#include "sunxi-mmc-debug.h"
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#define MMC_2MOD_CLK "sdmmc2mod"
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#define MMC_SRCCLK_PLL "pll_periph"
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#define MMC_SRCCLK_HOSC "hosc"
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#define SUNXI_RETRY_CNT_PER_PHA_V4P1X 3
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/*dma triger level setting*/
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#define SUNXI_DMA_TL_SDMMC_V4P1X ((0x2<<28)|(7<<16)|16)
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/*one dma des can transfer data size = 1<<SUNXI_DES_SIZE_SDMMC*/
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#define SUNXI_DES_SIZE_SDMMC_V4P1X (15)
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/*reg*/
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#define SDXC_REG_SD_NTSR (0x005C)
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/*bit*/
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#define SDXC_2X_TIMING_MODE (1U<<31)
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/*mask*/
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#define SDXC_TX_TL_MASK (0x1f)
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#define SDXC_RX_TL_MASK (0x001F0000)
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#define SDXC_STIMING_PH_MASK (0x00000030)
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#define SDXC_DRV_PH_MASK (0x00000003)
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/*shift*/
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#define SDXC_STIMING_PH_SHIFT (4)
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#define SDXC_DRV_PH_SHIFT (0)
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enum sunxi_mmc_clk_mode {
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mmc_clk_400k = 0,
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mmc_clk_26M,
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mmc_clk_52M,
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mmc_clk_52M_DDR4,
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mmc_clk_52M_DDR8,
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mmc_clk_104M,
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mmc_clk_208M,
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mmc_clk_104M_DDR,
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mmc_clk_208M_DDR,
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mmc_clk_mod_num,
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};
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struct sunxi_mmc_clk_dly {
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enum sunxi_mmc_clk_mode cmod;
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char *mod_str;
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u32 drv_ph;
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u32 sam_ph;
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};
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/*sample delay and output deley setting */
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struct sunxi_mmc_spec_regs {
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u32 sd_ntsr; /*REG_SD_NTSR*/
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};
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struct sunxi_mmc_ver_priv {
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struct sunxi_mmc_spec_regs bak_spec_regs;
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struct sunxi_mmc_clk_dly mmc_clk_dly[mmc_clk_mod_num];
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};
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static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *host, int clk,
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int bus_width, int timing)
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{
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struct mmc_host *mhost = host->mmc;
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u32 rval = 0;
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enum sunxi_mmc_clk_mode cmod = mmc_clk_400k;
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u32 in_clk_dly[5] = { 0 };
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int ret = 0;
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struct device_node *np = NULL;
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struct sunxi_mmc_clk_dly *mmc_clk_dly =
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((struct sunxi_mmc_ver_priv *)host->version_priv_dat)->mmc_clk_dly;
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if (!mhost->parent || !mhost->parent->of_node) {
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dev_err(mmc_dev(host->mmc),
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"no dts to parse clk dly,use default\n");
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return;
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}
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np = mhost->parent->of_node;
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if (clk <= 400 * 1000) {
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cmod = mmc_clk_400k;
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} else if (clk <= 26 * 1000 * 1000) {
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cmod = mmc_clk_26M;
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} else if (clk <= 52 * 1000 * 1000) {
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if ((bus_width == MMC_BUS_WIDTH_4)
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&& sunxi_mmc_ddr_timing(timing)) {
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cmod = mmc_clk_52M_DDR4;
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} else if ((bus_width == MMC_BUS_WIDTH_8)
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&& (timing == MMC_TIMING_MMC_DDR52)) {
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cmod = mmc_clk_52M_DDR8;
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} else {
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cmod = mmc_clk_52M;
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}
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} else if (clk <= 104 * 1000 * 1000) {
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if ((bus_width == MMC_BUS_WIDTH_8)
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&& (timing == MMC_TIMING_MMC_HS400)) {
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cmod = mmc_clk_104M_DDR;
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} else {
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cmod = mmc_clk_104M;
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}
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} else if (clk <= 208 * 1000 * 1000) {
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if ((bus_width == MMC_BUS_WIDTH_8)
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&& (timing == MMC_TIMING_MMC_HS400)) {
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cmod = mmc_clk_208M_DDR;
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} else {
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cmod = mmc_clk_208M;
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}
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} else {
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dev_err(mmc_dev(mhost), "clk %d is out of range\n", clk);
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return;
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}
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ret = of_property_read_u32_array(np, mmc_clk_dly[cmod].mod_str,
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in_clk_dly, ARRAY_SIZE(in_clk_dly));
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if (ret) {
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dev_dbg(mmc_dev(host->mmc), "failed to get %s used default\n",
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mmc_clk_dly[cmod].mod_str);
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} else {
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mmc_clk_dly[cmod].drv_ph = in_clk_dly[0];
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/*mmc_clk_dly[cmod].sam_dly = in_clk_dly[2];*/
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/*mmc_clk_dly[cmod].ds_dly = in_clk_dly[3];*/
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mmc_clk_dly[cmod].sam_ph = in_clk_dly[3];
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dev_dbg(mmc_dev(host->mmc), "Get %s clk dly ok\n",
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mmc_clk_dly[cmod].mod_str);
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}
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dev_dbg(mmc_dev(host->mmc), "Try set %s clk dly ok\n",
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mmc_clk_dly[cmod].mod_str);
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dev_dbg(mmc_dev(host->mmc), "drv_ph %d\n",
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mmc_clk_dly[cmod].drv_ph);
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dev_dbg(mmc_dev(host->mmc), "sam_ph %d\n",
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mmc_clk_dly[cmod].sam_ph);
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/*
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* rval = mmc_readl(host,REG_SAMP_DL);
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* rval &= ~SDXC_SAMP_DL_SW_MASK;
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* rval |= mmc_clk_dly[cmod].sam_dly & SDXC_SAMP_DL_SW_MASK;
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* rval |= SDXC_SAMP_DL_SW_EN;
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* mmc_writel(host,REG_SAMP_DL,rval);
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* rval = mmc_readl(host,REG_DS_DL);
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* rval &= ~SDXC_DS_DL_SW_MASK;
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* rval |= mmc_clk_dly[cmod].ds_dly & SDXC_DS_DL_SW_MASK;
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* rval |= SDXC_DS_DL_SW_EN;
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* mmc_writel(host,REG_DS_DL,rval);
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*/
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rval = mmc_readl(host, REG_SD_NTSR);
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rval &= ~SDXC_DRV_PH_MASK;
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rval |=
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(mmc_clk_dly[cmod].
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drv_ph << SDXC_DRV_PH_SHIFT) & SDXC_DRV_PH_MASK;
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mmc_writel(host, REG_SD_NTSR, rval);
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rval = mmc_readl(host, REG_SD_NTSR);
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rval &= ~SDXC_STIMING_PH_MASK;
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rval |=
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(mmc_clk_dly[cmod].
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sam_ph << SDXC_STIMING_PH_SHIFT) & SDXC_STIMING_PH_MASK;
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mmc_writel(host, REG_SD_NTSR, rval);
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dev_dbg(mmc_dev(host->mmc), "REG_SD_NTSR %08x\n",
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mmc_readl(host, REG_SD_NTSR));
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}
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static int __sunxi_mmc_do_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en,
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u32 pwr_save, u32 ignore_dat0)
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{
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unsigned long expire = jiffies + msecs_to_jiffies(250);
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u32 rval;
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
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if (oclk_en)
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rval |= SDXC_CARD_CLOCK_ON;
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if (pwr_save)
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rval |= SDXC_LOW_POWER_ON;
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if (ignore_dat0)
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rval |= SDXC_MASK_DATA0;
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mmc_writel(host, REG_CLKCR, rval);
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dev_dbg(mmc_dev(host->mmc), "%s REG_CLKCR:%x\n", __func__,
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mmc_readl(host, REG_CLKCR));
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rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
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mmc_writel(host, REG_CMDR, rval);
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do {
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rval = mmc_readl(host, REG_CMDR);
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} while (time_before(jiffies, expire) && (rval & SDXC_START));
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/* clear irq status bits set by the command */
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mmc_writel(host, REG_RINTR,
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mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
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if (rval & SDXC_START) {
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dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
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return -EIO;
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}
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/*only use mask data0 when update clk,clear it when not update clk */
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if (ignore_dat0)
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mmc_writel(host, REG_CLKCR,
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mmc_readl(host, REG_CLKCR) & ~SDXC_MASK_DATA0);
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return 0;
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}
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static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
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{
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struct device_node *np = NULL;
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struct mmc_host *mmc = host->mmc;
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int pwr_save = 0;
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int len = 0;
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if (!mmc->parent || !mmc->parent->of_node) {
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dev_err(mmc_dev(host->mmc),
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"no dts to parse power save mode\n");
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return -EIO;
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}
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np = mmc->parent->of_node;
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if (of_find_property(np, "sunxi-power-save-mode", &len))
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pwr_save = 1;
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return __sunxi_mmc_do_oclk_onoff(host, oclk_en, pwr_save, 1);
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}
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static int sunxi_mmc_updata_pha_v4p10x(struct sunxi_mmc_host *host,
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struct mmc_command *cmd, struct mmc_data *data)
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{
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return sunxi_mmc_oclk_onoff(host, 1);
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}
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static void sunxi_mmc_2xmod_onoff(struct sunxi_mmc_host *host, u32 newmode_en)
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{
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u32 rval = mmc_readl(host, REG_SD_NTSR);
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if (newmode_en)
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rval |= SDXC_2X_TIMING_MODE;
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else
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rval &= ~SDXC_2X_TIMING_MODE;
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mmc_writel(host, REG_SD_NTSR, rval);
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dev_dbg(mmc_dev(host->mmc), "REG_SD_NTSR: 0x%08x ,val %x\n",
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mmc_readl(host, REG_SD_NTSR), rval);
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}
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static int sunxi_mmc_clk_set_rate_for_sdmmc_v4p10x(
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struct sunxi_mmc_host *host, struct mmc_ios *ios)
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{
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u32 mod_clk = 0;
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u32 src_clk = 0;
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u32 rval = 0;
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u32 rval1 = 0;
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s32 err = 0;
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u32 rate = 0;
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u32 clk = 0;
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u32 source_rate = 0;
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u32 sdmmc2mod_rate = 0;
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char *sclk_name = NULL;
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struct clk *sclk = NULL;
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struct clk *mclk2 = NULL;
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struct device *dev = mmc_dev(host->mmc);
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if (ios->clock == 0) {
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__sunxi_mmc_do_oclk_onoff(host, 0, 0, 1);
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return 0;
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}
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if (sunxi_mmc_ddr_timing(ios->timing))
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mod_clk = ios->clock << 1;
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else
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mod_clk = ios->clock;
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if (ios->clock <= 400000) {
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sclk_name = MMC_SRCCLK_HOSC;
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sclk = clk_get(dev, sclk_name);
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} else {
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sclk_name = MMC_SRCCLK_PLL;
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sclk = clk_get(dev, sclk_name);
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}
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if ((sclk == NULL) || IS_ERR(sclk)) {
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dev_err(mmc_dev(host->mmc),
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"Error to get source clock %s %ld\n",
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sclk_name, (long)sclk);
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return -1;
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}
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sunxi_mmc_2xmod_onoff(host, 1);
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mclk2 = clk_get(dev, MMC_2MOD_CLK);
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if (IS_ERR_OR_NULL(mclk2)) {
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dev_err(mmc_dev(host->mmc),
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"Error to get source clock for clk %dHz\n", clk);
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return -1;
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}
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err = clk_set_parent(mclk2, sclk);
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source_rate = clk_get_rate(sclk);
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sdmmc2mod_rate = source_rate/2;
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clk_set_rate(mclk2, sdmmc2mod_rate);
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clk_put(mclk2);
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if (err) {
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clk_put(mclk2);
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return -1;
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}
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rate = clk_round_rate(host->clk_mmc, mod_clk);
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dev_dbg(mmc_dev(host->mmc), "get round rate %d\n", rate);
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clk_disable_unprepare(host->clk_mmc);
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/* sunxi_dump_reg(NULL); */
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err = clk_set_rate(host->clk_mmc, rate);
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if (err) {
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dev_err(mmc_dev(host->mmc),
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"set mclk rate error, rate %dHz\n",
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rate);
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clk_put(sclk);
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return -1;
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}
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rval1 = clk_prepare_enable(host->clk_mmc);
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if (rval1) {
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dev_err(mmc_dev(host->mmc),
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"Enable mmc clk err %d\n", rval1);
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return -1;
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}
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/* sunxi_dump_reg(NULL); */
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src_clk = clk_get_rate(sclk);
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clk_put(sclk);
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dev_dbg(mmc_dev(host->mmc),
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"set round clock %d, soure clk is %d\n",
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rate, src_clk);
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~0xff;
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if (sunxi_mmc_ddr_timing(ios->timing)) {
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rval |= 1;
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ios->clock = rate >> 1;
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clk = ios->clock;
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dev_dbg(mmc_dev(host->mmc), "card clk%d\n", clk);
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} else {
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ios->clock = rate;
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clk = ios->clock;
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}
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mmc_writel(host, REG_CLKCR, rval);
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sunxi_mmc_set_clk_dly(host, ios->clock, ios->bus_width, ios->timing);
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return sunxi_mmc_oclk_onoff(host, 1);
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}
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static void sunxi_mmc_save_spec_reg_v4p10x(struct sunxi_mmc_host *host)
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{
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struct sunxi_mmc_spec_regs *spec_regs = NULL;
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spec_regs = &((struct sunxi_mmc_ver_priv *)(host->version_priv_dat))
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->bak_spec_regs;
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spec_regs->sd_ntsr = mmc_readl(host, REG_SD_NTSR);
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}
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static void sunxi_mmc_restore_spec_reg_v4p10x(struct sunxi_mmc_host *host)
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{
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struct sunxi_mmc_spec_regs *spec_regs = NULL;
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spec_regs = &((struct sunxi_mmc_ver_priv *)(host->version_priv_dat))
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->bak_spec_regs;
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mmc_writel(host, REG_SD_NTSR, spec_regs->sd_ntsr);
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}
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static inline void sunxi_mmc_set_dly_raw(
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struct sunxi_mmc_host *host,
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s32 opha, s32 ipha)
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{
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u32 rval = mmc_readl(host, REG_SD_NTSR);
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if (ipha >= 0) {
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rval &= ~SDXC_STIMING_PH_MASK;
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rval |= (ipha << SDXC_STIMING_PH_SHIFT) & SDXC_STIMING_PH_MASK;
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}
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if (opha >= 0) {
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rval &= ~SDXC_DRV_PH_MASK;
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rval |= (opha << SDXC_DRV_PH_SHIFT) & SDXC_DRV_PH_MASK;
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}
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rval &= ~SDXC_2X_TIMING_MODE;
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mmc_writel(host, REG_SD_NTSR, rval);
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rval |= SDXC_2X_TIMING_MODE;
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mmc_writel(host, REG_SD_NTSR, rval);
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dev_info(mmc_dev(host->mmc), "REG_SD_NTSR: 0x%08x\n",
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mmc_readl(host, REG_SD_NTSR));
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}
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static int sunxi_mmc_judge_retry_v4p10x(
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struct sunxi_mmc_host *host,
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struct mmc_command *cmd, u32 rcnt,
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u32 errno, void *other)
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{
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const s32 sunxi_phase[10][2] = {{-1, -1},
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{1, 1}, {0, 0}, {1, 0}, {0, 1},
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{1, 2}, {0, 2} };
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if (rcnt < (SUNXI_RETRY_CNT_PER_PHA_V4P1X*10)) {
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sunxi_mmc_set_dly_raw(host,
|
|
sunxi_phase[rcnt/SUNXI_RETRY_CNT_PER_PHA_V4P1X][0],
|
|
sunxi_phase[rcnt/SUNXI_RETRY_CNT_PER_PHA_V4P1X][1]);
|
|
} else {
|
|
sunxi_mmc_set_dly_raw(host, sunxi_phase[0][0],
|
|
sunxi_phase[0][1]);
|
|
dev_info(mmc_dev(host->mmc), "sunxi v4p10x retry give up\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static bool sunxi_mmc_hw_busy_v4p10x(struct sunxi_mmc_host *host)
|
|
{
|
|
/**only use for sdc1,because sdc1 used for wifi(*/
|
|
if (host->phy_index == 1)
|
|
return true;
|
|
else
|
|
return false;
|
|
|
|
}
|
|
|
|
void sunxi_mmc_init_priv_v4p10x(struct sunxi_mmc_host *host,
|
|
struct platform_device *pdev, int phy_index)
|
|
{
|
|
struct sunxi_mmc_ver_priv *ver_priv =
|
|
devm_kzalloc(&pdev->dev, sizeof(struct sunxi_mmc_ver_priv),
|
|
GFP_KERNEL);
|
|
host->version_priv_dat = ver_priv;
|
|
ver_priv->mmc_clk_dly[mmc_clk_400k].cmod = mmc_clk_400k;
|
|
ver_priv->mmc_clk_dly[mmc_clk_400k].mod_str = "sunxi-dly-400k";
|
|
ver_priv->mmc_clk_dly[mmc_clk_400k].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_400k].sam_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_26M].cmod = mmc_clk_26M;
|
|
ver_priv->mmc_clk_dly[mmc_clk_26M].mod_str = "sunxi-dly-26M";
|
|
ver_priv->mmc_clk_dly[mmc_clk_26M].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_26M].sam_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M].cmod = mmc_clk_52M,
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M].mod_str = "sunxi-dly-52M";
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M].sam_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].cmod = mmc_clk_52M_DDR4;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].mod_str =
|
|
"sunxi-dly-52M-ddr4";
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].sam_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].cmod = mmc_clk_52M_DDR8;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].mod_str =
|
|
"sunxi-dly-52M-ddr8";
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].sam_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M].cmod = mmc_clk_104M;
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M].mod_str =
|
|
"sunxi-dly-104M";
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M].sam_ph = 00;
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M].cmod = mmc_clk_208M;
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M].mod_str =
|
|
"sunxi-dly-208M";
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M].sam_ph = 00;
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].cmod = mmc_clk_104M_DDR;
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].mod_str =
|
|
"sunxi-dly-104M-ddr";
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].sam_ph = 00;
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].cmod = mmc_clk_208M_DDR;
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].mod_str =
|
|
"sunxi-dly-208M-ddr";
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].drv_ph = 01;
|
|
ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].sam_ph = 00;
|
|
|
|
host->sunxi_mmc_clk_set_rate = sunxi_mmc_clk_set_rate_for_sdmmc_v4p10x;
|
|
host->dma_tl = SUNXI_DMA_TL_SDMMC_V4P1X;
|
|
host->idma_des_size_bits = SUNXI_DES_SIZE_SDMMC_V4P1X;
|
|
host->sunxi_mmc_thld_ctl = NULL;
|
|
host->sunxi_mmc_save_spec_reg = sunxi_mmc_save_spec_reg_v4p10x;
|
|
host->sunxi_mmc_restore_spec_reg = sunxi_mmc_restore_spec_reg_v4p10x;
|
|
sunxi_mmc_reg_ex_res_inter(host, phy_index);
|
|
host->sunxi_mmc_set_acmda = sunxi_mmc_set_a12a;
|
|
host->phy_index = phy_index;
|
|
host->sunxi_mmc_oclk_en = sunxi_mmc_oclk_onoff;
|
|
host->sunxi_mmc_judge_retry = sunxi_mmc_judge_retry_v4p10x;
|
|
host->sunxi_mmc_updata_pha = sunxi_mmc_updata_pha_v4p10x;
|
|
host->sunxi_mmc_hw_busy = sunxi_mmc_hw_busy_v4p10x;
|
|
/*sunxi_of_parse_clk_dly(host);*/
|
|
}
|