581 lines
14 KiB
C
581 lines
14 KiB
C
/*
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* Sunxi SD/MMC host driver
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*
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* Copyright (C) 2015 AllWinnertech Ltd.
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* Author: lixiang <lixiang@allwinnertech>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifdef CONFIG_ARCH_SUN50IW1P1
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#include <linux/clk.h>
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#include <linux/clk/sunxi.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/slot-gpio.h>
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#include "sunxi-mmc.h"
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#include "sunxi-mmc-sun50iw1p1-1.h"
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/*reg*/
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/*SMHC eMMC4.5 DDR Start Bit Detection Control Register */
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/*SMHC CRC Status Detect Control Register */
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/*SMHC Card Threshold Control Register */
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/*SMHC Drive Delay Control Register */
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/*SMHC Sample Delay Control Register */
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/*SMHC Data Strobe Delay Control Register */
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/*SMHC NewTiming Set Register */
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#define SDXC_REG_EDSD (0x010C)
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#define SDXC_REG_CSDC (0x0054)
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#define SDXC_REG_THLD (0x0100)
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#define SDXC_REG_DRV_DL (0x0140)
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#define SDXC_REG_SAMP_DL (0x0144)
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#define SDXC_REG_DS_DL (0x0148)
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#define SDXC_REG_SD_NTSR (0x005C)
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/*bit*/
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#define SDXC_HS400_MD_EN (1U<<31)
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#define SDXC_CARD_WR_THLD_ENB (1U<<2)
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#define SDXC_CARD_RD_THLD_ENB (1U)
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#define SDXC_DAT_DRV_PH_SEL (1U<<17)
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#define SDXC_CMD_DRV_PH_SEL (1U<<16)
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#define SDXC_SAMP_DL_SW_EN (1u<<7)
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#define SDXC_DS_DL_SW_EN (1u<<7)
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#define SDXC_2X_TIMING_MODE (1U<<31)
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/*mask*/
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#define SDXC_CRC_DET_PARA_MASK (0xf)
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#define SDXC_CARD_RD_THLD_MASK (0x0FFF0000)
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#define SDXC_TX_TL_MASK (0xff)
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#define SDXC_RX_TL_MASK (0x00FF0000)
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#define SDXC_SAMP_DL_SW_MASK (0x0000003F)
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#define SDXC_DS_DL_SW_MASK (0x0000003F)
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#define SDXC_SAM_TIMING_PH_MASK (0x00000030)
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/*value*/
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#define SDXC_CRC_DET_PARA_HS400 (6)
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#define SDXC_CRC_DET_PARA_OTHER (3)
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#define SDXC_FIFO_DETH (1024>>2)
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/*size*/
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#define SDXC_CARD_RD_THLD_SIZE (0x00000FFF)
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/*shit*/
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#define SDXC_CARD_RD_THLD_SIZE_SHIFT (16)
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#define SDXC_SAM_TIMING_PH_SHIFT (4)
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enum sunxi_mmc_clk_mode {
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mmc_clk_400k = 0,
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mmc_clk_26M,
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mmc_clk_52M,
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mmc_clk_52M_DDR4,
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mmc_clk_52M_DDR8,
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mmc_clk_104M,
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mmc_clk_208M,
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mmc_clk_104M_DDR,
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mmc_clk_208M_DDR,
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mmc_clk_mod_num,
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};
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struct sunxi_mmc_clk_dly {
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enum sunxi_mmc_clk_mode cmod;
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char *mod_str;
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u32 cmd_drv_ph;
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u32 dat_drv_ph;
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u32 sam_dly;
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u32 ds_dly;
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u32 sam_ph;
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};
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/*sample delay and output deley setting */
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static struct sunxi_mmc_clk_dly mmc_clk_dly[mmc_clk_mod_num] = {
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[mmc_clk_400k] = {
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.cmod = mmc_clk_400k,
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.mod_str = "sunxi-dly-400k",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_26M] = {
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.cmod = mmc_clk_26M,
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.mod_str = "sunxi-dly-26M",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_52M] = {
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.cmod = mmc_clk_52M,
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.mod_str = "sunxi-dly-52M",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_52M_DDR4] = {
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.cmod = mmc_clk_52M_DDR4,
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.mod_str = "sunxi-dly-52M-ddr4",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_52M_DDR8] = {
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.cmod = mmc_clk_52M_DDR8,
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.mod_str = "sunxi-dly-52M-ddr8",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_104M] = {
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.cmod = mmc_clk_104M,
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.mod_str = "sunxi-dly-104M",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_208M] = {
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.cmod = mmc_clk_208M,
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.mod_str = "sunxi-dly-208M",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_104M_DDR] = {
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.cmod = mmc_clk_104M_DDR,
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.mod_str = "sunxi-dly-104M-ddr",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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[mmc_clk_208M_DDR] = {
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.cmod = mmc_clk_208M_DDR,
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.mod_str = "sunxi-dly-208M-ddr",
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.cmd_drv_ph = 1,
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.dat_drv_ph = 0,
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.sam_dly = 0,
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.ds_dly = 0,
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.sam_ph = 0,
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},
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};
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struct sunxi_mmc_spec_regs {
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u32 drv_dl; /*REG_DRV_DL */
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u32 samp_dl; /*REG_SAMP_DL */
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u32 ds_dl; /*REG_DS_DL */
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u32 sd_ntsr; /*REG_SD_NTSR */
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};
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static struct sunxi_mmc_spec_regs bak_spec_regs;
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static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *host, int clk,
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int bus_width, int timing)
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{
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struct mmc_host *mhost = host->mmc;
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u32 rval = 0;
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enum sunxi_mmc_clk_mode cmod = mmc_clk_400k;
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u32 in_clk_dly[5] = { 0 };
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int ret = 0;
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struct device_node *np = NULL;
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if (!mhost->parent || !mhost->parent->of_node) {
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dev_err(mmc_dev(host->mmc),
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"no dts to parse clk dly,use default\n");
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return;
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}
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np = mhost->parent->of_node;
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if (clk <= 400 * 1000) {
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cmod = mmc_clk_400k;
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} else if (clk <= 26 * 1000 * 1000) {
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cmod = mmc_clk_26M;
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} else if (clk <= 52 * 1000 * 1000) {
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if ((bus_width == MMC_BUS_WIDTH_4)
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&& sunxi_mmc_ddr_timing(timing)) {
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cmod = mmc_clk_52M_DDR4;
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} else if ((bus_width == MMC_BUS_WIDTH_8)
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&& (timing == MMC_TIMING_MMC_DDR52)) {
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cmod = mmc_clk_52M_DDR8;
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} else {
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cmod = mmc_clk_52M;
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}
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} else if (clk <= 104 * 1000 * 1000) {
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if ((bus_width == MMC_BUS_WIDTH_8)
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&& (timing == MMC_TIMING_MMC_HS400)) {
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cmod = mmc_clk_104M_DDR;
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} else {
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cmod = mmc_clk_104M;
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}
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} else if (clk <= 208 * 1000 * 1000) {
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if ((bus_width == MMC_BUS_WIDTH_8)
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&& (timing == MMC_TIMING_MMC_HS400)) {
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cmod = mmc_clk_208M_DDR;
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} else {
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cmod = mmc_clk_208M;
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}
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} else {
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dev_err(mmc_dev(mhost), "clk %d is out of range\n", clk);
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return;
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}
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ret = of_property_read_u32_array(np, mmc_clk_dly[cmod].mod_str,
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in_clk_dly, ARRAY_SIZE(in_clk_dly));
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if (ret) {
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dev_dbg(mmc_dev(host->mmc), "failded to get %s used default\n",
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mmc_clk_dly[cmod].mod_str);
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} else {
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mmc_clk_dly[cmod].cmd_drv_ph = in_clk_dly[0];
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mmc_clk_dly[cmod].dat_drv_ph = in_clk_dly[1];
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/*mmc_clk_dly[cmod].sam_dly = in_clk_dly[2]; */
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/*mmc_clk_dly[cmod].ds_dly = in_clk_dly[3]; */
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mmc_clk_dly[cmod].sam_ph = in_clk_dly[4];
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dev_dbg(mmc_dev(host->mmc), "Get %s clk dly ok\n",
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mmc_clk_dly[cmod].mod_str);
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}
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dev_dbg(mmc_dev(host->mmc), "Try set %s clk dly ok\n",
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mmc_clk_dly[cmod].mod_str);
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dev_dbg(mmc_dev(host->mmc), "cmd_drv_ph %d\n",
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mmc_clk_dly[cmod].cmd_drv_ph);
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dev_dbg(mmc_dev(host->mmc), "dat_drv_ph %d\n",
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mmc_clk_dly[cmod].dat_drv_ph);
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dev_dbg(mmc_dev(host->mmc), "sam_ph %d\n",
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mmc_clk_dly[cmod].sam_ph);
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rval = mmc_readl(host, REG_DRV_DL);
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if (mmc_clk_dly[cmod].cmd_drv_ph)
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rval |= SDXC_CMD_DRV_PH_SEL; /*180 phase */
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else
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rval &= ~SDXC_CMD_DRV_PH_SEL; /*90 phase */
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if (mmc_clk_dly[cmod].dat_drv_ph)
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rval |= SDXC_DAT_DRV_PH_SEL; /*180 phase */
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else
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rval &= ~SDXC_DAT_DRV_PH_SEL; /*90 phase */
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mmc_writel(host, REG_DRV_DL, rval);
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/*
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* rval = mmc_readl(host,REG_SAMP_DL);
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* rval &= ~SDXC_SAMP_DL_SW_MASK;
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* rval |= mmc_clk_dly[cmod].sam_dly & SDXC_SAMP_DL_SW_MASK;
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* rval |= SDXC_SAMP_DL_SW_EN;
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* mmc_writel(host,REG_SAMP_DL,rval);
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*
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* rval = mmc_readl(host,REG_DS_DL);
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* rval &= ~SDXC_DS_DL_SW_MASK;
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* rval |= mmc_clk_dly[cmod].ds_dly & SDXC_DS_DL_SW_MASK;
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* rval |= SDXC_DS_DL_SW_EN;
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* mmc_writel(host,REG_DS_DL,rval);
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*/
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rval = mmc_readl(host, REG_SD_NTSR);
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rval &= ~SDXC_SAM_TIMING_PH_MASK;
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rval |=
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(mmc_clk_dly[cmod].
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sam_ph << SDXC_SAM_TIMING_PH_SHIFT) & SDXC_SAM_TIMING_PH_MASK;
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mmc_writel(host, REG_SD_NTSR, rval);
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dev_dbg(mmc_dev(host->mmc), " REG_DRV_DL %08x\n",
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mmc_readl(host, REG_DRV_DL));
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dev_dbg(mmc_dev(host->mmc), " REG_SAMP_DL %08x\n",
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mmc_readl(host, REG_SAMP_DL));
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dev_dbg(mmc_dev(host->mmc), " REG_DS_DL %08x\n",
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mmc_readl(host, REG_DS_DL));
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}
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static int __sunxi_mmc_do_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en,
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u32 pwr_save, u32 ignore_dat0)
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{
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unsigned long expire = jiffies + msecs_to_jiffies(250);
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u32 rval;
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rval = mmc_readl(host, REG_CLKCR);
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rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
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if (oclk_en)
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rval |= SDXC_CARD_CLOCK_ON;
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if (pwr_save)
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rval |= SDXC_LOW_POWER_ON;
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if (ignore_dat0)
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rval |= SDXC_MASK_DATA0;
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mmc_writel(host, REG_CLKCR, rval);
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dev_dbg(mmc_dev(host->mmc), "%s REG_CLKCR:%x\n", __func__,
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mmc_readl(host, REG_CLKCR));
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rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
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mmc_writel(host, REG_CMDR, rval);
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do {
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rval = mmc_readl(host, REG_CMDR);
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} while (time_before(jiffies, expire) && (rval & SDXC_START));
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/* clear irq status bits set by the command */
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/*? */
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mmc_writel(host, REG_RINTR,
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mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
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if (rval & SDXC_START) {
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dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
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return -EIO;
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}
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/*only use mask data0 when update clk,clear it when not update clk */
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if (ignore_dat0)
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mmc_writel(host, REG_CLKCR,
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mmc_readl(host, REG_CLKCR) & ~SDXC_MASK_DATA0);
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return 0;
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}
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static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
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{
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struct device_node *np = NULL;
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struct mmc_host *mmc = host->mmc;
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int pwr_save = 0;
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int len = 0;
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if (!mmc->parent || !mmc->parent->of_node) {
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dev_err(mmc_dev(host->mmc),
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"no dts to parse power save mode\n");
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return -EIO;
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}
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np = mmc->parent->of_node;
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if (of_find_property(np, "sunxi-power-save-mode", &len))
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pwr_save = 1;
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return __sunxi_mmc_do_oclk_onoff(host, oclk_en, pwr_save, 1);
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}
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int sunxi_mmc_oclk_onoff_sdmmc1(struct sunxi_mmc_host *host, u32 oclk_en)
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{
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return sunxi_mmc_oclk_onoff(host, oclk_en);
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}
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static void sunxi_mmc_2xmod_onoff(struct sunxi_mmc_host *host, u32 newmode_en)
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{
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u32 rval = mmc_readl(host, REG_SD_NTSR);
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if (newmode_en)
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rval |= SDXC_2X_TIMING_MODE;
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else
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rval &= ~SDXC_2X_TIMING_MODE;
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mmc_writel(host, REG_SD_NTSR, rval);
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dev_dbg(mmc_dev(host->mmc), "REG_SD_NTSR: 0x%08x ,val %x\n",
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mmc_readl(host, REG_SD_NTSR), rval);
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}
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int sunxi_mmc_clk_set_rate_for_sdmmc1(struct sunxi_mmc_host *host,
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struct mmc_ios *ios)
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{
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u32 mod_clk = 0;
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u32 src_clk = 0;
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u32 rval = 0;
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s32 err = 0;
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u32 rate = 0;
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char *sclk_name = NULL;
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struct clk *mclk = host->clk_mmc;
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struct clk *sclk = NULL;
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struct device *dev = mmc_dev(host->mmc);
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int div = 0;
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if (ios->clock == 0) {
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__sunxi_mmc_do_oclk_onoff(host, 0, 0, 1);
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return 0;
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}
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if (sunxi_mmc_ddr_timing(ios->timing)) {
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mod_clk = ios->clock << 2;
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div = 1;
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} else {
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mod_clk = ios->clock << 1;
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div = 0;
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}
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if (ios->clock <= 400000) {
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sclk = clk_get(dev, "osc24m");
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sclk_name = "osc24m";
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} else {
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sclk = clk_get(dev, "pll_periph");
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sclk_name = "pll_periph";
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}
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|
|
if (IS_ERR(sclk)) {
|
|
dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n",
|
|
sclk_name);
|
|
return -1;
|
|
}
|
|
|
|
sunxi_mmc_oclk_onoff(host, 0);
|
|
|
|
err = clk_set_parent(mclk, sclk);
|
|
if (err) {
|
|
dev_err(mmc_dev(host->mmc), "set parent failed\n");
|
|
clk_put(sclk);
|
|
return -1;
|
|
}
|
|
|
|
rate = clk_round_rate(mclk, mod_clk);
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "get round rate %d\n", rate);
|
|
|
|
clk_disable_unprepare(host->clk_mmc);
|
|
|
|
err = clk_set_rate(mclk, rate);
|
|
if (err) {
|
|
dev_err(mmc_dev(host->mmc), "set mclk rate error, rate %dHz\n",
|
|
rate);
|
|
clk_put(sclk);
|
|
return -1;
|
|
}
|
|
|
|
rval = clk_prepare_enable(host->clk_mmc);
|
|
if (rval) {
|
|
dev_err(mmc_dev(host->mmc), "Enable mmc clk err %d\n", rval);
|
|
return -1;
|
|
}
|
|
|
|
src_clk = clk_get_rate(sclk);
|
|
clk_put(sclk);
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "set round clock %d, soure clk is %d\n",
|
|
rate, src_clk);
|
|
|
|
#ifdef MMC_FPGA
|
|
if (sunxi_mmc_ddr_timing(ios->timing)) {
|
|
/* clear internal divider */
|
|
rval = mmc_readl(host, REG_CLKCR);
|
|
rval &= ~0xff;
|
|
rval |= 1;
|
|
} else {
|
|
/* support internal divide clock under fpga environment */
|
|
rval = mmc_readl(host, REG_CLKCR);
|
|
rval &= ~0xff;
|
|
rval |= 24000000 / mod_clk / 2; /* =24M/400K/2=0x1E*/
|
|
}
|
|
mmc_writel(host, REG_CLKCR, rval);
|
|
dev_info(mmc_dev(host->mmc), "FPGA REG_CLKCR: 0x%08x\n",
|
|
mmc_readl(host, REG_CLKCR));
|
|
#else
|
|
/* clear internal divider */
|
|
rval = mmc_readl(host, REG_CLKCR);
|
|
rval &= ~0xff;
|
|
rval |= div;
|
|
mmc_writel(host, REG_CLKCR, rval);
|
|
#endif
|
|
|
|
/*sunxi_of_parse_clk_dly(host);*/
|
|
sunxi_mmc_2xmod_onoff(host, 1);
|
|
|
|
if (sunxi_mmc_ddr_timing(ios->timing))
|
|
ios->clock = rate >> 2;
|
|
else
|
|
ios->clock = rate >> 1;
|
|
|
|
|
|
sunxi_mmc_set_clk_dly(host, ios->clock, ios->bus_width, ios->timing);
|
|
|
|
return sunxi_mmc_oclk_onoff(host, 1);
|
|
}
|
|
|
|
void sunxi_mmc_thld_ctl_for_sdmmc1(struct sunxi_mmc_host *host,
|
|
struct mmc_ios *ios, struct mmc_data *data)
|
|
{
|
|
u32 bsz = data->blksz;
|
|
/*unit:byte */
|
|
u32 rdtl = ((host->dma_tl & SDXC_RX_TL_MASK) >> 16) << 2;
|
|
u32 rval = 0;
|
|
|
|
if ((data->flags & MMC_DATA_READ)
|
|
&& (bsz <= SDXC_CARD_RD_THLD_SIZE)
|
|
/*((SDXC_FIFO_DETH<<2)-bsz) >= (rdtl)*/
|
|
&& ((SDXC_FIFO_DETH << 2) >= (rdtl + bsz))
|
|
&& ((ios->timing == MMC_TIMING_MMC_HS200)
|
|
|| (ios->timing == MMC_TIMING_UHS_SDR50)
|
|
|| (ios->timing == MMC_TIMING_UHS_SDR104))) {
|
|
rval = mmc_readl(host, REG_THLD);
|
|
rval &= ~SDXC_CARD_RD_THLD_MASK;
|
|
rval |= data->blksz << SDXC_CARD_RD_THLD_SIZE_SHIFT;
|
|
rval |= SDXC_CARD_RD_THLD_ENB;
|
|
mmc_writel(host, REG_THLD, rval);
|
|
} else {
|
|
rval = mmc_readl(host, REG_THLD);
|
|
rval &= ~SDXC_CARD_RD_THLD_ENB;
|
|
mmc_writel(host, REG_THLD, rval);
|
|
}
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "SDXC_REG_THLD: 0x%08x\n",
|
|
mmc_readl(host, REG_THLD));
|
|
|
|
}
|
|
|
|
void sunxi_mmc_save_spec_reg1(struct sunxi_mmc_host *host)
|
|
{
|
|
bak_spec_regs.drv_dl = mmc_readl(host, REG_DRV_DL);
|
|
bak_spec_regs.samp_dl = mmc_readl(host, REG_SAMP_DL);
|
|
bak_spec_regs.ds_dl = mmc_readl(host, REG_DS_DL);
|
|
bak_spec_regs.sd_ntsr = mmc_readl(host, REG_SD_NTSR);
|
|
}
|
|
|
|
void sunxi_mmc_restore_spec_reg1(struct sunxi_mmc_host *host)
|
|
{
|
|
mmc_writel(host, REG_DRV_DL, bak_spec_regs.drv_dl);
|
|
mmc_writel(host, REG_SAMP_DL, bak_spec_regs.samp_dl);
|
|
mmc_writel(host, REG_DS_DL, bak_spec_regs.ds_dl);
|
|
mmc_writel(host, REG_SD_NTSR, bak_spec_regs.sd_ntsr);
|
|
}
|
|
|
|
#endif
|