545 lines
12 KiB
C
Executable File
545 lines
12 KiB
C
Executable File
/*
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* sound\soc\sunxi\virtual_audio\ac100.h
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* (C) Copyright 2010-2016
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* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
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* huangxin <huangxin@reuuimllatech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef _SNDCODEC_H
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#define _SNDCODEC_H
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/*pll source*/
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#define AC100_MCLK1 1
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#define AC100_MCLK2 2
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#define AC100_BCLK1 3
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#define AC100_BCLK2 4
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#define AIF1_CLK 1
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#define AIF2_CLK 2
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#define CHIP_AUDIO_RST 0x0
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#define PLL_CTRL1 0x1
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#define PLL_CTRL2 0x2
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#define SYSCLK_CTRL 0x3
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#define MOD_CLK_ENA 0x4
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#define MOD_RST_CTRL 0x5
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#define AIF_SR_CTRL 0x6
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#define AIF1_CLK_CTRL 0x10
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#define AIF1_ADCDAT_CTRL 0x11
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#define AIF1_DACDAT_CTRL 0x12
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#define AIF1_MXR_SRC 0x13
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#define AIF1_VOL_CTRL1 0x14
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#define AIF1_VOL_CTRL2 0x15
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#define AIF1_VOL_CTRL3 0x16
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#define AIF1_VOL_CTRL4 0x17
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#define AIF1_MXR_GAIN 0x18
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#define AIF1_RXD_CTRL 0x19
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#define AIF2_CLK_CTRL 0x20
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#define AIF2_ADCDAT_CTRL 0x21
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#define AIF2_DACDAT_CTRL 0x22
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#define AIF2_MXR_SRC 0x23
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#define AIF2_VOL_CTRL1 0x24
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#define AIF2_VOL_CTRL2 0x26
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#define AIF2_MXR_GAIN 0x28
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#define AIF2_RXD_CTRL 0x29
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#define AIF3_CLK_CTRL 0x30
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#define AIF3_ADCDAT_CTRL 0x31
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#define AIF3_DACDAT_CTRL 0x32
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#define AIF3_SGP_CTRL 0x33
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#define AIF3_RXD_CTRL 0x39
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#define ADC_DIG_CTRL 0x40
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#define ADC_VOL_CTRL 0x41
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#define ADC_DBG_CTRL 0x42
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#define HMIC_CTRL1 0x44
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#define HMIC_CTRL2 0x45
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#define HMIC_STS 0x46
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#define DAC_DIG_CTRL 0x48
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#define DAC_VOL_CTRL 0x49
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#define DAC_DBG_CTRL 0x4a
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#define DAC_MXR_SRC 0x4c
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#define DAC_MXR_GAIN 0x4d
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#define ADC_APC_CTRL 0x50
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#define ADC_SRC 0x51
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#define ADC_SRCBST_CTRL 0x52
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#define OMIXER_DACA_CTRL 0x53
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#define OMIXER_SR 0x54
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#define OMIXER_BST1_CTRL 0x55
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#define HPOUT_CTRL 0x56
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#define ESPKOUT_CTRL 0x57
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#define SPKOUT_CTRL 0x58
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#define LOUT_CTRL 0x59
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#define ADDA_TUNE1 0x5a
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#define ADDA_TUNE2 0x5b
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#define ADDA_TUNE3 0x5c
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#define HPOUT_STR 0x5d
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/*PLL_CTRL1: 0X01*/
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#define DPLL_DAC_BIAS 14
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#define PLL_POSTDIV_M 8
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#define CLOSE_LOOP 6
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#define INT 0
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/*PLL_CTRL2: 0X02*/
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#define PLL_EN 15
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#define PLL_LOCK_STATUS 14
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#define PLL_PREDIV_NI 4
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#define PLL_POSTDIV_NF 0
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/*SYSCLK_CTRL: 0X3*/
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#define PLLCLK_ENA 15
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#define PLLCLK_SRC 12
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#define AIF1CLK_ENA 11
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#define AIF1CLK_SRC 8
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#define AIF2CLK_ENA 7
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#define AIF2CLK_SRC 4
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#define SYSCLK_ENA 3
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#define SYSCLK_SRC 0
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/*MOD_CLK_ENA: 0x4*/
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#define MOD_CLK_AIF1 15
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#define MOD_CLK_AIF2 14
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#define MOD_CLK_AIF3 13
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#define MOD_CLK_SRC1 11
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#define MOD_CLK_SRC2 10
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#define MOD_CLK_HPF_AGC 7
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#define MOD_CLK_HPF_DRC 6
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#define MOD_CLK_ADC_DIG 3
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#define MOD_CLK_DAC_DIG 2
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/*MOD_RST_CTRL: 0x5*/
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#define MOD_RESET_CTL 0
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#define MOD_RESET_AIF1 15
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#define MOD_RESET_AIF2 14
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#define MOD_RESET_AIF3 13
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#define MOD_RESET_SRC1 11
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#define MOD_RESET_SRC2 10
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#define MOD_RESET_HPF_AGC 7
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#define MOD_RESET_HPF_DRC 6
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#define MOD_RESET_ADC_DIG 3
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#define MOD_RESET_DAC_DIG 2
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/*AIF_SR_CTRL: 0x6*/
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#define AIF1_FS 12
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#define AIF2_FS 8
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#define SRC1_ENA 3
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#define SRC1_SRC 2
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#define SRC2_ENA 1
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#define SRC2_SRC 0
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/*AIF1LCK_CTRL: 0x10*/
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#define AIF1_MSTR_MOD 15
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#define AIF1_BCLK_INV 14
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#define AIF1_LRCK_INV 13
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#define AIF1_BCLK_DIV 9
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#define AIF1_LRCK_DIV 6
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#define AIF1_WORK_SIZ 4
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#define AIF1_DATA_FMT 2
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#define DSP_MONO_PCM 1
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#define AIF1_TDMM_ENA 0
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/*AIF1_ADCDAT_CTRL: 0x11*/
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#define AIF1_AD0L_ENA 15
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#define AIF1_AD0R_ENA 14
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#define AIF1_AD1L_ENA 13
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#define AIF1_AD1R_ENA 12
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#define AIF1_AD0L_SRC 10
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#define AIF1_AD0R_SRC 8
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#define AIF1_AD1L_SRC 6
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#define AIF1_AD1R_SRC 4
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#define AIF1_ADCP_ENA 3
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#define AIF1_ADUL_ENA 2
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#define AIF1_SLOT_SIZ 0
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/*AIF1_DACDAT_CTRL: 0x12*/
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#define AIF1_DA0L_ENA 15
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#define AIF1_DA0R_ENA 14
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#define AIF1_DA1L_ENA 13
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#define AIF1_DA1R_ENA 12
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#define AIF1_DA0L_SRC 10
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#define AIF1_DA0R_SRC 8
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#define AIF1_DA1L_SRC 6
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#define AIF1_DA1R_SRC 4
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#define AIF1_DACP_ENA 3
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#define AIF1_DAUL_ENA 2
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/*#define AIF1_SLOT_SIZ 0*/
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#define AIF1_LOOP_EN 0
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/*AIF1_MXR_SRC: 0x13*/
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/*AIF1 ADCDATA timeslot0 Left Channel mixer source select*/
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#define AIF1_AD0L_AIF1_DA0L_MXR 15
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#define AIF1_AD0L_AIF2_DACL_MXR 14
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#define AIF1_AD0L_ADCL_MXR 13
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#define AIF1_AD0L_AIF2_DACR_MXR 12
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/*AIF1 ADCDATA timeslot0 Right Channel mixer source select*/
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#define AIF1_AD0R_AIF1_DA0R_MXR 11
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#define AIF1_AD0R_AIF2_DACR_MXR 10
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#define AIF1_AD0R_ADCR_MXR 9
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#define AIF1_AD0R_AIF2_DACL_MXR 8
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/*AIF1 ADCDATA timeslot1 Left Channel mixer source select*/
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#define AIF1_AD1L_AIF2_DACL_MXR 7
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#define AIF1_AD1L_ADCL_MXR 6
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#define AIF1_AD1L_MXR_SRC 6
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/*AIF1 ADCDATA timeslot1 Right Channel mixer source select*/
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#define AIF1_AD1R_AIF2_DACR_MXR 3
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#define AIF1_AD1R_ADCR_MXR 2
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#define AIF1_AD1R_MXR_SRC 2
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/*AIF1_VOL_CTRL1: 0x14*/
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#define AIF1_AD0L_VOL 8
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#define AIF1_AD0R_VOL 0
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/*AIF1_VOL_CTRL2: 0x15*/
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#define AIF1_AD1L_VOL 8
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#define AIF1_AD1R_VOL 0
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/*AIF1_VOL_CTRL3: 0x16*/
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#define AIF1_DA0L_VOL 8
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#define AIF1_DA0R_VOL 0
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/*AIF1_VOL_CTRL4: 0x17*/
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#define AIF1_DA1L_VOL 8
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#define AIF1_DA1R_VOL 0
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/*AIF1_MXR_GAIN: 0x18*/
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#define AIF1_AD0L_MXR_GAIN 12
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#define AIF1_AD0R_MXR_GAIN 8
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#define AIF1_AD1L_MXR_GAIN 6
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#define AIF1_AD1R_MXR_GAIN 2
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/*AIF1_RXD_CTRL: 0x19*/
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#define AIF1_N_DATA_DISCARD 8
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/*AIF2_CLK_CTRL: 0x20*/
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#define AIF2_MSTR_MOD 15
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#define AIF2_BCLK_INV 14
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#define AIF2_LRCK_INV 13
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#define AIF2_BCLK_DIV 9
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#define AIF2_LRCK_DIV 6
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#define AIF2_WORD_SIZ 4
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#define AIF2_DATA_FMT 2
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#define AIF2_MONO_PCM 1
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/*AIF2_ADCDAT_CTRL: 0x21*/
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#define AIF2_ADCL_EN 15
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#define AIF2_ADCR_EN 14
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#define AIF2_ADCL_SRC 10
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#define AIF2_ADCR_SRC 8
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#define AIF2_ADCP_ENA 3
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#define AIF2_ADUL_ENA 2
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/*AIF2_DACDAT_CTRL: 0x22*/
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#define AIF2_DACL_ENA 15
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#define AIF2_DACR_ENA 14
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#define AIF2_DACL_SRC 10
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#define AIF2_DACR_SRC 8
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#define AIF2_DACP_ENA 3
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#define AIF2_DAUL_ENA 2
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#define AIF2_LOOP_EN 0
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/*AIF2_MXR_SRC; 0x23*/
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/*AIF2 ADCDATA Left Channel mixer source select*/
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#define AIF2_ADCL_AIF1DA0L_MXR 15
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#define AIF2_ADCL_AIF1DA1L_MXR 14
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#define AIF2_ADCL_AIF2DACR_MXR 13
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#define AIF2_ADCL_ADCL_MXR 12
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#define AIF2_ADCL_MXR_SRC 12
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/*AIF2 ADCDATA Right Channel mixer source select*/
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#define AIF2_ADCR_AIF1DA0R_MXR 11
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#define AIF2_ADCR_AIF1DA1R_MXR 10
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#define AIF2_ADCR_AIF2DACL_MXR 9
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#define AIF2_ADCR_ADCR_MXR 8
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#define AIF2_ADCR_MXR_SRC 8
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/*AIF2_VOL_CTRL1: 0x24*/
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#define AIF2_ADCL_VOL 8
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#define AIF2_ADCR_VOL 0
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/*AIF2_VOL_CTRL2; 0x26*/
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#define AIF2_DACL_VOL 8
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#define AIF2_DACR_VOL 0
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/*AIF2_MXR_GAIN; 0x28*/
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#define AIF2_ADCL_MXR_GAIN 12
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#define AIF2_ADCR_MXR_GAIN 8
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/*AIF2_RXD_CTRL: 0x29*/
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#define AIF2_N_DATA_DISCARD 8
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/*AIF3_CLK_CTRL: 0x30*/
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#define AIF3_BCLK_INV 14
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#define AIF3_LRCK_INV 13
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#define AIF3_WORD_SIZ 4
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#define AIF3_CLOC_SRC 0
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/*AIF3_ADCDAT_CTRL: 0x31*/
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#define AIF3_ADCP_ENA 3
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#define AIF3_ADUL_ENA 2
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/*AIF3_DACDAT_CTRL: 0x32*/
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#define AIF3_DACP_ENA 3
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#define AIF3_DAUL_ENA 2
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#define AIF3_LOOP_ENA 0
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/*AIF3_SGP_CTRL: 0x33*/
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#define AIF3_ADC_SRC 10
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#define AIF2_DAC_SRC 8
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#define AIF3_PINS_TRI 7
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#define AIF3_ADCDAT_SRC 4
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#define AIF2_ADCDAT_SRC 3
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#define AIF2_DACDAT_SRC 2
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#define AIF1_ADCDAT_SRC 1
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#define AIF1_DACDAT_SRC 0
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/*AIF3_RXD_CTRL: 0x39*/
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#define AIF3_N_DATA_DISCARD 8
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/*ADC_DIG_CTRL: 0x40*/
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#define ENAD 15
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#define ENDM 14
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#define ADFIR32 13
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#define ADOUT_DTS 2
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#define ADOUT_DLY 1
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/*ADC_VOL_CTRL: 0x41*/
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#define ADC_VOL_L 8
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#define ADC_VOL_R 0
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/*ADC_DBG_CTRL: 0x42*/
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#define ADSW 15
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#define DMIC_CLK_PIN_CTRL 12
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/*HMIC_CTRL1: 0x44*/
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#define HMIC_M 12
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#define HMIC_N 8
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#define HMIC_DATA_IRQ_MODE 7
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#define HMIC_TH1_HYSTERESIS 5
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#define HMIC_PULLOUT_IRQ 4
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#define HMIC_PLUGIN_IRQ 3
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#define HMIC_KEYUP_IRQ 2
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#define HMIC_KEYDOWN_IRQ 1
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#define HMIC_DATA_IRQ_EN 0
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/*HMIC_CTRL2: 0x45*/
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#define HMIC_SAMPLE_SELECT 14
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#define HMIC_TH2_HYSTERESIS 13
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#define HMIC_TH2 8
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#define HMIC_SF 6
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#define KEYUP_CLEAR 5
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#define HMIC_TH1 0
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/*HMIC_STS: 0x46*/
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#define HMIC_DATA 8
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#define HMIC_PULLOUT_PEND 4
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#define HMIC_PLUGIN_PEND 3
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#define HMIC_KEYUP_PEND 2
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#define HMKC_KEYDOWN_PEND 1
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#define HMIC_DATA_PEND 0
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/*DAC_DIG_CTRL: 0x48*/
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#define ENDA 15
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#define ENHPF 14
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#define DAFIR32 13
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#define MODQU 8
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/*DAC_VOL_CTRL: 0x49*/
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#define DAC_VOL_L 8
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#define DAC_VOL_R 0
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/*DAC_DBG_CTRL: 0x4a*/
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#define DASW 15
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#define ENDWA_N 14
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#define DAC_MOD_DBG 13
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#define DAC_PTN_SEL 6
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#define DVC 0
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/*DAC_MXR_SRC: 0x4c*/
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/*DAC Left Channel mixer SRC*/
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#define DACL_MXR_AIF1_DA0L 15
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#define DACL_MXR_AIF1_DA1L 14
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#define DACL_MXR_AIF2_DACL 13
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#define DACL_MXR_ADCL 12
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#define DACL_MXR_SRC 12
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/*DAC Right Channel mixer SRC*/
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#define DACR_MXR_AIF1_DA0R 11
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#define DACR_MXR_AIF1_DA1R 10
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#define DACR_MXR_AIF2_DACR 9
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#define DACR_MXR_ADCR 8
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#define DACR_MXR_SRC 8
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/*DAC_MXR_GAIN: 0x4d*/
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#define DACL_MXR_GAIN 12
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#define DACR_MXR_GAIN 8
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/*ADC_APC_CTRL: 0x50*/
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#define ADCREN 15
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#define ADCRG 12
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#define ADCLEN 11
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#define ADCLG 8
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#define MBIASEN 7
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#define MMIC_BIAS_CHOP_EN 6
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#define MMIC_BIAS_CHOP_CKS 4
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#define HBIASMOD 2
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#define HBIASEN 1
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#define HBIASADCEN 0
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/*ADC_SRC: 0x51*/
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/*Right ADC mixer Mute CTL*/
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#define RADCMIXMUTEMIC1BOOST (13)
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#define RADCMIXMUTEMIC2BOOST (12)
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#define RADCMIXMUTELINEINLR (11)
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#define RADCMIXMUTELINEINR (10)
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#define RADCMIXMUTEAUXINR (9)
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#define RADCMIXMUTEROUTPUT (8)
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#define RADCMIXMUTELOUTPUT (7)
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/*Left ADC mixer Mute CTL*/
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#define LADCMIXMUTEMIC1BOOST (6)
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#define LADCMIXMUTEMIC2BOOST (5)
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#define LADCMIXMUTELINEINLR (4)
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#define LADCMIXMUTELINEINL (3)
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#define LADCMIXMUTEAUXINL (2)
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#define LADCMIXMUTELOUTPUT (1)
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#define LADCMIXMUTEROUTPUT (0)
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/*ADC_SRCBST_CTRL; 0x52*/
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#define MIC1AMPEN 15
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#define ADC_MIC1G 12
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#define MIC2AMPEN 11
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#define ADC_MIC2G 8
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#define MIC2SLT 7
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#define LINEIN_PREG 4
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#define AUXI_PREG 0
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/*OMIXER_DACA_CTRL: 0x53*/
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#define DACAREN 15
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#define DACALEN 14
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#define RMIXEN 13
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#define LMIXEN 12
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#define HPOUTPUTENABLE 8
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/* #define HP_DRCM_EN 9 */
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/*OMIXER_SR: 0x54*/
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/*Right Output mixer Mute CTL*/
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#define RMIXMUTEMIC1BOOST (13)
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#define RMIXMUTEMIC2BOOST (12)
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#define RMIXMUTELINEINLR (11)
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#define RMIXMUTELINEINR (10)
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#define RMIXMUTEAUXINR (9)
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#define RMIXMUTEDACR (8)
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#define RMIXMUTEDACL (7)
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/*Left Output mixer Mute CTL*/
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#define LMIXMUTEMIC1BOOST (6)
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#define LMIXMUTEMIC2BOOST (5)
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#define LMIXMUTELINEINLR (4)
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#define LMIXMUTELINEINL (3)
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#define LMIXMUTEAUXINL (2)
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#define LMIXMUTEDACL (1)
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#define LMIXMUTEDACR (0)
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/*OMIXER_BST1_CTRL: 0x55*/
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#define BIASVOLTAGE 12
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#define AXG 9
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#define OMIXER_MIC1G 6
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#define OMIXER_MIC2G 3
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#define LINEING 0
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/*HPOUT_CTRL: 0x56*/
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#define RHPS 15
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#define LHPS 14
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#define RHPPA_MUTE 13
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#define LHPPA_MUTE 12
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#define HPPA_EN 11
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#define HP_VOL 4
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#define HPPA_DEL 2
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#define HPPA_IS 0
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/*ESPKOUT_CTRL: 0x57*/
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#define EAR_RAMP_TIME 11
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#define ESPA_OUT_CURRENT 9
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#define ESPSR 7
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#define ESPPA_MUTE 6
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#define ESPPA_EN 5
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#define ESP_VOL 0
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|
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/*SPKOUT_CTRL: 0x58*/
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#define HPCALICKS 13
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#define RSPKS 12
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#define RSPKINVEN 11
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#define RSPK_EN 9
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#define LSPKS 8
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#define LSPKINVEN 7
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#define LSPK_EN 5
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#define SPK_VOL 0
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|
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/*LOUT_CTRL: 0x59*/
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#define LINEOUTG 5
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#define LINEOUTEN 4
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#define LINEOUTS0 3
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#define LINEOUTS1 2
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#define LINEOUTS2 1
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#define LINEOUTS3 0
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|
|
|
/*ADDA_TUNE1: 0x5a*/
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#define CURRENT_TEST_SELECT 14
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#define BIHE_CTRL 12
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#define DITHER 11
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|
#define DITHER_CLK 9
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#define ZERO_CROSSOVER_EN 8
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#define ZERO_CROSSOVER_TIME 7
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|
#define EAR_SPEED_SELECT 6
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#define REF_CHOPPEN_CKS 4
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#define OPMIC_BIAS_CUR 0
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|
|
|
/*ADDA_TUNE2: 0x5b*/
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|
#define OPDAC_BIAS_CUR 14
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#define OPDRV_BIAS_CUR 12
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|
#define OPMIX_BIAS_CUR 10
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|
#define OPEAR_BIAS_CUR 8
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#define OPVR_BIAS_CUR 6
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|
#define OPAAF_BIAS_CUR 4
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|
#define OPADC1_BIAS_CUR 2
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|
#define OPADC2_BIAS_CUR 0
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|
|
|
/*ADDA_TUNE3: 0x5c*/
|
|
#define LDOEN 15
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|
#define LDO_SEL 12
|
|
#define BIASCALIVERIFY 11
|
|
#define BIASMODE 10
|
|
#define BIASCALIDATA 9
|
|
#define OSCS 1
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|
#define OSCEN 0
|
|
|
|
/*HPOUT_STR: 0x5d*/
|
|
#define HPVL_SOFT_MOD 14
|
|
#define HPVL_STEP_CTRL 8
|
|
#define DACA_CHND_ENA 7
|
|
#define HPPA_MXRD_ENA 6
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|
#define HPVL_CTRL_OUT 0
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|
struct spk_gpio {
|
|
u32 gpio;
|
|
bool used;
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|
};
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|
|
|
#define AC100_DEBG
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|
#ifdef AC100_DEBG
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|
#define AC100_DBG(format, args...) \
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|
printk(KERN_INFO"[AC100] "format, ##args)
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#else
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#define AC100_DBG(...)
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#endif
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|
#endif
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