205 lines
5.7 KiB
C
Executable File
205 lines
5.7 KiB
C
Executable File
/*
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* (C) Copyright 2007-2016
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* Allwinnertech Technology Co., Ltd <www.allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#ifndef __SUNXI_IR_H__
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#define __SUNXI_IR_H__
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extern void ir_clk_cfg(void);
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#define MAX_IR_ADDR_NUM (64)
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#define IR_DETECT_NULL (1)
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#define IR_DETECT_OK (2)
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#define IR_DETECT_END (3)
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/*#define SUNXI_IR_DEBUG */
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#ifdef SUNXI_IR_DEBUG
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#define print_debug(fmt, args...) printf(fmt, ##args)
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#else
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#define print_debug(fmt...)
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#endif
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#define CONFIG_FPGA_V4_PLATFORM
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/* Registers */
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#define IR_REG(x) (x)
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#define IR_CTRL_REG IR_REG(0x00) /* IR Control */
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#define IR_RXCFG_REG IR_REG(0x10) /* Rx Config */
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#define IR_RXDAT_REG IR_REG(0x20) /* Rx Data */
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#define IR_RXINTE_REG IR_REG(0x2C) /* Rx Interrupt Enable */
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#define IR_RXINTS_REG IR_REG(0x30) /* Rx Interrupt Status */
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#define IR_SPLCFG_REG IR_REG(0x34) /* IR Sample Config */
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#define IR_FIFO_SIZE (64) /* 64Bytes */
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#if (defined CONFIG_FPGA_V4_PLATFORM) || (defined CONFIG_FPGA_V7_PLATFORM)
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#define CIR_24M_CLK_USED
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#endif
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#ifdef CIR_24M_CLK_USED
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#define IR_SIMPLE_UNIT (21333) /* simple in ns */
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#define IR_CLK (24000000) /* fpga clk output is fixed */
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#define IR_CIR_MODE (0x3 << 4) /* CIR mode enable */
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#define IR_ENTIRE_ENABLE (0x3 << 0) /* IR entire enable */
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#define IR_SAMPLE_DEV (0x3 << 0) /* 24MHz/512 =46875Hz (21333ns) */
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#define IR_FIFO_32 (((IR_FIFO_SIZE >> 1) - 1) << 8)
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#define IR_IRQ_STATUS ((0x1 << 4) | 0x3)
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#else
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#define IR_SIMPLE_UNIT (32000) /* simple in ns */
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#define IR_CLK (8000000)
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#define IR_CIR_MODE (0x3 << 4) /* CIR mode enable */
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#define IR_ENTIRE_ENABLE (0x3 << 0) /* IR entire enable */
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#define IR_SAMPLE_DEV (0x2 << 0) /* 4MHz/256 =31250Hz (32000ns) */
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#define IR_FIFO_32 (((IR_FIFO_SIZE >> 1) - 1) << 8)
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#define IR_IRQ_STATUS ((0x1 << 4) | 0x3)
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#endif
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/* Bit Definition of IR_RXINTS_REG Register */
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#define IR_RXINTS_RXOF (0x1 << 0) /* Rx FIFO Overflow */
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#define IR_RXINTS_RXPE (0x1 << 1) /* Rx Packet End */
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#define IR_RXINTS_RXDA (0x1 << 4) /* Rx FIFO Data Available */
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#ifdef CIR_24M_CLK_USED
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#define IR_RXFILT_VAL \
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(((16) & 0x3f) << 2) /* Filter Threshold = 16*21.3 = ~341us < 500us */
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#define IR_RXIDLE_VAL \
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(((5) & 0xff) \
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<< 8) /* Idle Threshold = (5+1)*128*21.3 = ~16.4ms > 9ms */
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#define IR_ACTIVE_T ((0 & 0xff) << 16) /* Active Threshold */
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#define IR_ACTIVE_T_C ((1 & 0xff) << 23) /* Active Threshold */
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#else
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#define IR_RXFILT_VAL \
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(((12) & 0x3f) << 2) /* Filter Threshold = 12*32 = ~384us < 500us */
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#define IR_RXIDLE_VAL \
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(((2) & 0xff) << 8) /* Idle Threshold = (2+1)*128*32 = ~23.8ms > 9ms \
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*/
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#define IR_ACTIVE_T ((99 & 0xff) << 16) /* Active Threshold */
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#define IR_ACTIVE_T_C ((0 & 0xff) << 23) /* Active Threshold */
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#endif
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enum ir_mode {
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CIR_MODE_ENABLE,
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IR_MODULE_ENABLE,
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};
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enum ir_sample_config {
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IR_SAMPLE_REG_CLEAR,
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IR_CLK_SAMPLE,
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IR_FILTER_TH,
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IR_IDLE_TH,
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IR_ACTIVE_TH,
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};
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enum ir_irq_config {
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IR_IRQ_STATUS_CLEAR,
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IR_IRQ_ENABLE,
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IR_IRQ_FIFO_SIZE,
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};
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enum { IR_SUPLY_DISABLE = 0,
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IR_SUPLY_ENABLE,
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};
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struct ir_raw_event {
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union {
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u32 duration;
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struct {
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u32 carrier;
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u8 duty_cycle;
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};
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};
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unsigned pulse:1;
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unsigned reset:1;
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unsigned timeout:1;
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unsigned carrier_report:1;
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};
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#define DEFINE_IR_RAW_EVENT(event) \
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struct ir_raw_event event = {{.duration = 0}, \
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.pulse = 0, \
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.reset = 0, \
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.timeout = 0, \
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.carrier_report = 0}
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static inline void init_ir_raw_event(struct ir_raw_event *ev)
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{
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memset(ev, 0, sizeof(*ev));
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}
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struct nec_dec {
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int state;
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unsigned count;
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u32 bits;
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bool is_nec_x;
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bool necx_repeat;
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bool curt_repeat;
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};
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struct sunxi_ir_data {
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u32 ir_addr_cnt;
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u32 ir_recoverykey[MAX_IR_ADDR_NUM];
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u32 ir_addr[MAX_IR_ADDR_NUM];
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};
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struct ir_raw_buffer {
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unsigned long dcnt; /*Packet Count*/
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struct nec_dec nec;
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u32 scancode;
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#define IR_RAW_BUF_SIZE 128
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struct ir_raw_event raw[IR_RAW_BUF_SIZE];
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};
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/* macros for IR decoders */
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static inline bool geq_margin(unsigned d1, unsigned d2, unsigned margin)
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{
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return d1 > (d2 - margin);
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}
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static inline bool eq_margin(unsigned d1, unsigned d2, unsigned margin)
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{
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return (d1 > (d2 - margin)) && (d1 < (d2 + margin));
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}
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static inline bool is_transition(struct ir_raw_event *x, struct ir_raw_event *y)
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{
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return x->pulse != y->pulse;
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}
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static inline void decrease_duration(struct ir_raw_event *ev, unsigned duration)
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{
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if (duration > ev->duration)
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ev->duration = 0;
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else
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ev->duration -= duration;
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}
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/* Returns true if event is normal pulse/space event */
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static inline bool is_timing_event(struct ir_raw_event ev)
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{
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return !ev.carrier_report && !ev.reset;
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}
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#define TO_US(duration) DIV_ROUND_CLOSEST((duration), 1000)
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#define TO_STR(is_pulse) ((is_pulse) ? "pulse" : "space")
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void rc_keydown(struct ir_raw_buffer *ir_raw, u32 scancode, u8 toggle);
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int ir_setup(void);
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void ir_disable(void);
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#endif /* end of __SUNXI_IR_H__ */
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