82 lines
3.4 KiB
C
Executable File
82 lines
3.4 KiB
C
Executable File
/*
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* (C) Copyright 2007-2015
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __CCMU_H
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#define __CCMU_H
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#include "../sunxi_def.h"
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/* pll list */
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#define CCMU_PLL_CPUX_CTRL_REG (SUNXI_CCM_BASE + 0x00)
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#define CCMU_PLL_AUDIO_CTRL_REG (SUNXI_CCM_BASE + 0x08)
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#define CCMU_PLL_VIDEO0_CTRL_REG (SUNXI_CCM_BASE + 0x10)
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#define CCMU_PLL_VE_CTRL_REG (SUNXI_CCM_BASE + 0x18)
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#define CCMU_PLL_DDR0_CTRL_REG (SUNXI_CCM_BASE + 0x20)
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#define CCMU_PLL_PERIPH0_CTRL_REG (SUNXI_CCM_BASE + 0x28)
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#define CCMU_PLL_PERIPH1_CTRL_REG (SUNXI_CCM_BASE + 0x2C)
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#define CCMU_PLL_VIDEO1_CTRL_REG (SUNXI_CCM_BASE + 0x30)
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#define CCMU_PLL_GPU_CTRL_REG (SUNXI_CCM_BASE + 0x38)
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#define CCMU_PLL_MIPI_CTRL_REG (SUNXI_CCM_BASE + 0x40)
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#define CCMU_PLL_HSIC_CTRL_REG (SUNXI_CCM_BASE + 0x44)
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#define CCMU_PLL_DE_CTRL_REG (SUNXI_CCM_BASE + 0x48)
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#define CCMU_PLL_DDR1_CTRL_REG (SUNXI_CCM_BASE + 0x4C)
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/* cfg list */
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#define CCMU_CPUX_AXI_CFG_REG (SUNXI_CCM_BASE + 0x50)
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#define CCMU_AHB1_APB1_CFG_REG (SUNXI_CCM_BASE + 0x54)
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#define CCMU_APB2_CFG_GREG (SUNXI_CCM_BASE + 0x58)
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#define CCMU_AHB2_CFG_GREG (SUNXI_CCM_BASE + 0x5C)
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/* gate list */
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#define CCMU_BUS_CLK_GATING_REG0 (SUNXI_CCM_BASE + 0x60)
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#define CCMU_BUS_CLK_GATING_REG1 (SUNXI_CCM_BASE + 0x64)
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#define CCMU_BUS_CLK_GATING_REG2 (SUNXI_CCM_BASE + 0x68)
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#define CCMU_BUS_CLK_GATING_REG3 (SUNXI_CCM_BASE + 0x6C)
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#define CCMU_BUS_CLK_GATING_REG4 (SUNXI_CCM_BASE + 0x70)
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/* module list */
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#define CCMU_NAND0_CLK_REG (SUNXI_CCM_BASE + 0x80)
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#define CCMU_SDMMC0_CLK_REG (SUNXI_CCM_BASE + 0x88)
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#define CCMU_SDMMC1_CLK_REG (SUNXI_CCM_BASE + 0x8C)
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#define CCMU_SDMMC2_CLK_REG (SUNXI_CCM_BASE + 0x90)
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#define CCMU_CE_CLK_REG (SUNXI_CCM_BASE + 0x9C)
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#define CCMU_USBPHY_CLK_REG (SUNXI_CCM_BASE + 0xCC)
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#define CCMU_DRAM_CLK_REG (SUNXI_CCM_BASE + 0xF4)
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#define CCMU_PLL_DDR_CFG_REG (SUNXI_CCM_BASE + 0xF8)
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#define CCMU_MBUS_RST_REG (SUNXI_CCM_BASE + 0xFC)
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#define CCMU_DRAM_CLK_GATING_REG (SUNXI_CCM_BASE + 0x100)
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#define CCMU_AVS_CLK_REG (SUNXI_CCM_BASE + 0x144)
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#define CCMU_MBUS_CLK_REG (SUNXI_CCM_BASE + 0x15C)
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/*gate rst list*/
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#define CCMU_BUS_SOFT_RST_REG0 (SUNXI_CCM_BASE + 0x2C0)
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#define CCMU_BUS_SOFT_RST_REG1 (SUNXI_CCM_BASE + 0x2C4)
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#define CCMU_BUS_SOFT_RST_REG2 (SUNXI_CCM_BASE + 0x2C8)
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#define CCMU_BUS_SOFT_RST_REG3 (SUNXI_CCM_BASE + 0x2D0)
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#define CCMU_BUS_SOFT_RST_REG4 (SUNXI_CCM_BASE + 0x2D8)
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#endif
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