203 lines
6.9 KiB
C
203 lines
6.9 KiB
C
/*
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* Copyright (C) 2013 Allwinnertech, kevin.z.m <kevin@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable periph-based clock implementation
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*/
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#ifndef __MACH_SUNXI_CLK_PERIPH_H
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#define __MACH_SUNXI_CLK_PERIPH_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <asm/div64.h>
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/**
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* struct sunxi_clk_periph_gate - peripheral gate clock
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*
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* @flags: hardware-specific flags
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* @enable: enable register
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* @reset: reset register
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* @bus: bus gating resiter
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* @dram: dram gating register
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* @enb_shift: enable gate bit shift
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* @rst_shift: reset gate bit shift
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* @bus_shift: bus gate bit shift
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* @ddr_shift: dram gate bit shift
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*
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* Flags:
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* SUNXI_PERIPH_NO_GATE - this flag indicates that module gate is not allowed for this module.
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* SUNXI_PERIPH_NO_RESET - This flag indicates that reset is not allowed for this module.
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* SUNXI_PERIPH_NO_BUS_GATE - This flag indicates that bus gate is not allowed for this module.
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* SUNXI_PERIPH_NO_DDR_GATE - This flag indicates that dram gate is not allowed for this module.
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*/
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struct sunxi_clk_periph_gate {
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u32 flags;
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void __iomem *enable;
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void __iomem *reset;
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void __iomem *bus;
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void __iomem *dram;
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u8 enb_shift;
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u8 rst_shift;
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u8 bus_shift;
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u8 ddr_shift;
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};
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/**
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* struct sunxi_clk_periph_div - periph divider clock
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*
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* @reg: register containing divider
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* @mshift: shift to the divider-m bit field, div = (m+1)
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* @mwidth: width of the divider-m bit field
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* @nshift: shift to the divider-n bit field, div = (1<<n)
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* @nwidth: width of the divider-n bit field
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* @lock: register lock
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*
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* Flags:
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*/
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struct sunxi_clk_periph_div {
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void __iomem *reg;
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u8 mshift;
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u8 mwidth;
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u8 nshift;
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u8 nwidth;
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spinlock_t *lock;
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};
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/**
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* struct sunxi_clk_periph_mux - multiplexer clock
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*
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* @reg: register controlling multiplexer
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* @shift: shift to multiplexer bit field
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* @width: width of mutliplexer bit field
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* @lock: register lock
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*
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* Clock with multiple selectable parents. Implements .get_parent, .set_parent
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* and .recalc_rate
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*
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*/
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struct sunxi_clk_periph_mux {
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void __iomem *reg;
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u8 shift;
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u8 width;
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spinlock_t *lock;
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};
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struct sunxi_clk_comgate {
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const u8 *name;
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u16 val;
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u16 mask;
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u8 share;
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u8 res;
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};
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#define BUS_GATE_SHARE 0x01
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#define RST_GATE_SHARE 0x02
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#define MBUS_GATE_SHARE 0x04
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#define MOD_GATE_SHARE 0x08
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#define IS_SHARE_BUS_GATE(x) (x->com_gate?((x->com_gate->share & BUS_GATE_SHARE)?1:0):0)
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#define IS_SHARE_RST_GATE(x) (x->com_gate?((x->com_gate->share & RST_GATE_SHARE)?1:0):0)
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#define IS_SHARE_MBUS_GATE(x) (x->com_gate?((x->com_gate->share & MBUS_GATE_SHARE)?1:0):0)
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#define IS_SHARE_MOD_GATE(x) (x->com_gate?((x->com_gate->share & MOD_GATE_SHARE)?1:0):0)
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/**
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* struct sunxi-clk-periph - peripheral clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @flags: flags used across common struct clk, please take refference of the clk-provider.h
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* @lock: lock for protecting the periph clock operations
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* @mux: mux clock
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* @gate: gate clock
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* @divider: divider clock
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* @com_gate: the shared clock
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* @com_gate_off: bit shift to mark the flag in the com_gate
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* @priv_clkops: divider clock ops
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* @priv_regops: gate clock ops
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*/
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struct sunxi_clk_periph {
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struct clk_hw hw;
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unsigned long flags;
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spinlock_t *lock;
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struct sunxi_clk_periph_mux mux;
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struct sunxi_clk_periph_gate gate;
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struct sunxi_clk_periph_div divider;
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struct sunxi_clk_comgate *com_gate;
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u8 com_gate_off;
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struct clk_ops *priv_clkops;
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struct sunxi_reg_ops *priv_regops;
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};
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struct periph_init_data {
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const char *name;
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unsigned long flags;
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const char **parent_names;
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int num_parents;
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struct sunxi_clk_periph *periph;
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};
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static inline u32 periph_readl(struct sunxi_clk_periph *periph, void __iomem *reg)
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{
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return (((unsigned long)periph->priv_regops) \
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? periph->priv_regops->reg_readl(reg) \
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: readl(reg));
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}
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static inline void periph_writel(struct sunxi_clk_periph *periph, unsigned int val, void __iomem *reg)
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{
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(((unsigned long)periph->priv_regops) \
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? periph->priv_regops->reg_writel(val, reg) \
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: writel(val, reg));
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}
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struct clk *sunxi_clk_register_periph(struct periph_init_data *pd,
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void __iomem *base);
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int sunxi_periph_reset_deassert(struct clk *c);
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int sunxi_periph_reset_assert(struct clk *c);
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void sunxi_clk_get_periph_ops(struct clk_ops *ops);
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#define to_clk_periph(_hw) container_of(_hw, struct sunxi_clk_periph, hw)
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#define SUNXI_CLK_PERIPH(name, _mux_reg, _mux_shift, _mux_width, \
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_div_reg, _div_mshift, _div_mwidth, _div_nshift, _div_nwidth, \
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_gate_flags, _enable_reg, _reset_reg, _bus_gate_reg, _drm_gate_reg, \
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_enable_shift, _reset_shift, _bus_gate_shift, _dram_gate_shift, _lock, _com_gate, _com_gate_off) \
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static struct sunxi_clk_periph sunxi_clk_periph_##name = { \
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.lock = _lock, \
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\
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.mux = { \
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.reg = (void __iomem *)_mux_reg, \
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.shift = _mux_shift, \
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.width = _mux_width, \
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}, \
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\
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.divider = { \
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.reg = (void __iomem *)_div_reg, \
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.mshift = _div_mshift, \
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.mwidth = _div_mwidth, \
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.nshift = _div_nshift, \
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.nwidth = _div_nwidth, \
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}, \
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.gate = { \
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.flags = _gate_flags, \
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.enable = (void __iomem *)_enable_reg, \
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.reset = (void __iomem *)_reset_reg, \
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.bus = (void __iomem *)_bus_gate_reg, \
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.dram = (void __iomem *)_drm_gate_reg, \
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.enb_shift = _enable_shift, \
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.rst_shift = _reset_shift, \
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.bus_shift = _bus_gate_shift, \
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.ddr_shift = _dram_gate_shift, \
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}, \
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.com_gate = _com_gate, \
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.com_gate_off = _com_gate_off, \
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}
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#endif /* __MACH_SUNXI_CLK_PERIPH_H */
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