264 lines
7.1 KiB
C
Executable File
264 lines
7.1 KiB
C
Executable File
/*
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* linux-4.9/drivers/media/platform/sunxi-vfe/vfe_sundev.c
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*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include "vfe.h"
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#include "vfe_os.h"
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#include "vfe_subdev.h"
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#include "platform_cfg.h"
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#include "csi/sunxi_csi.h"
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/*
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* called by subdev in power on/off sequency
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* must be called after update_ccm_info
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*/
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#ifdef VFE_PMU
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static int iovdd_on_off_cnt;
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#endif
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#define CLK_OUT_CTRL_REG 0xf1c000f0
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/* enable/disable pmic channel */
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int vfe_set_pmu_channel(struct v4l2_subdev *sd, enum pmic_channel pmic_ch, enum on_off on_off)
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{
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#ifdef VFE_PMU
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struct vfe_dev *dev = (struct vfe_dev *)dev_get_drvdata(sd->v4l2_dev->dev);
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struct regulator *pmic;
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int ret;
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switch (pmic_ch) {
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case IOVDD:
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pmic = dev->power->iovdd;
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if (pmic) {
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ret = regulator_set_voltage(pmic, dev->power->iovdd_vol, 3300000);
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vfe_dbg(0, "set regulator iovdd = %d, return %x\n", dev->power->iovdd_vol, ret);
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}
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break;
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case DVDD:
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pmic = dev->power->dvdd;
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if (pmic) {
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ret = regulator_set_voltage(pmic,
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dev->power->dvdd_vol, 3300000);
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vfe_dbg(0, "set regulator dvdd = %d, return %x\n", dev->power->dvdd_vol, ret);
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}
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break;
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case AVDD:
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pmic = dev->power->avdd;
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if (pmic) {
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ret = regulator_set_voltage(pmic, dev->power->avdd_vol, 3300000);
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vfe_dbg(0, "set regulator avdd = %d, return %x\n", dev->power->avdd_vol, ret);
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}
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break;
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case AFVDD:
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pmic = dev->power->afvdd;
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if (pmic) {
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ret = regulator_set_voltage(pmic, dev->power->afvdd_vol, 3300000);
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vfe_dbg(0, "set regulator afvdd = %d, return %x\n", dev->power->afvdd_vol, ret);
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}
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break;
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case FLVDD:
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pmic = dev->power->flvdd;
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if (pmic) {
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ret = regulator_set_voltage(pmic, dev->power->flvdd_vol, 3300000);
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vfe_dbg(0, "set regulator flvdd = %d, return %x\n", dev->power->flvdd_vol, ret);
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}
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break;
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default:
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pmic = NULL;
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}
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if (on_off == OFF) {
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if (pmic) {
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if (!regulator_is_enabled(pmic))
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vfe_dbg(0, "regulator_is already disabled\n");
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if (pmic_ch == IOVDD) {
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iovdd_on_off_cnt--;
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vfe_dbg(0, "iovdd_on_off_cnt = %d! return\n", iovdd_on_off_cnt);
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}
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return regulator_disable(pmic);
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}
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} else {
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if (pmic) {
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if (regulator_is_enabled(pmic))
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vfe_dbg(0, "regulator_is already enabled\n");
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if (pmic_ch == IOVDD) {
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iovdd_on_off_cnt++;
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vfe_dbg(0, "iovdd_on_off_cnt = %d!\n", iovdd_on_off_cnt);
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}
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return regulator_enable(pmic);
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}
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}
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#endif
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return 0;
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}
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EXPORT_SYMBOL_GPL(vfe_set_pmu_channel);
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/* enable/disable master clock */
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int vfe_set_mclk(struct v4l2_subdev *sd, enum on_off on_off)
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{
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#ifdef VFE_CLK
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struct vfe_dev *dev = (struct vfe_dev *)dev_get_drvdata(sd->v4l2_dev->dev);
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struct csi_dev *csi = v4l2_get_subdevdata(dev->csi_sd);
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switch (on_off) {
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case ON:
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vfe_print("mclk on\n");
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#if defined CONFIG_ARCH_SUN8IW8P1
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dev->gpio[MCLK_PIN].mul_sel = 3; /*set mclk PIN to MCLK func.*/
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#elif defined CONFIG_ARCH_SUN8IW10P1
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dev->gpio[MCLK_PIN].mul_sel = 4; /*set mclk PIN to MCLK func.*/
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#elif defined CONFIG_ARCH_SUN8IW11P1
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dev->gpio[MCLK_PIN].mul_sel = 3; /*set mclk PIN to MCLK func.*/
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#else
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dev->gpio[MCLK_PIN].mul_sel = 2; /*set mclk PIN to MCLK func.*/
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#endif
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os_gpio_set(&dev->gpio[MCLK_PIN], 1);
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usleep_range(10000, 12000);
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if (csi->clock[CSI_MASTER_CLK]) {
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if (clk_prepare_enable(csi->clock[CSI_MASTER_CLK])) {
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vfe_err("csi%d master clock enable error\n", csi->id);
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return -1;
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}
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#ifdef CONFIG_ARCH_SUN3IW1P1
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/*CLK_OUT enable, CLK_OUT_SRC=OSC24M, DIV=0*/
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writel(0x82000000, CLK_OUT_CTRL_REG);
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#endif
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} else {
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vfe_err("csi%d master clock is null\n", csi->id);
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return -1;
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}
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break;
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case OFF:
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vfe_print("mclk off\n");
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if (csi->clock[CSI_MASTER_CLK]) {
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#ifdef CONFIG_ARCH_SUN3IW1P1
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/*CLK_OUT disable, CLK_OUT_SRC=LOSC, DIV=0*/
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writel(0x00000000, CLK_OUT_CTRL_REG);
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#endif
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clk_disable_unprepare(csi->clock[CSI_MASTER_CLK]);
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} else {
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vfe_err("csi%d master clock is null\n", csi->id);
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return -1;
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}
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usleep_range(10000, 12000);
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dev->gpio[MCLK_PIN].mul_sel = GPIO_OUTPUT; /* set mclk PIN to output. */
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os_gpio_set(&dev->gpio[MCLK_PIN], 1);
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vfe_gpio_write(sd, MCLK_PIN, 0);
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break;
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default:
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return -1;
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}
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#endif
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return 0;
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}
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EXPORT_SYMBOL_GPL(vfe_set_mclk);
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/* set frequency of master clock */
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int vfe_set_mclk_freq(struct v4l2_subdev *sd, unsigned long freq)
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{
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#ifdef VFE_CLK
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struct vfe_dev *dev = (struct vfe_dev *)dev_get_drvdata(sd->v4l2_dev->dev);
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struct csi_dev *csi = v4l2_get_subdevdata(dev->csi_sd);
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struct clk *master_clk_src;
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if (freq == 24000000 || freq == 12000000 || freq == 6000000) {
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if (csi->clock[CSI_MASTER_CLK_24M_SRC]) {
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master_clk_src = csi->clock[CSI_MASTER_CLK_24M_SRC];
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} else {
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vfe_err("csi master clock 24M source is null\n");
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return -1;
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}
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} else {
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if (csi->clock[CSI_MASTER_CLK_PLL_SRC]) {
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master_clk_src = csi->clock[CSI_MASTER_CLK_PLL_SRC];
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} else {
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vfe_err("csi master clock pll source is null\n");
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return -1;
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}
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}
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if (csi->clock[CSI_MASTER_CLK]) {
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if (clk_set_parent(csi->clock[CSI_MASTER_CLK], master_clk_src)) {
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vfe_err("set vfe master clock source failed!!!\n");
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return -1;
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}
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} else {
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vfe_err("csi master clock is null\n");
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return -1;
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}
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if (csi->clock[CSI_MASTER_CLK]) {
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if (clk_set_rate(csi->clock[CSI_MASTER_CLK], freq)) {
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vfe_err("set csi%d master clock error\n", csi->id);
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return -1;
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}
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} else {
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vfe_err("csi master clock is null\n");
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return -1;
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}
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#endif
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return 0;
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}
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EXPORT_SYMBOL_GPL(vfe_set_mclk_freq);
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/* set the gpio io status */
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int vfe_gpio_write(struct v4l2_subdev *sd, enum gpio_type gpio_type, unsigned int status)
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{
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#ifdef VFE_GPIO
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int force_value_flag = 1;
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struct vfe_dev *dev = (struct vfe_dev *)dev_get_drvdata(sd->v4l2_dev->dev);
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u32 gpio = dev->gpio[gpio_type].gpio;
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#ifndef CONFIG_ARCH_SUN3IW1P1
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if ((gpio_type == PWDN) || (gpio_type == RESET))
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force_value_flag = 0;
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#endif
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return os_gpio_write(gpio, status, NULL, force_value_flag);
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#else
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return 0;
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#endif
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}
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EXPORT_SYMBOL_GPL(vfe_gpio_write);
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/* set the gpio io status */
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int vfe_gpio_set_status(struct v4l2_subdev *sd, enum gpio_type gpio_type, unsigned int status)
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{
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#ifdef VFE_GPIO
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struct vfe_dev *dev = (struct vfe_dev *)dev_get_drvdata(sd->v4l2_dev->dev);
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u32 gpio = dev->gpio[gpio_type].gpio;
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return os_gpio_set_status(gpio, status, NULL);
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#else
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return 0;
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#endif
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}
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EXPORT_SYMBOL_GPL(vfe_gpio_set_status);
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/* get standby mode */
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void vfe_get_standby_mode(struct v4l2_subdev *sd, enum standby_mode *stby_mode)
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{
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struct vfe_dev *dev = (struct vfe_dev *)dev_get_drvdata(sd->v4l2_dev->dev);
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*stby_mode = dev->power->stby_mode;
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}
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EXPORT_SYMBOL_GPL(vfe_get_standby_mode);
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MODULE_AUTHOR("raymonxiu");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_DESCRIPTION("Video front end subdev for sunxi");
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