405 lines
8.3 KiB
C
Executable File
405 lines
8.3 KiB
C
Executable File
/*
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* The interface function of controlling the SS register.
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*
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* Copyright (C) 2013 Allwinner.
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*
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* Mintow <duanmintao@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "../sunxi_ss.h"
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#include "sunxi_ss_reg.h"
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inline u32 ss_readl(u32 offset)
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{
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return readl(ss_membase() + offset);
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}
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inline void ss_writel(u32 offset, u32 val)
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{
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writel(val, ss_membase() + offset);
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}
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u32 ss_reg_rd(u32 offset)
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{
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return ss_readl(offset);
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}
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void ss_reg_wr(u32 offset, u32 val)
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{
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ss_writel(offset, val);
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}
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void ss_keyselect_set(int select, ce_task_desc_t *task)
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{
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task->sym_ctl |= select << CE_SYM_CTL_KEY_SELECT_SHIFT;
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}
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void ss_keysize_set(int size, ce_task_desc_t *task)
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{
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int type = CE_AES_KEY_SIZE_128;
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switch (size) {
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case AES_KEYSIZE_192:
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type = CE_AES_KEY_SIZE_192;
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break;
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case AES_KEYSIZE_256:
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type = CE_AES_KEY_SIZE_256;
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break;
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default:
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break;
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}
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task->sym_ctl |= (type << CE_SYM_CTL_KEY_SIZE_SHIFT);
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}
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/* key: phsical address. */
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void ss_key_set(char *key, int size, ce_task_desc_t *task)
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{
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int i = 0;
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int key_sel = CE_KEY_SELECT_INPUT;
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struct {
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int type;
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char desc[AES_MIN_KEY_SIZE];
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} keys[] = {
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{CE_KEY_SELECT_SSK, CE_KS_SSK},
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{CE_KEY_SELECT_HUK, CE_KS_HUK},
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{CE_KEY_SELECT_RSSK, CE_KS_RSSK},
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#ifdef SS_SUPPORT_CE_V3_2
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{CE_KEY_SELECT_SCK0, CE_KS_SCK0},
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{CE_KEY_SELECT_SCK1, CE_KS_SCK1},
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#endif
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{CE_KEY_SELECT_INTERNAL_0, CE_KS_INTERNAL_0},
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{CE_KEY_SELECT_INTERNAL_1, CE_KS_INTERNAL_1},
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{CE_KEY_SELECT_INTERNAL_2, CE_KS_INTERNAL_2},
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{CE_KEY_SELECT_INTERNAL_3, CE_KS_INTERNAL_3},
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{CE_KEY_SELECT_INTERNAL_4, CE_KS_INTERNAL_4},
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{CE_KEY_SELECT_INTERNAL_5, CE_KS_INTERNAL_5},
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{CE_KEY_SELECT_INTERNAL_6, CE_KS_INTERNAL_6},
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{CE_KEY_SELECT_INTERNAL_7, CE_KS_INTERNAL_7},
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{CE_KEY_SELECT_INPUT, ""} };
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while (keys[i].type != CE_KEY_SELECT_INPUT) {
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if (strncasecmp(key, keys[i].desc, AES_MIN_KEY_SIZE) == 0) {
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key_sel = keys[i].type;
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memset(key, 0, size);
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break;
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}
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i++;
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}
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SS_DBG("The key select: %d\n", key_sel);
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ss_keyselect_set(key_sel, task);
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ss_keysize_set(size, task);
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task->key_addr = virt_to_phys(key);
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}
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void ss_pending_clear(int flow)
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{
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int val = CE_CHAN_PENDING << flow;
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ss_writel(CE_REG_ISR, val);
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}
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int ss_pending_get(void)
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{
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return ss_readl(CE_REG_ISR);
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}
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void ss_irq_enable(int flow)
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{
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int val = ss_readl(CE_REG_ICR);
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val |= CE_CHAN_INT_ENABLE << flow;
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ss_writel(CE_REG_ICR, val);
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}
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void ss_irq_disable(int flow)
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{
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int val = ss_readl(CE_REG_ICR);
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val &= ~(CE_CHAN_INT_ENABLE << flow);
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ss_writel(CE_REG_ICR, val);
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}
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void ss_md_get(char *dst, char *src, int size)
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{
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memcpy(dst, src, size);
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}
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/* iv: phsical address. */
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void ss_iv_set(char *iv, int size, ce_task_desc_t *task)
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{
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task->iv_addr = virt_to_phys(iv);
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}
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void ss_iv_mode_set(int mode, ce_task_desc_t *task)
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{
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task->comm_ctl |= mode << CE_COMM_CTL_IV_MODE_SHIFT;
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}
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void ss_cntsize_set(int size, ce_task_desc_t *task)
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{
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task->sym_ctl |= size << CE_SYM_CTL_CTR_SIZE_SHIFT;
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}
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void ss_cnt_set(char *cnt, int size, ce_task_desc_t *task)
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{
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task->ctr_addr = virt_to_phys(cnt);
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ss_cntsize_set(CE_CTR_SIZE_128, task);
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}
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void ss_cts_last(ce_task_desc_t *task)
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{
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task->sym_ctl |= CE_SYM_CTL_AES_CTS_LAST;
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}
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#ifndef SS_SUPPORT_CE_V3_1
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void ss_xts_first(ce_task_desc_t *task)
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{
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task->sym_ctl |= CE_SYM_CTL_AES_XTS_FIRST;
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}
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void ss_xts_last(ce_task_desc_t *task)
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{
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task->sym_ctl |= CE_SYM_CTL_AES_XTS_LAST;
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}
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#endif
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void ss_hmac_sha1_last(ce_task_desc_t *task)
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{
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task->comm_ctl |= CE_HMAC_SHA1_LAST;
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}
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void ss_method_set(int dir, int type, ce_task_desc_t *task)
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{
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task->comm_ctl |= dir << CE_COMM_CTL_OP_DIR_SHIFT;
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task->comm_ctl |= type << CE_COMM_CTL_METHOD_SHIFT;
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}
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void ss_aes_mode_set(int mode, ce_task_desc_t *task)
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{
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task->sym_ctl |= mode << CE_SYM_CTL_OP_MODE_SHIFT;
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}
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void ss_cfb_bitwidth_set(int bitwidth, ce_task_desc_t *task)
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{
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int val = 0;
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switch (bitwidth) {
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case 1:
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val = CE_CFB_WIDTH_1;
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break;
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case 8:
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val = CE_CFB_WIDTH_8;
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break;
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case 64:
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val = CE_CFB_WIDTH_64;
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break;
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case 128:
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val = CE_CFB_WIDTH_128;
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break;
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default:
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break;
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}
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task->sym_ctl |= val << CE_SYM_CTL_CFB_WIDTH_SHIFT;
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}
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void ss_sha_final(void)
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{
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/* unsupported. */
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}
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void ss_check_sha_end(void)
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{
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/* unsupported. */
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}
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void ss_rsa_width_set(int size, ce_task_desc_t *task)
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{
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#ifdef SS_SUPPORT_CE_V3_1
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int width_type = CE_RSA_PUB_MODULUS_WIDTH_512;
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switch (size*8) {
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case 512:
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width_type = CE_RSA_PUB_MODULUS_WIDTH_512;
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break;
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case 1024:
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width_type = CE_RSA_PUB_MODULUS_WIDTH_1024;
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break;
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case 2048:
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width_type = CE_RSA_PUB_MODULUS_WIDTH_2048;
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break;
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case 3072:
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width_type = CE_RSA_PUB_MODULUS_WIDTH_3072;
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break;
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case 4096:
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width_type = CE_RSA_PUB_MODULUS_WIDTH_4096;
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break;
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default:
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break;
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}
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task->asym_ctl |= width_type<<CE_ASYM_CTL_RSA_PM_WIDTH_SHIFT;
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#else
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task->asym_ctl |= DIV_ROUND_UP(size, 4);
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#endif
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}
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void ss_rsa_op_mode_set(int mode, ce_task_desc_t *task)
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{
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/* Consider !2 as M_EXP, for compatible with the previous SOC. */
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if (mode == CE_RSA_OP_M_MUL)
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task->asym_ctl |= CE_RSA_OP_M_MUL<<CE_ASYM_CTL_RSA_OP_SHIFT;
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else
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task->asym_ctl |= CE_RSA_OP_M_EXP<<CE_ASYM_CTL_RSA_OP_SHIFT;
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}
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void ss_ecc_width_set(int size, ce_task_desc_t *task)
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{
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#ifdef SS_SUPPORT_CE_V3_1
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int width_type = CE_ECC_PARA_WIDTH_160;
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switch (size*8) {
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case 224:
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width_type = CE_ECC_PARA_WIDTH_224;
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break;
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case 256:
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width_type = CE_ECC_PARA_WIDTH_256;
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break;
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case 544: /* align with word */
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width_type = CE_ECC_PARA_WIDTH_521;
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break;
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default:
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break;
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}
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task->asym_ctl |= width_type<<CE_ASYM_CTL_ECC_PARA_WIDTH_SHIFT;
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#else
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task->asym_ctl |= DIV_ROUND_UP(size, 4);
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#endif
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}
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void ss_ecc_op_mode_set(int mode, ce_task_desc_t *task)
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{
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#ifdef SS_SUPPORT_CE_V3_1
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task->asym_ctl |= mode<<CE_ASYM_CTL_ECC_OP_SHIFT;
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#else
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task->asym_ctl |= mode<<CE_ASYM_CTL_RSA_OP_SHIFT;
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#endif
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}
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void ss_ctrl_start(ce_task_desc_t *task)
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{
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#ifndef SS_SUPPORT_CE_V3_1
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u32 method = task->comm_ctl&CE_COMM_CTL_METHOD_MASK;
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#endif
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ss_writel(CE_REG_TSK, virt_to_phys(task));
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#ifdef SS_SUPPORT_CE_V3_1
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ss_writel(CE_REG_TLR, 0x1);
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#else
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ss_writel(CE_REG_TLR, 0x1|(method<<CE_REG_TLR_METHOD_TYPE_SHIFT));
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#endif
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}
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void ss_ctrl_stop(void)
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{
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/* unsupported */
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}
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int ss_flow_err(int flow)
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{
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return ss_readl(CE_REG_ERR) & CE_REG_ESR_CHAN_MASK(flow);
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}
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void ss_wait_idle(void)
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{
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#ifdef SS_SUPPORT_CE_V3_1
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while ((ss_readl(CE_REG_TSR) & CE_REG_TSR_BUSY_MASK) ==
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CE_REG_TSR_BUSY) {
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SS_DBG("Need wait for the hardware.\n");
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msleep(20);
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}
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#else
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while ((ss_readl(CE_REG_TSR) & 0xff) != 0x0) {
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SS_DBG("Need wait for the hardware.\n");
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msleep(20);
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}
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#endif
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}
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void ss_data_len_set(int len, ce_task_desc_t *task)
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{
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task->data_len = len;
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}
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int ss_reg_print(char *buf, int len)
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{
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return snprintf(buf, len,
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"The SS control register:\n"
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"[TSK] 0x%02x = 0x%08x\n"
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#ifdef SS_SUPPORT_CE_V3_1
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"[CTL] 0x%02x = 0x%08x\n"
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#endif
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"[ICR] 0x%02x = 0x%08x, [ISR] 0x%02x = 0x%08x\n"
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"[TLR] 0x%02x = 0x%08x\n"
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"[TSR] 0x%02x = 0x%08x\n"
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"[ERR] 0x%02x = 0x%08x\n"
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#ifdef SS_SUPPORT_CE_V3_1
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"[CSS] 0x%02x = 0x%08x, [CDS] 0x%02x = 0x%08x\n"
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#endif
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"[CSA] 0x%02x = 0x%08x, [CDA] 0x%02x = 0x%08x\n"
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#ifdef SS_SUPPORT_CE_V3_1
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"[TPR] 0x%02x = 0x%08x\n"
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#else
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"[HCSA] 0x%02x = 0x%08x\n"
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"[HCDA] 0x%02x = 0x%08x\n"
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"[ACSA] 0x%02x = 0x%08x\n"
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"[ACDA] 0x%02x = 0x%08x\n"
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"[XCSA] 0x%02x = 0x%08x\n"
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"[XCDA] 0x%02x = 0x%08x\n"
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"[VER] 0x%02x = 0x%08x\n"
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#endif
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,
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CE_REG_TSK, ss_readl(CE_REG_TSK),
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#ifdef SS_SUPPORT_CE_V3_1
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CE_REG_CTL, ss_readl(CE_REG_CTL),
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#endif
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CE_REG_ICR, ss_readl(CE_REG_ICR),
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CE_REG_ISR, ss_readl(CE_REG_ISR),
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CE_REG_TLR, ss_readl(CE_REG_TLR),
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CE_REG_TSR, ss_readl(CE_REG_TSR),
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CE_REG_ERR, ss_readl(CE_REG_ERR),
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#ifdef SS_SUPPORT_CE_V3_1
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CE_REG_CSS, ss_readl(CE_REG_CSS),
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CE_REG_CDS, ss_readl(CE_REG_CDS),
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#endif
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CE_REG_CSA, ss_readl(CE_REG_CSA),
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CE_REG_CDA, ss_readl(CE_REG_CDA)
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#ifdef SS_SUPPORT_CE_V3_1
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,
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CE_REG_TPR, ss_readl(CE_REG_TPR)
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#else
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,
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CE_REG_HCSA, ss_readl(CE_REG_HCSA),
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CE_REG_HCDA, ss_readl(CE_REG_HCDA),
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CE_REG_ACSA, ss_readl(CE_REG_ACSA),
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CE_REG_ACDA, ss_readl(CE_REG_ACDA),
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CE_REG_XCSA, ss_readl(CE_REG_XCSA),
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CE_REG_XCDA, ss_readl(CE_REG_XCDA),
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CE_REG_VER, ss_readl(CE_REG_VER)
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#endif
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);
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}
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