163 lines
4.8 KiB
C
Executable File
163 lines
4.8 KiB
C
Executable File
/*
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* The register macro of SUNXI SecuritySystem controller.
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*
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* Copyright (C) 2013 Allwinner.
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*
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* Mintow <duanmintao@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef _SUNXI_SECURITY_SYSTEM_REG_H_
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#define _SUNXI_SECURITY_SYSTEM_REG_H_
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#define SS_REG_CTL 0x00
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#define SS_REG_KEY_BASE 0x04
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#define SS_REG_KEY(n) (SS_REG_KEY_BASE + 4*n)
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#define SS_REG_KEY_NUM 8
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#define SS_REG_IV_BASE 0x24
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#define SS_REG_IV(n) (SS_REG_IV_BASE + 4*n)
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#define SS_REG_IV_NUM 4
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#define SS_REG_FCSR 0x44
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#define SS_REG_ICSR 0x48
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#define SS_REG_MD_BASE 0x4C
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#define SS_REG_MD(n) (SS_REG_MD_BASE + 4*n)
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#define SS_REG_MD_NUM 5
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#define SS_REG_CNT_BASE 0x34
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#define SS_REG_CNT(n) (SS_REG_CNT_BASE + 4*n)
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#define SS_REG_CNT_NUM 4
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#if defined(CONFIG_ARCH_SUN8IW5) || defined(CONFIG_ARCH_SUN8IW8)
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#define SS_REG_CTS_LEN 0x60
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#endif
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#define SS_REG_RXFIFO 0x200
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#define SS_REG_TXFIFO 0x204
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#define SS_KEY_SELECT_INPUT 0
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#define SS_KEY_SELECT_SID_R 1
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#define SS_KEY_SELECT_SID_B 2
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#define SS_KEY_SELECT_INTER 3
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#define SS_REG_CTL_KEY_SELECT_SHIFT 24
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#define SS_REG_CTL_KEY_SELECT_MASK (0x4 << SS_REG_CTL_KEY_SELECT_SHIFT)
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#define SS_RNG_MODE_ONESHOT 0
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#define SS_RNG_MODE_CONTINUE 1
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#define SS_REG_CTL_PRNG_MODE_SHIFT 15
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#define SS_REG_CTL_PRNG_MODE_MASK (1 << SS_REG_CTL_PRNG_MODE_SHIFT)
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#define SS_IV_MODE_CONSTANT 0
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#define SS_IV_MODE_ARBITRARY 1
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#define SS_REG_CTL_IV_MODE_SHIFT 14
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#define SS_REG_CTL_IV_MODE_MASK (1 << SS_REG_CTL_IV_MODE_SHIFT)
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#define SS_AES_MODE_ECB 0
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#define SS_AES_MODE_CBC 1
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#define SS_AES_MODE_CTR 2
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#if defined(CONFIG_ARCH_SUN8IW5) || defined(CONFIG_ARCH_SUN8IW8)
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#define SS_AES_MODE_CTS 3
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#endif
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#define SS_REG_CTL_OP_MODE_SHIFT 12
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#define SS_REG_CTL_OP_MODE_MASK (0x3 << SS_REG_CTL_OP_MODE_SHIFT)
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#define SS_CTR_SIZE_16 0
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#define SS_CTR_SIZE_32 1
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#define SS_CTR_SIZE_64 2
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#define SS_REG_CTL_CTR_SIZE_SHIFT 10
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#define SS_REG_CTL_CTR_SIZE_MASK (0x3 << SS_REG_CTL_CTR_SIZE_SHIFT)
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#define SS_AES_KEY_SIZE_128 0
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#define SS_AES_KEY_SIZE_192 1
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#define SS_AES_KEY_SIZE_256 2
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#define SS_REG_CTL_KEY_SIZE_SHIFT 8
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#define SS_REG_CTL_KEY_SIZE_MASK (0x3 << SS_REG_CTL_KEY_SIZE_SHIFT)
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#define SS_DIR_ENCRYPT 0
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#define SS_DIR_DECRYPT 1
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#define SS_REG_CTL_OP_DIR_SHIFT 7
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#define SS_REG_CTL_OP_DIR_MASK (0x1 << SS_REG_CTL_OP_DIR_SHIFT)
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#define SS_METHOD_AES 0
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#define SS_METHOD_DES 1
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#define SS_METHOD_3DES 2
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#define SS_METHOD_SHA1 3
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#define SS_METHOD_MD5 4
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#define SS_METHOD_PRNG 5
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#define SS_REG_CTL_METHOD_SHIFT 4
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#define SS_REG_CTL_METHOD_MASK (0x7 << SS_REG_CTL_METHOD_SHIFT)
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#define SS_METHOD_IS_HASH(type) ((type == SS_METHOD_MD5) \
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|| (type == SS_METHOD_SHA1))
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#define SS_REG_CTL_SHA_END_SHIFT 2
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#define SS_REG_CTL_SHA_END_MASK (0x1 << SS_REG_CTL_SHA_END_SHIFT)
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#define SS_CTL_START 1
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#define SS_REG_CTL_START_MASK 0x1
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#define SS_REG_FCSR_RXFIFO_STATUS BIT(30)
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#define SS_REG_FCSR_RXFIFO_EMP_CNT_SHIFT 24
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#define SS_REG_FCSR_RXFIFO_EMP_CNT_MASK \
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(0x3F << SS_REG_FCSR_RXFIFO_EMP_CNT_SHIFT)
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#define SS_REG_FCSR_TXFIFO_STATUS BIT(22)
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#define SS_REG_FCSR_TXFIFO_AVA_CNT_SHIFT 16
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#define SS_REG_FCSR_TXFIFO_AVA_CNT_MASK \
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(0x3F << SS_REG_FCSR_TXFIFO_AVA_CNT_SHIFT)
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#define SS_REG_FCSR_RXFIFO_TRIG_LEVEL_SHIFT 8
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#define SS_REG_FCSR_RXFIFO_TRIG_LEVEL_MASK \
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(0x1F << SS_REG_FCSR_RXFIFO_TRIG_LEVEL_SHIFT)
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#define SS_REG_FCSR_TXFIFO_TRIG_LEVEL_SHIFT 0
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#define SS_REG_FCSR_TXFIFO_TRIG_LEVEL_MASK \
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(0x1F << SS_REG_FCSR_TXFIFO_TRIG_LEVEL_SHIFT)
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#define SS_REG_ICSR_RXFIFO_EMP_PENDING BIT(10)
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#define SS_REG_ICSR_TXFIFO_AVA_PENDING BIT(8)
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#define SS_REG_ICSR_DRA_ENABLE BIT(4)
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#define SS_REG_ICSR_RXFIFO_EMP_INT_ENABLE BIT(2)
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#define SS_REG_ICSR_TXFIFO_AVA_INT_ENABLE BIT(0)
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#define SS_SEED_SIZE 24
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/* Function declaration */
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u32 ss_reg_rd(u32 offset);
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void ss_reg_wr(u32 offset, u32 val);
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void ss_keyselect_set(int select);
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void ss_keysize_set(int size);
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void ss_key_set(char *key, int size);
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void ss_fifo_init(void);
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void ss_flow_enable(int flow);
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void ss_flow_mode_set(int mode);
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int ss_pending_get(void);
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void ss_pending_clear(int flow);
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void ss_dma_enable(int flow);
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void ss_dma_disable(int flow);
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void ss_iv_set(char *iv, int size);
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void ss_cntsize_set(int size);
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void ss_cnt_set(char *cnt, int size);
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void ss_cnt_get(int flow, char *cnt, int size);
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void ss_md_get(char *dst, char *src, int size);
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void ss_sha_final(void);
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void ss_check_sha_end(void);
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void ss_iv_mode_set(int mode);
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void ss_method_set(int dir, int type);
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void ss_aes_mode_set(int mode);
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void ss_rng_mode_set(int mode);
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int ss_random_rd(char *data, int len);
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void ss_wait_idle(void);
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void ss_ctrl_start(void);
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void ss_ctrl_stop(void);
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int ss_reg_print(char *buf, int len);
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#endif /* end of _SUNXI_SECURITY_SYSTEM_REG_H_ */
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