981 lines
25 KiB
C
Executable File
981 lines
25 KiB
C
Executable File
/*
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*********************************************************************************************************
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* LINUX-KERNEL
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* AllWinner Linux Platform Develop Kits
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* Kernel Module
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*
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* (c) Copyright 2006-2011, kevin.z China
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* All Rights Reserved
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*
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* File : standby_clock.c
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* By : kevin.z
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* Version : v1.0
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* Date : 2011-5-31 13:40
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* Descript: ccmu process for platform standby;
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* Update : date auther ver notes
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*********************************************************************************************************
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*/
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#include "standby_i.h"
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#define readb(addr) (*((volatile unsigned char *)(addr)))
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#define readw(addr) (*((volatile unsigned short *)(addr)))
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#define readl(addr) (*((volatile unsigned long *)(addr)))
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#define writeb(v, addr) (*((volatile unsigned char *)(addr)) = (unsigned char)(v))
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#define writew(v, addr) (*((volatile unsigned short *)(addr)) = (unsigned short)(v))
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#define writel(v, addr) (*((volatile unsigned long *)(addr)) = (unsigned long)(v))
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#ifdef CONFIG_ARCH_SUN8IW8P1
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#else
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static void *r_prcm;
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#endif
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static __ccmu_reg_list_t *CmuReg;
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//==============================================================================
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// CLOCK SET FOR SYSTEM STANDBY
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//==============================================================================
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#ifdef CONFIG_ARCH_SUN8I
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static __ccmu_pll1_reg0000_t CmuReg_Pll1Ctl_tmp;
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static __ccmu_sysclk_ratio_reg0050_t CmuReg_SysClkDiv_tmp;
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#ifdef CONFIG_ARCH_SUN8IW8P1
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#define PIO_INT_DEB_REG (AW_GPIO_BASE_PA + 0x258)
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static __u32 pio_int_deb_back = 0;
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static __ccmu_ahb1_ratio_reg0054_t CmuReg_ahb1_tmp;
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static __ccmu_ahb1_ratio_reg0054_t CmuReg_ahb1_backup;
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static __ccmu_apb2_ratio_reg0058_t CmuReg_apb2_tmp;
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static __ccmu_apb2_ratio_reg0058_t CmuReg_apb2_backup;
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static __ccmu_ahb2_ratio_reg005c_t CmuReg_ahb2_tmp;
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static __ccmu_ahb2_ratio_reg005c_t CmuReg_ahb2_backup;
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/*
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*********************************************************************************************************
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* standby_clk_init
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*
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*Description: ccu init for platform standby
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*
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*Arguments : none
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*
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*Return : result,
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*
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*Notes :
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_init(void)
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{
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CmuReg = (__ccmu_reg_list_t *)IO_ADDRESS(AW_CCM_BASE);
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_exit
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*
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*Description: ccu exit for platform standby
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*
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*Arguments : none
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*
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*Return : result,
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*
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*Notes :
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_exit(void)
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{
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_core2losc
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*
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* Description: switch core clock to 32k low osc.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_core2losc(void)
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{
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unsigned int tmp;
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//CmuReg->SysClkDiv.CpuClkSrc = 0;
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/* cpu frequency is internal Losc hz */
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tmp = readl(&(CmuReg->SysClkDiv));
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tmp &= (~(0x00030000));
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writel(tmp, &(CmuReg->SysClkDiv));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_core2hosc
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*
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* Description: switch core clock to 24M high osc.
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*
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* Arguments : none
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_core2hosc(void)
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{
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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CmuReg_SysClkDiv_tmp.bits.CpuClkSrc = 1;
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CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_core2pll
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*
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* Description: switch core clock to core pll.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_core2pll(void)
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{
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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CmuReg_SysClkDiv_tmp.bits.CpuClkSrc = 2;
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CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_plldisable
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*
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* Description: disable dram pll.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_plldisable(void)
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{
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unsigned int tmp;
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//pll1
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tmp = readl(&(CmuReg->Pll1Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll1Ctl));
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//pll6: for periph0
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tmp = readl(&(CmuReg->Pll6Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll6Ctl));
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//pll9: periph 1
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tmp = readl(&(CmuReg->Pll9Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll9Ctl));
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#if 0
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//pll2: for audio
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tmp = readl(&(CmuReg->Pll2Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll2Ctl));
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//pll3: for video
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tmp = readl(&(CmuReg->Pll3Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll3Ctl));
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//pll4: for ve
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tmp = readl(&(CmuReg->Pll4Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll4Ctl));
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//pll5: for ddr
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tmp = readl(&(CmuReg->Pll5Ctl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->Pll5Ctl));
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//pll7: for isp
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tmp = readl(&(CmuReg->PllIspCtl));
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tmp &= (~(0x80000000));
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writel(tmp, &(CmuReg->PllIspCtl));
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#endif
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_pllenable
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*
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* Description: enable dram pll.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_pllenable(void)
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{
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unsigned int tmp;
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//pll1
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tmp = readl(&(CmuReg->Pll1Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll1Ctl));
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//pll6: for periph0
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tmp = readl(&(CmuReg->Pll6Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll6Ctl));
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//pll9: periph 1
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tmp = readl(&(CmuReg->Pll9Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll9Ctl));
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#if 0
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//pll2: for audio
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tmp = readl(&(CmuReg->Pll2Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll2Ctl));
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//pll3: for video
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tmp = readl(&(CmuReg->Pll3Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll3Ctl));
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//pll4: for ve
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tmp = readl(&(CmuReg->Pll4Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll4Ctl));
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//pll5: for ddr
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tmp = readl(&(CmuReg->Pll5Ctl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->Pll5Ctl));
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//pll7: for isp
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tmp = readl(&(CmuReg->PllIspCtl));
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tmp |= ((0x80000000));
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writel(tmp, &(CmuReg->PllIspCtl));
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#endif
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return 0;
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}
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#if 0
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/*
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*********************************************************************************************************
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* standby_clk_pll1enable
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*
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* Description: enable pll1.
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*
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* Arguments : none
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*
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*********************************************************************************************************
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*/
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__s32 standby_clk_pll1enable(void)
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{
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CmuReg_Pll1Ctl_tmp.dwval = CmuReg->Pll1Ctl.dwval;
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CmuReg_Pll1Ctl_tmp.bits.PLLEn = 1;
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CmuReg->Pll1Ctl.dwval = CmuReg_Pll1Ctl_tmp.dwval;
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return 0;
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}
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#endif
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/*
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*********************************************************************************************************
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* standby_clk_hoscdisable
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*
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* Description: disable HOSC.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_hoscdisable(void)
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{
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unsigned int tmp;
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//0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1)
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//bit2: hosc;
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//bit1: ldo for analog;
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//bit0: ldo for digital
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//keyfield set to: 0xa7
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tmp = readl((void *)(0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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tmp |= ((0xa7000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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//disable hosc
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0x00000004));
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writel(tmp, (0xf1c00000 + 0xf4));
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//keyfield set to: 0
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_hoscenable
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*
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* Description: enable HOSC.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_hoscenable(void)
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{
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unsigned int tmp;
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//0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1)
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//bit2: hosc;
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//bit1: ldo for analog;
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//bit0: ldo for digital
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//keyfield set to: 0xa7
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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tmp |= ((0xa7000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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//enable hosc
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tmp = readl((0xf1c00000 + 0xf4));
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tmp |= ((0x00000004));
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writel(tmp, (0xf1c00000 + 0xf4));
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//keyfield set to: 0
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_ldodisable
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*
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* Description: disable LDO.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_ldodisable(void)
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{
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unsigned int tmp;
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//0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1)
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//bit2: hosc;
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//bit1: ldo for analog;
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//bit0: ldo for digital
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//keyfield set to: 0xa7
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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tmp |= ((0xa7000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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//disable ldo
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0x00000003));
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writel(tmp, (0xf1c00000 + 0xf4));
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//keyfield set to: 0
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_ldoenable
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*
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* Description: enable LDO.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_ldoenable(void)
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{
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unsigned int tmp;
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//0xf1c00000 + 0xf4 (system_ctrl: pll ctrl reg1)
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//bit2: hosc;
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//bit1: ldo for analog;
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//bit0: ldo for digital
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//keyfield set to: 0xa7
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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tmp |= ((0xa7000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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//enable ldo
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tmp = readl((0xf1c00000 + 0xf4));
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tmp |= ((0x00000003));
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writel(tmp, (0xf1c00000 + 0xf4));
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//keyfield set to: 0
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tmp = readl((0xf1c00000 + 0xf4));
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tmp &= (~(0xff000000));
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writel(tmp, (0xf1c00000 + 0xf4));
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_setdiv
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*
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* Description: switch core clock to 32k low osc.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_setdiv(struct standby_clk_div_t *clk_div)
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{
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unsigned int tmp;
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if(!clk_div)
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{
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return -1;
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}
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//axi
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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CmuReg_SysClkDiv_tmp.bits.AXIClkDiv = clk_div->axi_div;
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CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
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//ahb1
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CmuReg_ahb1_tmp.dwval = CmuReg->Ahb1Div.dwval;
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CmuReg_ahb1_tmp.bits.Ahb1Div = clk_div->ahb_div;
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CmuReg_ahb1_tmp.bits.Ahb1PreDiv = clk_div->ahb_pre_div;
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CmuReg->Ahb1Div.dwval = CmuReg_ahb1_tmp.dwval;
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//apb2
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CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
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CmuReg_apb2_tmp.bits.DivM = clk_div->apb_div;
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CmuReg_apb2_tmp.bits.DivN = clk_div->apb_pre_div;
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CmuReg->Apb2Div.dwval = CmuReg_apb2_tmp.dwval;
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_clk_getdiv
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*
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* Description: switch core clock to 32k low osc.
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*
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* Arguments : none
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*
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_getdiv(struct standby_clk_div_t *clk_div)
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{
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if(!clk_div)
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{
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return -1;
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}
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//axi
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CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
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clk_div->axi_div = CmuReg_SysClkDiv_tmp.bits.AXIClkDiv;
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//ahb1
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CmuReg_ahb1_tmp.dwval = CmuReg->Ahb1Div.dwval;
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clk_div->ahb_div = CmuReg_ahb1_tmp.bits.Ahb1Div;
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clk_div->ahb_pre_div = CmuReg_ahb1_tmp.bits.Ahb1PreDiv;
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//apb2
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CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
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clk_div->apb_div = CmuReg_apb2_tmp.bits.DivM;
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clk_div->apb_pre_div = CmuReg_apb2_tmp.bits.DivN;
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return 0;
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}
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|
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/*
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*********************************************************************************************************
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|
* standby_clk_set_pll_factor
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*
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* Description: set pll factor, target cpu freq is 384M hz
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*
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* Arguments : none
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*
|
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* Returns : 0;
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*********************************************************************************************************
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*/
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__s32 standby_clk_set_pll_factor(struct pll_factor_t *pll_factor)
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|
{
|
|
__ccmu_pll1_reg0000_t pll1_ctrl;
|
|
|
|
if(!pll_factor)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
pll1_ctrl.dwval = readl(&(CmuReg->Pll1Ctl));
|
|
|
|
pll1_ctrl.bits.FactorN = pll_factor->FactorN;
|
|
pll1_ctrl.bits.FactorK = pll_factor->FactorK;
|
|
pll1_ctrl.bits.FactorM = pll_factor->FactorM;
|
|
pll1_ctrl.bits.FactorP = pll_factor->FactorP;
|
|
|
|
writel(pll1_ctrl.dwval, &(CmuReg->Pll1Ctl));
|
|
//busy_waiting();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_get_pll_factor
|
|
*
|
|
* Description:
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
|
|
__s32 standby_clk_get_pll_factor(struct pll_factor_t *pll_factor)
|
|
{
|
|
__ccmu_pll1_reg0000_t pll1_ctrl;
|
|
|
|
if(!pll_factor)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
pll1_ctrl.dwval = readl(&(CmuReg->Pll1Ctl));
|
|
|
|
pll_factor->FactorN = pll1_ctrl.bits.FactorN;
|
|
pll_factor->FactorK = pll1_ctrl.bits.FactorK;
|
|
pll_factor->FactorM = pll1_ctrl.bits.FactorM;
|
|
pll_factor->FactorP = pll1_ctrl.bits.FactorP;
|
|
|
|
//busy_waiting();
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_apb2losc
|
|
*
|
|
* Description: switch apb2 clock to 32k low osc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_apb2losc(void)
|
|
{
|
|
unsigned int tmp;
|
|
|
|
//apb2
|
|
CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
|
|
CmuReg_apb2_tmp.bits.ClkSrc = APB2_CLKSRC_LOSC;
|
|
CmuReg->Apb2Div.dwval = CmuReg_apb2_tmp.dwval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_apb2hosc
|
|
*
|
|
* Description: switch apb2 clock to 24M hosc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_apb2hosc(void)
|
|
{
|
|
unsigned int tmp;
|
|
|
|
//apb2
|
|
CmuReg_apb2_tmp.dwval = CmuReg->Apb2Div.dwval;
|
|
CmuReg_apb2_tmp.bits.ClkSrc = APB2_CLKSRC_HOSC;
|
|
CmuReg->Apb2Div.dwval = CmuReg_apb2_tmp.dwval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_bus_src_backup
|
|
*
|
|
* Description: switch ahb2->?
|
|
* ahb1->?.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_bus_src_backup(void)
|
|
{
|
|
//backup bus src cfg
|
|
/* backup ahb clk src */
|
|
CmuReg_ahb1_backup.dwval = CmuReg->Ahb1Div.dwval;
|
|
CmuReg_ahb2_backup.dwval = CmuReg->Ahb2Div.dwval;
|
|
/* backup apb clk src */
|
|
CmuReg_apb2_backup.dwval = CmuReg->Apb2Div.dwval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_bus_src_set
|
|
*
|
|
* Description: switch ahb2->ahb1->axi.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
|
|
__s32 standby_clk_bus_src_set(void)
|
|
{
|
|
/* change ahb2 clock to ahb1*/
|
|
CmuReg_ahb2_tmp.dwval = CmuReg->Ahb2Div.dwval;
|
|
CmuReg_ahb2_tmp.bits.ClkSrc = AHB2_CLKSRC_AHB1;
|
|
CmuReg->Ahb2Div.dwval = CmuReg_ahb2_tmp.dwval;
|
|
//printk("CmuReg_ahb2_backup, %x!\n", CmuReg_ahb2_backup);
|
|
|
|
/* change ahb1 clock to axi */
|
|
CmuReg_ahb1_tmp.dwval = CmuReg->Ahb1Div.dwval;
|
|
CmuReg_ahb1_tmp.bits.ClkSrc = AHB1_CLKSRC_AXI;
|
|
CmuReg->Ahb1Div.dwval = CmuReg_ahb1_tmp.dwval;
|
|
// printk("CmuReg_ahb1_backup, %x!\n", CmuReg_ahb1_backup);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_bus_src_restore
|
|
*
|
|
* Description: switch ahb2->?
|
|
* ahb1->?.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_bus_src_restore(void)
|
|
{
|
|
/* restore ahb clk src */
|
|
CmuReg->Ahb2Div.dwval = CmuReg_ahb2_backup.dwval;
|
|
CmuReg->Ahb1Div.dwval = CmuReg_ahb1_backup.dwval;
|
|
|
|
/* restore apb clk src */
|
|
CmuReg->Apb2Div.dwval = CmuReg_apb2_backup.dwval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_dramgating
|
|
*
|
|
* Description: gating dram clock.
|
|
*
|
|
* Arguments : onoff dram clock gating on or off;
|
|
*
|
|
* Returns : 0;
|
|
*********************************************************************************************************
|
|
*/
|
|
void standby_clk_dramgating(int onoff)
|
|
{
|
|
unsigned int tmp;
|
|
tmp = readl(&(CmuReg->Pll5Ctl));
|
|
|
|
if(onoff) {
|
|
tmp |= (0x80000000);
|
|
}
|
|
else {
|
|
tmp &= (~0x80000000);
|
|
}
|
|
|
|
writel(tmp, &(CmuReg->Pll5Ctl));
|
|
|
|
return ;
|
|
}
|
|
|
|
#else
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_init
|
|
*
|
|
*Description: ccu init for platform standby
|
|
*
|
|
*Arguments : none
|
|
*
|
|
*Return : result,
|
|
*
|
|
*Notes :
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_init(void)
|
|
{
|
|
#ifdef CONFIG_ARCH_SUN8IW8P1
|
|
#else
|
|
r_prcm = (void *)IO_ADDRESS(AW_R_PRCM_BASE);
|
|
#endif
|
|
|
|
CmuReg = (__ccmu_reg_list_t *)IO_ADDRESS(AW_CCM_BASE);
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_exit
|
|
*
|
|
*Description: ccu exit for platform standby
|
|
*
|
|
*Arguments : none
|
|
*
|
|
*Return : result,
|
|
*
|
|
*Notes :
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_exit(void)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_core2hosc
|
|
*
|
|
* Description: switch core clock to 24M high osc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_core2hosc(void)
|
|
{
|
|
CmuReg_SysClkDiv_tmp.dwval = CmuReg->SysClkDiv.dwval;
|
|
CmuReg_SysClkDiv_tmp.bits.CpuClkSrc = 1;
|
|
CmuReg->SysClkDiv.dwval = CmuReg_SysClkDiv_tmp.dwval;
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_SUN8IW8P1
|
|
#else
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_ldoenable
|
|
*
|
|
* Description: enable LDO, ld01, hosc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
static void standby_cpus_clk_ldoenable(void)
|
|
{
|
|
//cpus power domain, offset 0x44, how to enable?
|
|
__u32 tmp;
|
|
tmp = readl(r_prcm + PLL_CTRL_REG1_OFFSET );
|
|
tmp &= ~(0xff000000);
|
|
tmp |= (0xa7000000);
|
|
writel(tmp, r_prcm + PLL_CTRL_REG1_OFFSET);
|
|
|
|
//enalbe ldo, ldo1,crystal
|
|
tmp = readl(r_prcm + PLL_CTRL_REG1_OFFSET );
|
|
tmp &= ~(0x00000007);
|
|
tmp |= (0x00000007);
|
|
writel(tmp, r_prcm + PLL_CTRL_REG1_OFFSET);
|
|
|
|
//disable change.
|
|
tmp = readl(r_prcm + PLL_CTRL_REG1_OFFSET );
|
|
tmp &= ~(0xff000000);
|
|
writel(tmp, r_prcm + PLL_CTRL_REG1_OFFSET);
|
|
|
|
return ;
|
|
}
|
|
#endif
|
|
|
|
__s32 standby_clk_ldoenable(void)
|
|
{
|
|
#ifdef CONFIG_ARCH_SUN8IW8P1
|
|
#else
|
|
standby_cpus_clk_ldoenable();
|
|
#endif
|
|
}
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_pll1enable
|
|
*
|
|
* Description: enable pll1.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
void standby_clk_pll1enable(void)
|
|
{
|
|
CmuReg_Pll1Ctl_tmp.dwval = CmuReg->Pll1Ctl.dwval;
|
|
CmuReg_Pll1Ctl_tmp.bits.PLLEn = 1;
|
|
CmuReg->Pll1Ctl.dwval = CmuReg_Pll1Ctl_tmp.dwval;
|
|
return ;
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_SUN9IW1
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_init
|
|
*
|
|
*Description: ccu init for platform standby
|
|
*
|
|
*Arguments : none
|
|
*
|
|
*Return : result,
|
|
*
|
|
*Notes :
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_init(void)
|
|
{
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_exit
|
|
*
|
|
*Description: ccu exit for platform standby
|
|
*
|
|
*Arguments : none
|
|
*
|
|
*Return : result,
|
|
*
|
|
*Notes :
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_exit(void)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_core2hosc
|
|
*
|
|
* Description: switch core clock to 24M high osc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_core2hosc(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_ldoenable
|
|
*
|
|
* Description: enable LDO, ld01, hosc.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
__s32 standby_clk_ldoenable(void)
|
|
{
|
|
|
|
return ;
|
|
}
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* standby_clk_pll1enable
|
|
*
|
|
* Description: enable pll1.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
*********************************************************************************************************
|
|
*/
|
|
void standby_clk_pll1enable(void)
|
|
{
|
|
return ;
|
|
}
|
|
#endif
|
|
|