632 lines
18 KiB
C
Executable File
632 lines
18 KiB
C
Executable File
/*
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*********************************************************************************************************
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* LINUX-KERNEL
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* AllWinner Linux Platform Develop Kits
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* Kernel Module
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*
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* (c) Copyright 2006-2011, kevin.z China
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* All Rights Reserved
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*
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* File : standby.c
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* By : kevin.z
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* Version : v1.0
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* Date : 2011-5-30 18:34
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* Descript: platform standby fucntion.
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* Update : date auther ver notes
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*********************************************************************************************************
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*/
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#include "standby_i.h"
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static void restore_ccu(void);
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static void backup_ccu(void);
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static void destory_mmu(void);
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static void restore_mmu(void);
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static void cache_count_init(void);
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static void cache_count_get(void);
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static void cache_count_output(void);
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extern char *__bss_start;
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extern char *__bss_end;
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extern char *__standby_start;
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extern char *__standby_end;
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static __u32 sp_backup;
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static __u32 ttb_0r_backup = 0;
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#define MMU_START (0xc0004000)
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#define MMU_END (0xc0007ffc) //reserve 0xffff0000 range.
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static __u32 mmu_backup[((MMU_END - MMU_START)>>2) + 1];
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static void standby(void);
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#ifdef CHECK_CACHE_TLB_MISS
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int d_cache_miss_start = 0;
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int d_tlb_miss_start = 0;
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int i_tlb_miss_start = 0;
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int i_cache_miss_start = 0;
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int d_cache_miss_end = 0;
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int d_tlb_miss_end = 0;
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int i_tlb_miss_end = 0;
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int i_cache_miss_end = 0;
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#endif
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static void standby(void);
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#ifdef CONFIG_SUNXI_ARISC
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static void arisc_standby(void);
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#else
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unsigned int dram_suspend_flag = 0;
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static __u8 dram_traning_area_back[DRAM_TRANING_SIZE];
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static void cpux_standby(void);
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static struct pll_factor_t orig_pll;
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static struct pll_factor_t local_pll;
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static struct standby_clk_div_t clk_div;
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static struct standby_clk_div_t tmp_clk_div;
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#endif
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/* parameter for standby, it will be transfered from sys_pwm module */
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struct aw_pm_info pm_info;
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unsigned int power_regu_tree[VCC_MAX_INDEX];
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struct normal_standby_para normal_standby_para_info;
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extended_standby_t extended_standby_para_info;
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/*
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*********************************************************************************************************
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* STANDBY MAIN PROCESS ENTRY
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*
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* Description: standby main process entry.
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*
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* Arguments : arg pointer to the parameter that transfered from sys_pwm module.
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*
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* Returns : none
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*
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* Note : the code&data may resident in cache.
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*********************************************************************************************************
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*/
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int standby_main(struct aw_pm_info *arg)
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{
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char *tmpPtr = (char *)&__bss_start;
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if(!arg){
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/* standby parameter is invalid */
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return -1;
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}
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/* flush data and instruction tlb, there is 32 items of data tlb and 32 items of instruction tlb,
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The TLB is normally allocated on a rotating basis. The oldest entry is always the next allocated */
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mem_flush_tlb();
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/* clear bss segment */
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do{*tmpPtr ++ = 0;}while(tmpPtr <= (char *)&__bss_end);
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/* save stack pointer registger, switch stack to sram */
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sp_backup = save_sp();
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save_mem_status(RESUME0_START | 0X02);
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/* copy standby parameter from dram */
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standby_memcpy(&pm_info, arg, sizeof(pm_info));
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standby_memcpy(&power_regu_tree, arg->pmu_arg.soc_power_tree, sizeof(power_regu_tree));
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/* preload tlb for standby */
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mem_preload_tlb();
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/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
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/* init module before dram enter selfrefresh */
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/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
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/*init perf counter for timing.*/
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init_perfcounters(1, 0); //need double check..
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standby_clk_init();
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mem_clk_init(1);
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#ifdef CONFIG_SUNXI_ARISC
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standby_arisc_init();
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#endif
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save_mem_status(RESUME0_START | 0X03);
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if(unlikely(pm_info.standby_para.debug_mask&PM_STANDBY_PRINT_STANDBY)){
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//don't need init serial ,depend kernel?
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serial_init_manager();
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printk("normal standby wakeup src config = 0x%x. \n", pm_info.standby_para.event);
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save_mem_status(RESUME0_START | 0X05);
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}
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/* copy extended standby info */
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if(NULL != (void *)pm_info.standby_para.pextended_standby){
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printk("use extended_standby cfg.\n");
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standby_memcpy(&extended_standby_para_info, (void *)(DRAM_EXTENDED_STANDBY_INFO_VA), sizeof(extended_standby_para_info));
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save_mem_status(RESUME0_START | 0X06);
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}
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save_mem_status(RESUME0_START | 0X07);
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/* init some system wake source */
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/* process standby */
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if(unlikely(pm_info.standby_para.debug_mask&PM_STANDBY_PRINT_CACHE_TLB_MISS)){
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cache_count_init();
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}
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save_mem_status(RESUME0_START | 0X08);
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standby();
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/* restore stack pointer register, switch stack back to dram */
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restore_sp(sp_backup);
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if(unlikely(pm_info.standby_para.debug_mask&PM_STANDBY_PRINT_STANDBY)){
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//restore serial clk & gpio config.
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serial_exit_manager();
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}
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#ifdef CONFIG_SUNXI_ARISC
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standby_arisc_exit();
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#endif
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/* report which wake source wakeup system */
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arg->standby_para.event = pm_info.standby_para.event;
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arg->standby_para.axp_event = pm_info.standby_para.axp_event;
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//enable_cache();
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save_mem_status(RESUME0_START | 0x0c);
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/* FIXME: seems the dram para have some err.
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* 1. the dram crc, in normal standby case, may have crc err.
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* such as the region: 0x40000000 -> 0x40010000
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* 2. need delay, such as: 5ms, before return to kernel.
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* 3. the bug is inexplicable, the summary as follow:
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* 3.1 rtc err code: may be 5004, or 5005, or 8000.
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* mean, the reason for cpu die is not sure.
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* 3.2 add delay here, bring good effect for cpu running.
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* but if we have an condition expresstion before delay,
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* it may have no effect.
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* so, memory attribute or bus behavior may have
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* contribute to this bug. to locate the real reason,
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* not use compile optiomize is better option.
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* 3.3 dram crc, in normal standby case, may have crc err.
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* 4. the right flow to correct this bug is:
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* 4.1 make sure dram crc is right. (right now, crc err occur.)
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* 4.2 make sure the sramA1 memory attribute is correct.
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* (right now, strongly-order is in use? conflict with trm.)
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*/
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if(likely(pm_info.standby_para.debug_mask&PM_STANDBY_TEST)){
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init_perfcounters(1, 0); //need double check..
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change_runtime_env();
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delay_ms(5);
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}
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return 0;
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}
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#ifndef CONFIG_SUNXI_ARISC
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/*
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*********************************************************************************************************
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* SYSTEM PWM ENTER STANDBY MODE
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*
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* Description: cpux enter standby mode.
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*
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* Arguments : none
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*
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* Returns : none;
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*********************************************************************************************************
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*/
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static void cpux_standby(void)
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{
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unsigned int dram_crc_bef = 0;
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unsigned int dram_crc_aft = 0;
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if((NULL != (void *)pm_info.standby_para.pextended_standby)){
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standby_set_dram_crc_paras(extended_standby_para_info.soc_dram_state.crc_en, \
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extended_standby_para_info.soc_dram_state.crc_start, \
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extended_standby_para_info.soc_dram_state.crc_len);
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dram_crc_bef = standby_dram_crc();
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}
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if((NULL != (void *)pm_info.standby_para.pextended_standby) && (0 == extended_standby_para_info.soc_dram_state.selfresh_flag)){
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//not enter selfresh according user define.
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printk("selfresh flag = 0. \n");
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}else{
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/*dram crc*/
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/* backup dram traning area */
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standby_memcpy((char *)dram_traning_area_back, (char *)DRAM_BASE_ADDR, DRAM_TRANING_SIZE);
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/* dram enter self-refresh flag */
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dram_suspend_flag = 1;
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dram_power_save_process();
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//mctl_self_refresh_entry();
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/* gating off dram clock */
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//standby_clk_dramgating(0);
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}
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/* backup cpu freq */
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standby_clk_get_pll_factor(&orig_pll);
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/* backup bus src */
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standby_clk_bus_src_backup();
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/*lower freq from 1008M to 408M*/
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local_pll.FactorN = 16;
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local_pll.FactorK = 0;
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local_pll.FactorM = 0;
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local_pll.FactorP = 0;
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standby_clk_set_pll_factor(&local_pll);
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change_runtime_env();
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delay_ms(10);
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/* switch cpu clock to HOSC, and disable pll */
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standby_clk_core2hosc();
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change_runtime_env();
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delay_us(1);
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if (extended_standby_para_info.pmu_id)
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{
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int i = 0;
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standby_twi_init(pm_info.pmu_arg.twi_port);
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for (i=0; i<VCC_MAX_INDEX; i++) {
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if ((0 < extended_standby_para_info.soc_pwr_dm_state.volt[i])&&
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(4200 > extended_standby_para_info.soc_pwr_dm_state.volt[i])) {
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standby_set_power(extended_standby_para_info.pmu_id, i,
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&power_regu_tree, extended_standby_para_info.soc_pwr_dm_state.volt[i]);
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}
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}
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}
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/* change ahb src to axi? losc?*/
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standby_clk_bus_src_set();
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standby_clk_getdiv(&clk_div);
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/* set clock division cpu:axi:ahb:apb = 2:2:2:1 */
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tmp_clk_div.axi_div = 0;
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tmp_clk_div.ahb_div = 0;
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tmp_clk_div.ahb_pre_div = 0;
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tmp_clk_div.apb_div = 0;
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tmp_clk_div.apb_pre_div = 0;
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standby_clk_setdiv(&tmp_clk_div);
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/* swtich apb2 to losc */
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standby_clk_apb2losc();
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change_runtime_env();
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//delay_ms(1);
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standby_clk_plldisable();
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/* switch cpu to 32k */
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standby_clk_core2losc();
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#if(ALLOW_DISABLE_HOSC)
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if( 1 == dram_suspend_flag){
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// disable HOSC, and disable LDO
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standby_clk_hoscdisable();
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standby_clk_ldodisable();
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}
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#endif
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/* cpu enter sleep, wait wakeup by interrupt */
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asm("WFI");
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#if(ALLOW_DISABLE_HOSC)
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if( 1 == dram_suspend_flag){
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/* enable LDO, enable HOSC */
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standby_clk_ldoenable();
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/* delay 1ms for power be stable */
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//3ms
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standby_delay_cycle(1);
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standby_clk_hoscenable();
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//3ms
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standby_delay_cycle(1);
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}
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#endif
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/* switch clock to hosc */
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standby_clk_core2hosc();
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/* swtich apb2 to hosc */
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standby_clk_apb2hosc();
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/* restore clock division */
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standby_clk_setdiv(&clk_div);
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/* check system wakeup event */
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pm_info.standby_para.event = 0;
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/* check system wakeup event */
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_EXTNMI)? 0:CPU0_WAKEUP_EXINT;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBOTG)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBEHCI0)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBEHCI1)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBEHCI2)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBOHCI0)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBOHCI1)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_USBOHCI2)? 0:CPU0_WAKEUP_USB;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_LRADC)? 0:CPU0_WAKEUP_KEY;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_IR0)? 0:CPU0_WAKEUP_IR;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_ALARM)? 0:CPU0_WAKEUP_ALARM;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_TIMER0)? 0:CPU0_WAKEUP_TIMEOUT;
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/* enable pll */
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standby_clk_pllenable();
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change_runtime_env();
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delay_ms(10);
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if (extended_standby_para_info.pmu_id)
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{
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/* restore voltage for exit standby */
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standby_recovery_power(extended_standby_para_info.pmu_id);
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standby_twi_exit();
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}
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standby_clk_bus_src_restore();
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/* switch cpu clock to core pll */
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standby_clk_core2pll();
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change_runtime_env();
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delay_ms(10);
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/*restore freq from 384 to 1008M*/
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standby_clk_set_pll_factor(&orig_pll);
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change_runtime_env();
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delay_ms(5);
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if( 1 == dram_suspend_flag){
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/* gating on dram clock */
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//standby_clk_dramgating(1);
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/* enable watch-dog to preserve dram training failed */
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//standby_tmr_enable_watchdog();
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/* restore dram */
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dram_power_up_process(0);
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//mctl_self_refresh_exit();
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//init_DRAM(&pm_info.dram_para);
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/* disable watch-dog */
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//standby_tmr_disable_watchdog();
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dram_suspend_flag = 0;
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/* restore dram traning area */
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standby_memcpy((char *)DRAM_BASE_ADDR, (char *)dram_traning_area_back, DRAM_TRANING_SIZE);
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}
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if((NULL != (void *)pm_info.standby_para.pextended_standby)){
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dram_crc_aft = standby_dram_crc();
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if(dram_crc_aft != dram_crc_bef){
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save_mem_status(RESUME0_START | 0X0b);
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printk("ERR: (dram_crc_bef = 0x%x) != (dram_crc_aft = 0x%x) \n", \
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dram_crc_bef, dram_crc_aft);
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while(1){};
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}else{
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printk("OK: (dram_crc_bef = 0x%x) == (dram_crc_aft = 0x%x) \n", \
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dram_crc_bef, dram_crc_aft);
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}
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}
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return;
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}
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#endif
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#ifdef CONFIG_SUNXI_ARISC
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/*
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*********************************************************************************************************
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* SYSTEM PWM ENTER STANDBY MODE
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*
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* Description: enter standby mode.
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*
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* Arguments : none
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*
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* Returns : none;
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*********************************************************************************************************
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*/
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static void arisc_standby(void)
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{
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/*backup clk freq and voltage*/
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backup_ccu();
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/*notify arisc enter normal standby*/
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normal_standby_para_info.event = pm_info.standby_para.axp_event;
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normal_standby_para_info.timeout = pm_info.standby_para.timeout;
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normal_standby_para_info.gpio_enable_bitmap = pm_info.standby_para.gpio_enable_bitmap;
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standby_arisc_standby_normal((&normal_standby_para_info));
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/* cpu enter sleep, wait wakeup by interrupt */
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asm("WFI");
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/*restore cpu0 ccu: enable hosc and change to 24M. */
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restore_ccu();
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/*query wakeup src*/
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standby_arisc_query_wakeup_src((unsigned long *)&(pm_info.standby_para.axp_event));
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save_mem_status(RESUME1_START | 0x01);
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/* enable watch-dog to prevent in case dram training failed */
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mem_tmr_enable_watchdog();
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save_mem_status(RESUME1_START | 0x02);
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/* notify for cpus to: restore cpus freq and volt, restore dram */
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standby_arisc_notify_restore(STANDBY_ARISC_ASYNC);
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save_mem_status(RESUME1_START | 0x03);
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/* check system wakeup event */
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pm_info.standby_para.event = 0;
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//actually, msg_box int will be clear by arisc-driver.
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_MSG_BOX)? 0:CPU0_WAKEUP_MSGBOX;
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pm_info.standby_para.event |= mem_query_int(INT_SOURCE_LRADC)? 0:CPU0_WAKEUP_KEY;
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/*check completion status: only after restore completion, access dram is allowed. */
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save_mem_status(RESUME1_START | 0x04);
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while(standby_arisc_check_restore_status()){
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if(unlikely(pm_info.standby_para.debug_mask&PM_STANDBY_PRINT_STANDBY)){
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printk("0xf1c20050 value: 0x%x. \n", *((volatile unsigned int *)0xf1c20050));
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printk("0xf1c20000 value: 0x%x. \n", *((volatile unsigned int *)0xf1c20000));
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}
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;
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}
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if(unlikely(pm_info.standby_para.debug_mask&PM_STANDBY_PRINT_CACHE_TLB_MISS)){
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cache_count_get();
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if(d_cache_miss_end || d_tlb_miss_end || i_tlb_miss_end || i_cache_miss_end){
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printk("=============================NOTICE====================================. \n");
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cache_count_output();
|
|
}else{
|
|
printk("no miss. \n");
|
|
//cache_count_output();
|
|
}
|
|
}
|
|
|
|
save_mem_status(RESUME1_START | 0x05);
|
|
/* disable watch-dog */
|
|
mem_tmr_disable_watchdog();
|
|
if(unlikely(pm_info.standby_para.debug_mask&PM_STANDBY_PRINT_STANDBY)){
|
|
printk("after mem_tmr_disable_watchdog. \n");
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void backup_ccu(void)
|
|
{
|
|
return;
|
|
}
|
|
|
|
/*change clk src to hosc*/
|
|
static void restore_ccu(void)
|
|
{
|
|
|
|
#if(ALLOW_DISABLE_HOSC)
|
|
/* enable LDO, ldo1, enable HOSC */
|
|
standby_clk_ldoenable();
|
|
standby_clk_pll1enable();
|
|
/* delay 10ms for power be stable */
|
|
standby_delay_cycle(1); //?ms
|
|
//switch to 24M src
|
|
standby_clk_core2hosc();
|
|
#endif
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* destory_mmu
|
|
*
|
|
* Description: to destory the mmu mapping, so, the tlb miss will result in an data/cache abort
|
|
* while not accessing dram.
|
|
* Arguments : none
|
|
*
|
|
* Returns : none;
|
|
*********************************************************************************************************
|
|
*/
|
|
static void destory_mmu(void)
|
|
{
|
|
__u32 ttb_1r = 0;
|
|
int i = 0;
|
|
volatile __u32 * p_mmu = (volatile __u32 *)MMU_START;
|
|
|
|
for(p_mmu = (volatile __u32 *)MMU_START; p_mmu < (volatile __u32 *)MMU_END; p_mmu++, i++)
|
|
{
|
|
mmu_backup[i] = *p_mmu;
|
|
*p_mmu = 0;
|
|
}
|
|
flush_dcache();
|
|
|
|
//u need to set ttbr0 to 0xc0004000?
|
|
//backup
|
|
asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r"(ttb_0r_backup));
|
|
//get ttbr1
|
|
asm volatile ("mrc p15, 0, %0, c2, c0, 1" : "=r"(ttb_1r));
|
|
//use ttbr1 to set ttbr0
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_1r));
|
|
asm volatile ("dsb");
|
|
asm volatile ("isb");
|
|
|
|
return;
|
|
}
|
|
|
|
static void restore_mmu(void)
|
|
{
|
|
volatile __u32 * p_mmu = (volatile __u32 *)MMU_START;
|
|
int i = 0;
|
|
|
|
//restore ttbr0
|
|
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_0r_backup));
|
|
asm volatile ("dsb");
|
|
asm volatile ("isb");
|
|
|
|
for(p_mmu = (volatile __u32 *)MMU_START; p_mmu < (volatile __u32 *)MMU_END; p_mmu++, i++)
|
|
{
|
|
*p_mmu = mmu_backup[i];
|
|
}
|
|
|
|
flush_dcache();
|
|
return;
|
|
}
|
|
|
|
#ifdef CHECK_CACHE_TLB_MISS
|
|
|
|
static void cache_count_init(void)
|
|
{
|
|
set_event_counter(D_CACHE_MISS);
|
|
set_event_counter(D_TLB_MISS);
|
|
set_event_counter(I_CACHE_MISS);
|
|
set_event_counter(I_TLB_MISS);
|
|
init_event_counter(1, 0);
|
|
d_cache_miss_start = get_event_counter(D_CACHE_MISS);
|
|
d_tlb_miss_start = get_event_counter(D_TLB_MISS);
|
|
i_tlb_miss_start = get_event_counter(I_TLB_MISS);
|
|
i_cache_miss_start = get_event_counter(I_CACHE_MISS);
|
|
|
|
return;
|
|
}
|
|
|
|
static void cache_count_get(void)
|
|
{
|
|
d_cache_miss_end = get_event_counter(D_CACHE_MISS);
|
|
d_tlb_miss_end = get_event_counter(D_TLB_MISS);
|
|
i_tlb_miss_end = get_event_counter(I_TLB_MISS);
|
|
i_cache_miss_end = get_event_counter(I_CACHE_MISS);
|
|
|
|
return;
|
|
}
|
|
|
|
static void cache_count_output(void)
|
|
{
|
|
printk("d_cache_miss_start = %d, d_cache_miss_end= %d. \n", d_cache_miss_start, d_cache_miss_end);
|
|
printk("d_tlb_miss_start = %d, d_tlb_miss_end= %d. \n", d_tlb_miss_start, d_tlb_miss_end);
|
|
printk("i_cache_miss_start = %d, i_cache_miss_end= %d. \n", i_cache_miss_start, i_cache_miss_end);
|
|
printk("i_tlb_miss_start = %d, i_tlb_miss_end= %d. \n", i_tlb_miss_start, i_tlb_miss_end);
|
|
|
|
return;
|
|
}
|
|
|
|
#else
|
|
static void cache_count_init(void)
|
|
{
|
|
return;
|
|
}
|
|
|
|
static void cache_count_get(void)
|
|
{
|
|
return;
|
|
}
|
|
|
|
static void cache_count_output(void)
|
|
{
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
|
|
/*
|
|
*********************************************************************************************************
|
|
* SYSTEM PWM ENTER STANDBY MODE
|
|
*
|
|
* Description: cpux enter standby mode.
|
|
*
|
|
* Arguments : none
|
|
*
|
|
* Returns : none;
|
|
*********************************************************************************************************
|
|
*/
|
|
static void standby(void)
|
|
{
|
|
#ifdef CONFIG_SUNXI_ARISC
|
|
arisc_standby();
|
|
#else
|
|
cpux_standby();
|
|
#endif
|
|
}
|
|
|