720 lines
15 KiB
C
Executable File
720 lines
15 KiB
C
Executable File
/*
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* lixiang <lixiang@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/rsb.h>
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#include <asm/arch/platform.h>
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#include <sunxi_board.h>
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#if 0
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struct sunxi_rsb_slave_set
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{
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u8 *m_slave_name;
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u32 m_slave_addr;
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u32 m_rtaddr;
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u32 chip_id;
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};
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#define SUNXI_RSB_SLAVE_MAX 2
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#undef rsb_reg_writel
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#undef rsb_reg_readl
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#define rsb_reg_writel writel
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#define rsb_reg_readl readl
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#undef rsb_printk
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#define rsb_printk(format,arg...)
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static struct rsb_info rsbc = {1, 1, 1};
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static struct sunxi_rsb_slave_set rsb_slave[SUNXI_RSB_SLAVE_MAX]={{NULL, 1, 1, 1}};
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static int sunxi_rsb_rtsaddr[16] = {0x2d, 0x3a, 0x3e, 0x59, 0x63, 0x74, 0x8b, 0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff};
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#if (defined FPGA_PLATFORM)
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static void rsb_cfg_io(void)
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{
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uint reg,val;
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//PH14,PH15 cfg 3
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reg = SUNXI_PIO_BASE+0x100;
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val = rsb_reg_readl(reg) & (~(0xff<<24));
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val |= (0x33<<24);
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rsb_reg_writel(val,reg);
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//PH14,PH15 pull up 1
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reg = SUNXI_PIO_BASE+0x118;
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val = rsb_reg_readl(reg) & (~(0xf<<28));
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val |= (0x5<<28);
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rsb_reg_writel(val,reg);
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//PH14,PH15 drv 2
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reg = SUNXI_PIO_BASE+0x110;
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val = rsb_reg_readl(reg) & (~(0xf<<28));
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val |= (0xa<<28);
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rsb_reg_writel(val,reg);
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}
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#else
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static void rsb_cfg_io(void)
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{
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#if (defined(CONFIG_ARCH_SUN50IW1P1) )
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uint reg,val;
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//if r_pio gating not open
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reg = SUNXI_RPRCM_BASE + 0x28;
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val = rsb_reg_readl(reg);
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if( !(rsb_reg_readl(reg)&0x1))
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{
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val |= 0x1; //open r_pio
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rsb_reg_writel(val,reg);
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}
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//PL0,PL1 cfg 2
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reg = SUNXI_RPIO_BASE;
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val = rsb_reg_readl(reg) & (~0xff);
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val |= 0x22;
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rsb_reg_writel(val,reg);
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//PL0,PL1 pull up 1
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reg = SUNXI_RPIO_BASE+0x1c;
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val = rsb_reg_readl(reg) & (~0xf);
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val |= 0x5;
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rsb_reg_writel(val,reg);
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//PL0,PL1 drv 2
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reg = SUNXI_RPIO_BASE+0x14;
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val = rsb_reg_readl(reg) & (~0xf);
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val |= 0xa;
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rsb_reg_writel(val,reg);
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#endif
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}
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#endif
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static void rsb_module_reset(void)
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{
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// r_prcm_module_reset(R_RSB_CKID);
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rsb_reg_writel(rsb_reg_readl(SUNXI_RPRCM_BASE + 0xb0)& ~(0x1U << 3),SUNXI_RPRCM_BASE + 0xb0);
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rsb_reg_writel(rsb_reg_readl(SUNXI_RPRCM_BASE + 0xb0)|(0x1U << 3),SUNXI_RPRCM_BASE + 0xb0);
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}
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static void rsb_clock_enable(void)
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{
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// r_prcm_clock_enable(R_RSB_CKID);
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rsb_reg_writel(rsb_reg_readl(SUNXI_RPRCM_BASE + 0x28)|(0x1U << 3),SUNXI_RPRCM_BASE + 0x28);
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}
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static void rsb_set_clk(u32 sck)
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{
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u32 src_clk = 0;
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u32 div = 0;
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u32 cd_odly = 0;
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u32 rval = 0;
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src_clk = 24000000;
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div = src_clk/sck/2;
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if(0==div){
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div = 1;
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rsb_printk("Source clock is too low\n");
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}else if(div>256){
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div = 256;
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rsb_printk("Source clock is too high\n");
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}
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div--;
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cd_odly = div >> 1;
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//cd_odly = 1;
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if(!cd_odly)
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cd_odly = 1;
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rval = div | (cd_odly << 8);
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rsb_reg_writel(rval, RSB_REG_CCR);
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}
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/* RSB function */
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#ifdef RSB_USE_INT
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static void rsb_irq_handler(void)
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{
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u32 istat = rsb_reg_readl(RSB_REG_STAT);
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if(istat & RSB_LBSY_INT){
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rsbc.rsb_load_busy = 1;
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}
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if (istat & RSB_TERR_INT) {
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rsbc.rsb_flag = (istat >> 8) & 0xffff;
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}
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if (istat & RSB_TOVER_INT) {
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rsbc.rsb_busy = 0;
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}
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rsb_reg_writel(istat, RSB_REG_STAT);
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}
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#endif
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static void rsb_init(void)
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{
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rsbc.rsb_flag = 0;
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rsbc.rsb_busy = 0;
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rsbc.rsb_load_busy = 0;
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rsb_cfg_io();
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rsb_module_reset();
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rsb_clock_enable();
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rsb_reg_writel(RSB_SOFT_RST, RSB_REG_CTRL);
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rsb_set_clk(RSB_SCK);
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#ifdef RSB_USE_INT
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rsb_reg_writel(RSB_GLB_INTEN, RSB_REG_CTRL);
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rsb_reg_writel(RSB_TOVER_INT|RSB_TERR_INT|RSB_LBSY_INT, RSB_REG_INTE);
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irq_request(GIC_SRC_RRSB, rsb_irq_handler);
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irq_enable(GIC_SRC_RRSB);
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#endif
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}
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//
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static s32 rsb_send_initseq(u32 slave_addr, u32 reg, u32 data)
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{
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while(rsb_reg_readl(RSB_REG_STAT)&(RSB_LBSY_INT|RSB_TERR_INT|RSB_TOVER_INT))
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{
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rsb_printk("status err\n");
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}
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rsbc.rsb_busy = 1;
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rsbc.rsb_flag = 0;
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rsbc.rsb_load_busy = 0;
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rsb_reg_writel(RSB_PMU_INIT|(slave_addr << 1) \
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|(reg << PMU_MOD_REG_ADDR_SHIFT) \
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|(data << PMU_INIT_DAT_SHIFT), \
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RSB_REG_PMCR);
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while(rsb_reg_readl(RSB_REG_PMCR) & RSB_PMU_INIT){
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}
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while(rsbc.rsb_busy){
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#ifndef RSB_USE_INT
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//istat will be optimize?
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u32 istat = rsb_reg_readl(RSB_REG_STAT);
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if(istat & RSB_LBSY_INT){
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rsbc.rsb_load_busy = 1;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TERR_INT) {
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rsbc.rsb_flag = (istat >> 8) & 0xffff;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TOVER_INT) {
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rsbc.rsb_busy = 0;
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rsb_reg_writel(istat, RSB_REG_STAT);
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}
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#endif
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}
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if(rsbc.rsb_load_busy){
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rsb_printk("Load busy\n");
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return RET_FAIL;
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}
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if (rsbc.rsb_flag) {
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rsb_printk( "rsb write failed, flag 0x%x:%s%s%s%s%s !!\n",
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rsbc.rsb_flag,
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rsbc.rsb_flag & ERR_TRANS_1ST_BYTE ? " 1STE " : "",
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rsbc.rsb_flag & ERR_TRANS_2ND_BYTE ? " 2NDE " : "",
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rsbc.rsb_flag & ERR_TRANS_3RD_BYTE ? " 3RDE " : "",
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rsbc.rsb_flag & ERR_TRANS_4TH_BYTE ? " 4THE " : "",
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rsbc.rsb_flag & ERR_TRANS_RT_NO_ACK ? " NOACK " : ""
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);
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return -rsbc.rsb_flag;
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}
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return 0;
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}
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static s32 set_run_time_addr(u32 saddr,u32 rtsaddr)
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{
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while(rsb_reg_readl(RSB_REG_STAT)&(RSB_LBSY_INT|RSB_TERR_INT|RSB_TOVER_INT))
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{
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rsb_printk("status err\n");
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}
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rsbc.rsb_busy = 1;
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rsbc.rsb_flag = 0;
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rsbc.rsb_load_busy = 0;
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rsb_reg_writel((saddr<<RSB_SADDR_SHIFT) \
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|(rtsaddr<<RSB_RTSADDR_SHIFT), \
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RSB_REG_SADDR);
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rsb_reg_writel(RSB_CMD_SET_RTSADDR,RSB_REG_CMD);
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rsb_reg_writel(rsb_reg_readl(RSB_REG_CTRL)|RSB_START_TRANS, RSB_REG_CTRL);
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while(rsbc.rsb_busy){
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#ifndef RSB_USE_INT
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//istat will be optimize?
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u32 istat = rsb_reg_readl(RSB_REG_STAT);
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if(istat & RSB_LBSY_INT){
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rsbc.rsb_load_busy = 1;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TERR_INT) {
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rsbc.rsb_flag = (istat >> 8) & 0xffff;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TOVER_INT) {
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rsbc.rsb_busy = 0;
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rsb_reg_writel(istat, RSB_REG_STAT);
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}
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#endif
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}
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if(rsbc.rsb_load_busy){
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rsb_printk("Load busy\n");
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return RET_FAIL;
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}
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if (rsbc.rsb_flag) {
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rsb_printk( "rsb set run time address failed, flag 0x%x:%s%s%s%s%s !!\n",
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rsbc.rsb_flag,
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rsbc.rsb_flag & ERR_TRANS_1ST_BYTE ? " 1STE " : "",
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rsbc.rsb_flag & ERR_TRANS_2ND_BYTE ? " 2NDE " : "",
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rsbc.rsb_flag & ERR_TRANS_3RD_BYTE ? " 3RDE " : "",
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rsbc.rsb_flag & ERR_TRANS_4TH_BYTE ? " 4THE " : "",
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rsbc.rsb_flag & ERR_TRANS_RT_NO_ACK ? " NOACK " : ""
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);
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return -rsbc.rsb_flag;
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}
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return 0;
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}
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//s32 rsb_write(u32 rtsaddr,struct rsb_ad *ad, u32 len)
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static s32 rsb_write(u32 rtsaddr,u32 daddr, u8 *data,u32 len)
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{
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u32 cmd = 0;
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u32 dat = 0;
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s32 i = 0;
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if (len > 4 || len==0||len==3) {
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rsb_printk("error length %d\n", len);
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return -1;
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}
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if(NULL==data){
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rsb_printk("data should not be NULL\n");
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return -1;
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}
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while(rsb_reg_readl(RSB_REG_STAT)&(RSB_LBSY_INT|RSB_TERR_INT|RSB_TOVER_INT))
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{
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rsb_printk("status err\n");
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}
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rsbc.rsb_flag = 0;
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rsbc.rsb_busy = 1;
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rsbc.rsb_load_busy = 0;
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rsb_reg_writel(rtsaddr<<RSB_RTSADDR_SHIFT,RSB_REG_SADDR);
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rsb_reg_writel(daddr, RSB_REG_DADDR0);
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for(i=0;i<len;i++){
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dat |= data[i]<<(i*8);
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}
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rsb_reg_writel(dat, RSB_REG_DATA0);
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//rsb_reg_writel(*((u32*)data), RSB_REG_DATA0);
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//rsb_reg_writew(*((u16*)data), RSB_REG_DATA0);
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// rsb_reg_writel((len-1)|RSB_WRITE_FLAG, RSB_REG_DLEN);
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switch(len) {
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case 1:
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cmd = RSB_CMD_BYTE_WRITE;
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break;
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case 2:
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cmd = RSB_CMD_HWORD_WRITE;
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break;
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case 4:
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cmd = RSB_CMD_WORD_WRITE;
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break;
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default:
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break;
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}
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rsb_reg_writel(cmd,RSB_REG_CMD);
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rsb_reg_writel(rsb_reg_readl(RSB_REG_CTRL)|RSB_START_TRANS, RSB_REG_CTRL);
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while(rsbc.rsb_busy){
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#ifndef RSB_USE_INT
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//istat will be optimize?
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u32 istat = rsb_reg_readl(RSB_REG_STAT);
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if(istat & RSB_LBSY_INT){
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rsbc.rsb_load_busy = 1;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TERR_INT) {
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rsbc.rsb_flag = (istat >> 8) & 0xffff;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TOVER_INT) {
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rsbc.rsb_busy = 0;
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rsb_reg_writel(istat, RSB_REG_STAT);
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}
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#endif
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}
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if(rsbc.rsb_load_busy){
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rsb_printk("Load busy\n");
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return RET_FAIL;
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}
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if (rsbc.rsb_flag) {
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rsb_printk( "rsb write failed, flag 0x%x:%s%s%s%s%s !!\n",
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rsbc.rsb_flag,
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rsbc.rsb_flag & ERR_TRANS_1ST_BYTE ? " 1STE " : "",
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rsbc.rsb_flag & ERR_TRANS_2ND_BYTE ? " 2NDE " : "",
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rsbc.rsb_flag & ERR_TRANS_3RD_BYTE ? " 3RDE " : "",
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rsbc.rsb_flag & ERR_TRANS_4TH_BYTE ? " 4THE " : "",
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rsbc.rsb_flag & ERR_TRANS_RT_NO_ACK ? " NOACK " : ""
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);
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return -rsbc.rsb_flag;
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}
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return 0;
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}
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//s32 rsb_read(u32 rtsaddr,struct rsb_ad *ad, u32 len)
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static s32 rsb_read(u32 rtsaddr,u32 daddr, u8 *data, u32 len)
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{
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u32 cmd = 0;
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u32 dat = 0;
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s32 i = 0;
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if (len > 4 || len==0||len==3) {
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rsb_printk("error length %d\n", len);
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return -1;
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}
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if(NULL==data){
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rsb_printk("data should not be NULL\n");
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return -1;
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}
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while(rsb_reg_readl(RSB_REG_STAT)&(RSB_LBSY_INT|RSB_TERR_INT|RSB_TOVER_INT))
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{
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rsb_printk("status err\n");
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}
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rsbc.rsb_flag = 0;
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rsbc.rsb_busy = 1;
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rsbc.rsb_load_busy = 0;
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rsb_reg_writel(rtsaddr<<RSB_RTSADDR_SHIFT,RSB_REG_SADDR);
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rsb_reg_writel(daddr, RSB_REG_DADDR0);
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// rsb_reg_writel((len-1)|RSB_READ_FLAG, RSB_REG_DLEN);
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switch(len){
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case 1:
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cmd = RSB_CMD_BYTE_READ;
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break;
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case 2:
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cmd = RSB_CMD_HWORD_READ;
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break;
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case 4:
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cmd = RSB_CMD_WORD_READ;
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break;
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default:
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break;
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}
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rsb_reg_writel(cmd,RSB_REG_CMD);
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rsb_reg_writel(rsb_reg_readl(RSB_REG_CTRL)|RSB_START_TRANS, RSB_REG_CTRL);
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while(rsbc.rsb_busy){
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#ifndef RSB_USE_INT
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//istat will be optimize?
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u32 istat = rsb_reg_readl(RSB_REG_STAT);
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if(istat & RSB_LBSY_INT){
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rsbc.rsb_load_busy = 1;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TERR_INT) {
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rsbc.rsb_flag = (istat >> 8) & 0xffff;
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rsb_reg_writel(istat, RSB_REG_STAT);
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break;
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}
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if (istat & RSB_TOVER_INT) {
|
|
rsbc.rsb_busy = 0;
|
|
rsb_reg_writel(istat, RSB_REG_STAT);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
if(rsbc.rsb_load_busy){
|
|
rsb_printk("Load busy\n");
|
|
return RET_FAIL;
|
|
}
|
|
|
|
if (rsbc.rsb_flag) {
|
|
rsb_printk( "rsb read failed, flag 0x%x:%s%s%s%s%s !!\n",
|
|
rsbc.rsb_flag,
|
|
rsbc.rsb_flag & ERR_TRANS_1ST_BYTE ? " 1STE " : "",
|
|
rsbc.rsb_flag & ERR_TRANS_2ND_BYTE ? " 2NDE " : "",
|
|
rsbc.rsb_flag & ERR_TRANS_3RD_BYTE ? " 3RDE " : "",
|
|
rsbc.rsb_flag & ERR_TRANS_4TH_BYTE ? " 4THE " : "",
|
|
rsbc.rsb_flag & ERR_TRANS_RT_NO_ACK ? " NOACK " : ""
|
|
);
|
|
return -rsbc.rsb_flag;
|
|
}
|
|
|
|
//*((u32*)data) = rsb_reg_readl(RSB_REG_DATA0);
|
|
//*((u16*)data) = rsb_reg_readw(RSB_REG_DATA0);
|
|
|
|
dat = rsb_reg_readl(RSB_REG_DATA0);
|
|
for(i=0;i<len;i++){
|
|
data[i]=(dat>>(i*8))&0xff;
|
|
}
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
#define CD_HIGH 0x3
|
|
#define CD_LOW 0x1
|
|
#define CK_HIGH (0x3<<2)
|
|
#define CK_LOW (0x1<<2)
|
|
|
|
|
|
//static void rsb_set_ck_level(u32 level)
|
|
//{
|
|
// u32 rval = rsb_reg_readb(RSB_REG_LCR);
|
|
//
|
|
// rval &= ~(CK_HIGH);
|
|
// if (level)
|
|
// rsb_reg_writeb(rval | CK_HIGH, RSB_REG_LCR);
|
|
// else
|
|
// rsb_reg_writeb(rval | CK_LOW, RSB_REG_LCR);
|
|
//}
|
|
|
|
//static void rsb_set_cd_level(u32 level)
|
|
//{
|
|
// u32 rval = rsb_reg_readb(RSB_REG_LCR);
|
|
//
|
|
// rval &= ~(CD_HIGH);
|
|
// if (level)
|
|
// rsb_reg_writeb(rval | CD_HIGH, RSB_REG_LCR);
|
|
// else
|
|
// rsb_reg_writeb(rval | CD_LOW, RSB_REG_LCR);
|
|
//}
|
|
|
|
//static u32 rsb_get_ck_level(void)
|
|
//{
|
|
// return 0x1 & (rsb_reg_readb(RSB_REG_LCR) >> 5);
|
|
//}
|
|
//
|
|
//static u32 rsb_get_cd_level(void)
|
|
//{
|
|
// return 0x1 & (rsb_reg_readb(RSB_REG_LCR) >> 4);
|
|
//}
|
|
|
|
|
|
s32 sunxi_rsb_init(u32 slave_id)
|
|
{
|
|
int ret;
|
|
memset(rsb_slave, 0, SUNXI_RSB_SLAVE_MAX * sizeof(struct sunxi_rsb_slave_set));
|
|
rsb_init();
|
|
// rsb clk = 400Khz
|
|
rsb_set_clk(400000);
|
|
ret = rsb_send_initseq(0x00, 0x3e, 0x7c);
|
|
// rsb clk = 3Mhz
|
|
rsb_set_clk(RSB_SCK);
|
|
printf("rsb_send_initseq: rsb clk 400Khz -> 3Mhz\n");
|
|
return ret;
|
|
}
|
|
|
|
s32 sunxi_rsb_config(u32 slave_id, u32 rsb_addr)
|
|
{
|
|
u32 rtaddr = 0;
|
|
int i;
|
|
|
|
for(i=0;i<SUNXI_RSB_SLAVE_MAX;i++)
|
|
{
|
|
if(!rsb_slave[i].m_slave_addr)
|
|
{
|
|
rsb_slave[i].m_slave_addr = rsb_addr;
|
|
rsb_slave[i].m_rtaddr = sunxi_rsb_rtsaddr[i];
|
|
rsb_slave[i].chip_id = slave_id;
|
|
|
|
rtaddr = sunxi_rsb_rtsaddr[i];
|
|
|
|
return set_run_time_addr(rsb_addr, rtaddr);
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
s32 sunxi_rsb_exit(u32 slave_id)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
s32 sunxi_rsb_read(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
u32 rtaddr = 0;
|
|
u32 tmp_slave_id;
|
|
int i;
|
|
|
|
for(i=0;;)
|
|
{
|
|
tmp_slave_id = rsb_slave[i].chip_id;
|
|
if(tmp_slave_id == slave_id)
|
|
{
|
|
break;
|
|
}
|
|
else if (!tmp_slave_id)
|
|
{
|
|
rsb_printk("sunxi_rsb_read err: bad id\n");
|
|
return -1;
|
|
}
|
|
i++;
|
|
}
|
|
|
|
rtaddr = rsb_slave[i].m_rtaddr;
|
|
|
|
return rsb_read(rtaddr,daddr, data,len);
|
|
}
|
|
|
|
|
|
s32 sunxi_rsb_write(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
u32 rtaddr = 0;
|
|
u32 tmp_slave_id;
|
|
int i;
|
|
|
|
for(i=0;;)
|
|
{
|
|
tmp_slave_id = rsb_slave[i].chip_id;
|
|
if(tmp_slave_id == slave_id)
|
|
{
|
|
break;
|
|
}
|
|
else if(!tmp_slave_id) {
|
|
rsb_printk("sunxi_rsb_write err: bad id\n");
|
|
return -1;
|
|
}
|
|
i++;
|
|
}
|
|
|
|
rtaddr = rsb_slave[i].m_rtaddr;
|
|
|
|
return rsb_write(rtaddr,daddr, data,len);
|
|
}
|
|
|
|
int axp_i2c_read(unsigned char chip, unsigned char addr, unsigned char *buffer)
|
|
{
|
|
|
|
return sunxi_rsb_read(chip, addr, buffer, 1);
|
|
|
|
}
|
|
|
|
int axp_i2c_write(unsigned char chip, unsigned char addr, unsigned char data)
|
|
{
|
|
return sunxi_rsb_write(chip, addr, &data, 1);
|
|
|
|
}
|
|
#endif
|
|
|
|
static s32 sunxi_rsb_io_null(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
s32 (* sunxi_rsb_read_pt)(u32 slave_id, u32 daddr, u8 *data, u32 len) = sunxi_rsb_io_null;
|
|
s32 (* sunxi_rsb_write_pt)(u32 slave_id, u32 daddr, u8 *data, u32 len) = sunxi_rsb_io_null;
|
|
|
|
|
|
|
|
|
|
static s32 sunxi_rsb_read_secos(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
int ret = 0;
|
|
ret = (u8)(arm_svc_arisc_read_pmu((ulong)daddr));
|
|
if(ret < 0 )
|
|
{
|
|
return -1;
|
|
}
|
|
*data = ret&0xff;
|
|
return 0;
|
|
}
|
|
|
|
static s32 sunxi_rsb_write_secos(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
return arm_svc_arisc_write_pmu((ulong)daddr,(u32)(*data));
|
|
}
|
|
|
|
|
|
|
|
int sunxi_rsb_read(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
return sunxi_rsb_read_pt(slave_id, daddr, data, len);
|
|
}
|
|
|
|
int sunxi_rsb_write(u32 slave_id, u32 daddr, u8 *data, u32 len)
|
|
{
|
|
return sunxi_rsb_write_pt(slave_id, daddr, data, len);
|
|
}
|
|
|
|
int sunxi_rsb_config(u32 slave_id, u32 rsb_addr)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
|
|
s32 sunxi_rsb_init(u32 slave_id)
|
|
{
|
|
if(sunxi_probe_secure_monitor())
|
|
{
|
|
printf("rsb: secure monitor exist\n");
|
|
sunxi_rsb_read_pt = sunxi_rsb_read_secos;
|
|
sunxi_rsb_write_pt = sunxi_rsb_write_secos;
|
|
}
|
|
else
|
|
{
|
|
printf("without secure monitor\n");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
|