230 lines
6.2 KiB
C
Executable File
230 lines
6.2 KiB
C
Executable File
/* arch/arm/mach-sunxi/pm/pm_debug_secure.c
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* Copyright (C) 2013-2014 allwinner.
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*
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* By : huangshr
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* Date : 2014-10-20
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*/
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#include <linux/ctype.h>
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#include <linux/module.h>
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#ifdef CONFIG_SUNXI_TRUSTZONE
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#include <linux/secure/te_protocol.h>
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#endif
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#include <asm/firmware.h>
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#include <mach/sunxi-smc.h>
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#include "pm_debug.h"
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#include "mem_hwspinlock.h"
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#if defined(CONFIG_ARCH_SUN8IW6P1) || defined(CONFIG_ARCH_SUN9IW1P1)
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static volatile __r_prcm_pio_pad_hold *pm_secure_status_reg;
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static volatile __r_prcm_pio_pad_hold *pm_secure_status_reg_pa;
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#ifndef CONFIG_SUNXI_TRUSTZONE
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static __r_prcm_pio_pad_hold pm_secure_status_reg_tmp;
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static __r_prcm_pio_pad_hold pm_secure_status_reg_pa_tmp;
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#endif //for define status reg tmp
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void pm_secure_mem_status_init(void)
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{
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pm_secure_status_reg = (volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG);
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pm_secure_status_reg_pa = (volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG_PA);
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hwspinlock_init(1);
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}
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void pm_secure_mem_status_init_nommu(void)
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{
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pm_secure_status_reg = (volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG);
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pm_secure_status_reg_pa = (volatile __r_prcm_pio_pad_hold *)(STANDBY_STATUS_REG_PA);
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hwspinlock_init(0);
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}
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void pm_secure_mem_status_clear(void)
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{
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#ifndef CONFIG_SUNXI_TRUSTZONE
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int i = 1;
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pm_secure_status_reg_tmp.dwval = (*pm_secure_status_reg).dwval;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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while(i < STANDBY_STATUS_REG_NUM){
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pm_secure_status_reg_tmp.bits.reg_sel = i;
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pm_secure_status_reg_tmp.bits.data_wr = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 1;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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i++;
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}
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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#else
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call_firmware_op(set_standby_status,TEE_SMC_PLAFORM_OPERATION, TE_SMC_STANDBY_STATUS_CLEAR, (u32)pm_secure_status_reg, 0);
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#endif
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}
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void pm_secure_mem_status_exit(void)
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{
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return ;
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}
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void save_pm_secure_mem_status(volatile __u32 val)
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{
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#ifndef CONFIG_SUNXI_TRUSTZONE
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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pm_secure_status_reg_tmp.bits.reg_sel = 1;
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pm_secure_status_reg_tmp.bits.data_wr = val;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 1;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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asm volatile ("dsb");
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asm volatile ("isb");
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return;
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#else
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call_firmware_op(set_standby_status,TEE_SMC_PLAFORM_OPERATION, TE_SMC_STANDBY_STATUS_SET, (u32)pm_secure_status_reg, val);
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return;
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#endif
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}
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__u32 get_pm_secure_mem_status(void)
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{
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int val = 0;
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#ifndef CONFIG_SUNXI_TRUSTZONE
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pm_secure_status_reg_tmp.bits.reg_sel = 1;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.dwval = (*pm_secure_status_reg).dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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val = pm_secure_status_reg_tmp.bits.data_rd;
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return (val);
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#else
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val = call_firmware_op(set_standby_status,TEE_SMC_PLAFORM_OPERATION, TE_SMC_STANDBY_STATUS_GET, (u32)pm_secure_status_reg, 1);
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return (val);
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#endif
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}
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void show_pm_secure_mem_status(void)
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{
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int i = 1;
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int val = 0;
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#ifndef CONFIG_SUNXI_TRUSTZONE
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while(i < STANDBY_STATUS_REG_NUM) {
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pm_secure_status_reg_tmp.bits.reg_sel = i;
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if (!hwspin_lock_timeout(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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(*pm_secure_status_reg).dwval = pm_secure_status_reg_tmp.dwval;
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pm_secure_status_reg_tmp.dwval = (*pm_secure_status_reg).dwval;
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hwspin_unlock(MEM_RTC_REG_HWSPINLOCK);
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}
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val = pm_secure_status_reg_tmp.bits.data_rd;
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printk("addr %x, value = %x. \n", (i), val);
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i++;
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}
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#else
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while(i < STANDBY_STATUS_REG_NUM){
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val = call_firmware_op(set_standby_status,TEE_SMC_PLAFORM_OPERATION, TE_SMC_STANDBY_STATUS_GET, (u32)pm_secure_status_reg, i);
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printk("addr %x, value = %x. \n", (i), val);
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i++;
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}
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#endif
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}
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void save_pm_secure_mem_status_nommu(volatile __u32 val)
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{
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#ifndef CONFIG_SUNXI_TRUSTZONE
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if (!hwspin_lock_timeout_nommu(MEM_RTC_REG_HWSPINLOCK, 20000)) {
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pm_secure_status_reg_pa_tmp.bits.reg_sel = 1;
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pm_secure_status_reg_pa_tmp.bits.data_wr = val;
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(*pm_secure_status_reg_pa).dwval = pm_secure_status_reg_pa_tmp.dwval;
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pm_secure_status_reg_pa_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg_pa).dwval = pm_secure_status_reg_pa_tmp.dwval;
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pm_secure_status_reg_pa_tmp.bits.wr_pulse = 1;
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(*pm_secure_status_reg_pa).dwval = pm_secure_status_reg_pa_tmp.dwval;
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pm_secure_status_reg_pa_tmp.bits.wr_pulse = 0;
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(*pm_secure_status_reg_pa).dwval = pm_secure_status_reg_pa_tmp.dwval;
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hwspin_unlock_nommu(MEM_RTC_REG_HWSPINLOCK);
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}
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return;
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#else
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call_firmware_op(set_standby_status,TEE_SMC_PLAFORM_OPERATION, TE_SMC_STANDBY_STATUS_SET, (u32)pm_secure_status_reg_pa, val);
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#endif
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}
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#elif defined(CONFIG_ARCH_SUN8IW1P1) || \
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defined(CONFIG_ARCH_SUN8IW3P1) || \
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defined(CONFIG_ARCH_SUN8IW5P1) || \
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defined(CONFIG_ARCH_SUN8IW7P1) || \
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defined(CONFIG_ARCH_SUN8IW8P1) || \
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defined(CONFIG_ARCH_SUN8IW9P1)
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void pm_secure_mem_status_init(void)
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{
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mem_status_init();
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return;
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}
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void pm_secure_mem_status_init_nommu(void)
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{
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mem_status_init_nommu();
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return ;
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}
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void pm_secure_mem_status_clear(void)
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{
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mem_status_clear();
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return;
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}
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void pm_secure_mem_status_exit(void)
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{
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mem_status_exit();
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return ;
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}
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void save_pm_secure_mem_status(volatile __u32 val)
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{
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save_mem_status(val);
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return;
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}
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__u32 get_pm_secure_mem_status(void)
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{
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u32 val;
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val = get_mem_status();
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return val;
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}
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void show_pm_secure_mem_status(void)
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{
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show_mem_status();
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}
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void save_pm_secure_mem_status_nommu(volatile __u32 val)
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{
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save_mem_status_nommu(val);
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return;
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}
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void save_cpux_pm_secure_mem_status_nommu(volatile __u32 val)
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{
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save_cpux_mem_status_nommu(val);
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return;
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}
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#endif
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