203 lines
6.6 KiB
ArmAsm
203 lines
6.6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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.globl bl31_entrypoint
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/* -----------------------------------------------------
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* bl31_entrypoint() is the cold boot entrypoint,
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* executed only by the primary cpu.
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* -----------------------------------------------------
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*/
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func bl31_entrypoint
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/* ---------------------------------------------------------------
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* Preceding bootloader has populated x0 with a pointer to a
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* 'bl31_params' structure & x1 with a pointer to platform
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* specific structure
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* ---------------------------------------------------------------
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*/
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#if !RESET_TO_BL31
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/*
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*AA32 warmreset to AA64, the high 32bit in reg R0,R1 is unpredictable
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*/
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/*mov x20, x0*/
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/*mov x21, x1*/
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mov x20, 0
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mov x21, 0
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mov w20, w0
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mov w21, w1
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#else
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/* ---------------------------------------------
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* Set the CPU endianness before doing anything
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* that might involve memory reads or writes.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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/* -----------------------------------------------------
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* Perform any processor specific actions upon reset
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* e.g. cache, tlb invalidations etc. Override the
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* Boot ROM(BL0) programming sequence
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* -----------------------------------------------------
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*/
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bl reset_handler
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#endif
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------
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* Initialise cpu_data early to enable crash
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* reporting to have access to crash stack.
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* Since crash reporting depends on cpu_data to
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* report the unhandled exception, not
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* doing so can lead to recursive exceptions due
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* to a NULL TPIDR_EL3
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* ---------------------------------------------
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*/
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bl init_cpu_data_ptr
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/* ---------------------------------------------
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* Set the exception vector.
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* ---------------------------------------------
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*/
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adr x1, runtime_exceptions
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msr vbar_el3, x1
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* ---------------------------------------------------------------------
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*/
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mrs x1, cptr_el3
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bic w1, w1, #TCPAC_BIT
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bic w1, w1, #TTA_BIT
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bic w1, w1, #TFP_BIT
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msr cptr_el3, x1
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#if RESET_TO_BL31
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/* -------------------------------------------------------
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* Will not return from this macro if it is a warm boot.
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* -------------------------------------------------------
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*/
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wait_for_entrypoint
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bl platform_mem_init
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#endif
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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/* ---------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------
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*/
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msr spsel, #0
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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/* ---------------------------------------------
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* Perform platform specific early arch. setup
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* ---------------------------------------------
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*/
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#if RESET_TO_BL31
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mov x0, 0
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mov x1, 0
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#else
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mov x0, x20
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mov x1, x21
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#endif
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bl bl31_early_platform_setup
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bl bl31_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl31_main
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b el3_exit
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