160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
/*
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* Allwinner sun50iw1p1 SoCs R_PIO pinctrl driver.
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*
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* Copyright (C) 2014 Jackie Hwang
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*
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* Jackie Hwang <huangshr@allwinnertech.com>
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*
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* Copyright (C) 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* Copyright (C) 2014 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun50iw1p1_r_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_rsb0"), /* SCK */
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SUNXI_FUNCTION(0x3, "s_twi0"), /* SCK */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_rsb0"), /* SDA */
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SUNXI_FUNCTION(0x3, "s_twi0"), /* SDA */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag0"), /* MS */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag0"), /* CK */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag0"), /* DO */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_jtag0"), /* DI */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_twi0"), /* SCK */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_twi0"), /* SDA */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_pwm0"),
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_cir0"), /* RX */
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x7, "io_disabled"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
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};
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#define IRQ_BANK_NUM 1
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static const unsigned sun50iw1p1_r_irq_bank_base[IRQ_BANK_NUM] = {0};
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static const struct sunxi_pinctrl_desc sun50iw1p1_r_pinctrl_data = {
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.pins = sun50iw1p1_r_pins,
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.npins = ARRAY_SIZE(sun50iw1p1_r_pins),
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.pin_base = PL_BASE,
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.irq_banks = IRQ_BANK_NUM,
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.irq_bank_base = sun50iw1p1_r_irq_bank_base,
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};
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static int sun50iw1p1_r_pinctrl_probe(struct platform_device *pdev)
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{
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return sunxi_pinctrl_init(pdev,
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&sun50iw1p1_r_pinctrl_data);
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}
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static struct of_device_id sun50iw1p1_r_pinctrl_match[] = {
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{ .compatible = "allwinner,sun50i-r-pinctrl", },
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{}
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};
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MODULE_DEVICE_TABLE(of, sun50iw1p1_r_pinctrl_match);
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static struct platform_driver sun50iw1p1_r_pinctrl_driver = {
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.probe = sun50iw1p1_r_pinctrl_probe,
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.driver = {
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.name = "sun50i-r-pinctrl",
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.owner = THIS_MODULE,
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.of_match_table = sun50iw1p1_r_pinctrl_match,
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},
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};
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static int __init sun50iw1p1_r_pio_init(void)
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{
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int ret;
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ret = platform_driver_register(&sun50iw1p1_r_pinctrl_driver);
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if (ret) {
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pr_debug("register sun50iw1p1 r-pio controller failed\n");
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return -EINVAL;
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}
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return 0;
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}
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postcore_initcall(sun50iw1p1_r_pio_init);
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MODULE_AUTHOR("Jackie Hwang <huangshr@allwinnertech.com>");
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MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
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MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
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MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
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MODULE_DESCRIPTION("Allwinner sun50iw1p1 R_PIO pinctrl driver");
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MODULE_LICENSE("GPL");
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