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SmartAudio/lichee/linux-4.9/arch/arm/boot/dts/sun8iw17p1.dtsi

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/*
* Allwinner Technology CO., Ltd. sun8iw17p1 platform
*
* modify base on juno.dts
*/
/* nobody use, just to "avoid"(not reslove) OOM problem at the begining of the physical memory address. */
/memreserve/ 0x40000000 0x00001000; /* reserve for out of memory access problem: size = 4K */
/* kernel used */
/memreserve/ 0x43000000 0x00000800; /* super standby range : [0x40020000~0x41020800], size = 2K */
/memreserve/ 0x48000000 0x01000000; /* atf : [0x48000000~0x49000000], size = 16M */
/* tf used */
/memreserve/ 0x48100000 0x00004000; /* arisc dram code space range: [0x48100000~0x48104000], size = 16K */
/memreserve/ 0x48104000 0x00001000; /* arisc para cfg range : [0x48104000~0x48105000], size = 4K */
/memreserve/ 0x48105000 0x00001000; /* arisc message pool range : [0x48105000~0x48106000], size = 4K */
/* pstore used */
/memreserve/ 0x48106000 0x00100000; /* ram oops log range : [0x48106000~0x48206000], size = 1M */
/memreserve/ 0x48200000 0x00100000; /* 360 config size = 1M */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw17p1-clk.dtsi"
#include "sun8iw17p1-pinctrl.dtsi"
/ {
model = "sun8iw17p1";
compatible = "allwinner,sun8iw17p1";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
serial8 = &uart8;
/* serial9 = &uart9; */
twi0 = &twi0;
twi1 = &twi1;
twi2 = &twi2;
twi3 = &twi3;
twi4 = &twi4;
twi5 = &twi5;
twi6 = &twi6;
twi7 = &twi7;
spi0 = &spi0;
spi1 = &spi1;
gmac0 = &gmac0;
scr0 = &scr0;
global_timer0 = &soc_timer0;
mmc0 = &sdc0;
mmc2 = &sdc2;
mmc3 = &sdc3;
nand0 =&nand0;
disp = &disp;
lcd0 = &lcd0;
lcd1 = &lcd1;
pwm = &pwm;
pwm0 = &pwm0;
pwm1 = &pwm1;
tv0 = &tv0;
s_pwm = &s_pwm;
spwm0 = &spwm0;
spwm1 = &spwm1;
spwm2 = &spwm2;
spwm3 = &spwm3;
spwm4 = &spwm4;
spwm5 = &spwm5;
spwm6 = &spwm6;
spwm7 = &spwm7;
boot_disp = &boot_disp;
charger0 = &charger0;
regulator0 = &regulator0;
tvd = &tvd;
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
firmware {
android {
compatible = "android,firmware";
name = "android";
fstab {
compatible = "android,fstab";
name = "fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
fsmgr_flags = "wait";
mnt_flags = "ro,barrier=1";
name = "vendor";
status = "ok";
type = "ext4";
};
system {
compatible = "android,system";
dev = "/dev/block/by-name/system";
fsmgr_flags = "wait";
mnt_flags = "ro,barrier=1";
name = "system";
status = "ok";
type = "ext4";
};
};
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
clocks = <&clk_pll_cpu0>;
clock-latency = <2000000>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
enable-method = "psci";
clocks = <&clk_pll_cpu0>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
enable-method = "psci";
clocks = <&clk_pll_cpu0>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
enable-method = "psci";
clocks = <&clk_pll_cpu1>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
enable-method = "psci";
clocks = <&clk_pll_cpu1>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@5 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clocks = <&clk_pll_cpu1>;
enable-method = "psci";
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <22>;
exit-latency-us = <85>;
min-residency-us = <10000>;
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <1000>;
min-residency-us = <2500>;
local-timer-stop;
};
SYS_SLEEP_0: sys-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x2010000>;
entry-latency-us = <1000>;
exit-latency-us = <2000>;
min-residency-us = <4500>;
local-timer-stop;
};
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
gpu: gpu@0x01800000 {
compatible = "arm,mali-400", "arm,mali-utgard";
reg = <0x0 0x01800000 0x0 0x10000>;
interrupts = <GIC_SPI 89 4>,
<GIC_SPI 90 4>,
<GIC_SPI 91 4>,
<GIC_SPI 92 4>,
<GIC_SPI 94 4>,
<GIC_SPI 95 4>,
<GIC_SPI 96 4>,
<GIC_SPI 97 4>,
<GIC_SPI 98 4>,
<GIC_SPI 99 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", "IRQPP2", "IRQPPMMU2", "IRQPP3", "IRQPPMMU3";
clocks = <&clk_pll_gpu>, <&clk_gpu>;
};
n_brom {
compatible = "allwinner,n-brom";
reg = <0x0 0x0 0x0 0xc000>;
};
s_brom {
compatible = "allwinner,s-brom";
reg = <0x0 0x0 0x0 0x10000>;
};
sram_ctrl {
device_type = "sram_ctrl";
compatible = "allwinner,sram_ctrl";
reg = <0x0 0x03000000 0x0 0x100>;
};
sram_a1 {
compatible = "allwinner,sram_a1";
reg = <0x0 0x00020000 0x0 0x8000>;
};
sram_a2 {
compatible = "allwinner,sram_a2";
reg = <0x0 0x00100000 0x0 0x120000>;
};
prcm {
compatible = "allwinner,prcm";
reg = <0x0 0x07010000 0x0 0x400>;
};
cpuscfg {
compatible = "allwinner,cpuscfg";
reg = <0x0 0x07000400 0x0 0x800>;
};
ion {
compatible = "allwinner,sunxi-ion";
/*
*types list here:
ION_HEAP_TYPE_SYSTEM = 0,
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
ION_HEAP_TYPE_CARVEOUT = 2,
ION_HEAP_TYPE_CHUNK = 3,
ION_HEAP_TYPE_DMA = 4,
ION_HEAP_TYPE_SECURE = 6,
**/
heap_sys_user@0{
compatible = "allwinner,sys_user";
heap-name = "sys_user";
heap-id = <0x0>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_system";
};
heap_sys_contig@0{
compatible = "allwinner,sys_contig";
heap-name = "sys_contig";
heap-id = <0x1>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_contig";
};
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
};
dram: dram {
compatible = "allwinner,dram";
clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>;
clock-names = "pll_ddr0","pll_ddr1";
dram_clk = <672>;
dram_type = <3>;
dram_zq = <0x003F3FDD>;
dram_odt_en = <1>;
dram_para1 = <0x10f41000>;
dram_para2 = <0x00001200>;
dram_mr0 = <0x1A50>;
dram_mr1 = <0x40>;
dram_mr2 = <0x10>;
dram_mr3 = <0>;
dram_tpr0 = <0x04E214EA>;
dram_tpr1 = <0x004214AD>;
dram_tpr2 = <0x10A75030>;
dram_tpr3 = <0>;
dram_tpr4 = <0>;
dram_tpr5 = <0>;
dram_tpr6 = <0>;
dram_tpr7 = <0>;
dram_tpr8 = <0>;
dram_tpr9 = <0>;
dram_tpr10 = <0>;
dram_tpr11 = <0>;
dram_tpr12 = <168>;
dram_tpr13 = <0x823>;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
};
gic: interrupt-controller@03020000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
};
sid: sunxi-sid@03006000 {
compatible = "allwinner,sunxi-sid";
device_type = "sid";
reg = <0x0 0x03006000 0 0x0200>;
};
chipid: sunxi-chipid@03006200 {
compatible = "allwinner,sunxi-chipid";
device_type = "chipid";
reg = <0x0 0x03006200 0 0x0140>;
};
timer_arch {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Secure Phys IRQ */
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Non-secure Phys IRQ */
clock-frequency = <24000000>;
arm,cpu-registers-not-fw-configured;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 172 4>,
<GIC_SPI 173 4>,
<GIC_SPI 174 4>,
<GIC_SPI 192 4>,
<GIC_SPI 193 4>,
<GIC_SPI 194 4>;
};
opp_dvfs_table:opp_dvfs_table {
cluster_num = <1>;
opp_table_count = <1>;
cpu_opp_l_table0: opp_l_table0 {
/* compatible = "operating-points-v2"; */
compatible = "allwinner,opp_l_table0";
opp_count = <6>;
opp-shared;
opp00 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <1000000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp02 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1060000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp03 {
opp-hz = /bits/ 64 <912000000>;
opp-microvolt = <1120000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp05 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1320000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
};
};
dramfreq {
compatible = "allwinner,sunxi-dramfreq";
reg = <0x0 0x04002000 0x0 0x1000>,
<0x0 0x04003000 0x0 0x1000>,
<0x0 0x03001000 0x0 0x800>;
interrupts = <GIC_SPI 9 0x4>;
clocks = <&clk_pll_ddr0>,<&clk_pll_ddr1>,<&clk_ahb1>;
status = "okay";
};
uboot: uboot {
};
soc: soc@03000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_type = "soc";
dma0:dma-controller@03002000 {
compatible = "allwinner,sun8i-dma";
reg = <0x0 0x03002000 0x0 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_dma>;
#dma-cells = <1>;
};
mbus0:mbus-controller@04002000 {
compatible = "allwinner,sun8i-mbus";
reg = <0x0 0x04002000 0x0 0x1000>;
#mbus-cells = <1>;
};
arisc {
compatible = "allwinner,sunxi-arisc";
#address-cells = <2>;
#size-cells = <2>;
clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>;
clock-names = "losc", "iosc", "hosc", "pll_periph0";
powchk_used = <0x0>;
power_reg = <0x02309621>;
system_power = <50>;
};
arisc_space {
compatible = "allwinner,arisc_space";
/* num dst offset size */
space1 = <0x48040000 0x00000000 0x00014000>; /* srama2 code space */
space2 = <0x48100000 0x00018000 0x00004000>; /* dram code space */
space3 = <0x48104000 0x00000000 0x00001000>; /* para space */
space4 = <0x48105000 0x00000000 0x00001000>; /* msgpool space */
};
standby_space {
compatible = "allwinner,sun8iw17-usbstandby";
/* num dst offset size */
space1 = <0x43000000 0x00000000 0x00000800>; /* super standby para space */
};
msgbox: msgbox@3003000 {
compatible = "allwinner,msgbox";
clocks = <&clk_msgbox>;
clock-names = "clk_msgbox";
reg = <0x0 0x03003000 0x0 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>;
status = "okay";
};
hwspinlock: hwspinlock@3004000 {
compatible = "allwinner,sunxi-hwspinlock";
clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>;
clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
reg = <0x0 0x03004000 0x0 0x1000>;
num-locks = <8>; /* the number hwspinlock we needed, max 32 */
status = "okay";
};
s_cir0: s_cir@07040000 {
compatible = "allwinner,s_cir";
reg = <0x0 0x07040000 0x0 0x400>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_cir0_pins_a>;
pinctrl-1 = <&s_cir0_pins_b>;
clocks = <&clk_hosc>,<&clk_cpurcir>;
supply = "";
supply_vol = "";
status = "okay";
};
s_uart0: s_uart@1f02800 {
compatible = "allwinner,s_uart";
reg = <0x0 0x01f02800 0x0 0x400>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_uart0_pins_a>;
status = "okay";
};
s_twi0: s_twi@1f03400 {
compatible = "allwinner,s_twi";
reg = <0x0 0x01f02400 0x0 0x20>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_twi0_pins_a>;
status = "okay";
};
s_rsb0: s_rsb@7083000 {
compatible = "allwinner,s_rsb";
reg = <0x0 0x07083000 0x0 0x400>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_rsb0_pins_a>;
status = "disable";
};
s_jtag0: s_jtag0 {
compatible = "allwinner,s_jtag";
pinctrl-names = "default";
pinctrl-0 = <&s_jtag0_pins_a>;
status = "disable";
};
s_cpuscfg: s_cpuscfg@0x7000400 {
compatible = "allwinner,s_cpuscfg";
reg = <0x0 0x07000400 0x0 0x800>;
status = "okay";
};
box_start_os: box_start_os0 {
compatible = "allwinner,box_start_os";
start_type = <0x0>;
irkey_used = <0x0>;
pmukey_used = <0x0>;
pmukey_num = <0x0>;
led_power = <0x0>;
led_state = <0x0>;
status = "disable";
};
soc_timer0: timer@03009000 {
compatible = "allwinner,sun4i-a10-timer";
device_type = "timer";
reg = <0x0 0x03009000 0x0 0x90>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
/* On FPGA, timer can only use the losc.
* On IC, timer should use the hosc.
*/
clocks = <&clk_hosc>, <&clk_losc>;
};
rtc: rtc@07000000 {
compatible = "allwinner,sun8i-rtc",
"allwinner,sunxi-rtc";
device_type = "rtc";
reg = <0x0 0x07000000 0x0 0x400>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
gpr_offset = <0x100>;
gpr_len = <8>;
gpr_cur_pos = <6>;
};
wdt: watchdog@030090a0 {
compatible = "allwinner,sun8i-wdt";
reg = <0x0 0x030090a0 0x0 0x20>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
};
eve: eve@01500000 {
compatible = "allwinner,sunxi-aie-eve";
reg = <0x0 0x01500000 0x0 0xff>,
<0x0 0x03001000 0x0 0x80f>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_eve>, <&clk_eve>;
};
ve@01c0e000 {
compatible = "allwinner,sunxi-cedar-ve";
reg = <0x0 0x01c0e000 0x0 0x1000>,
<0x0 0x03000000 0x0 0x10>,
<0x0 0x03001000 0x0 0x800>;
interrupts = <GIC_SPI 25 4>;
clocks = <&clk_pll_ve>, <&clk_ve>;
};
uart0: uart@05000000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart0";
reg = <0x0 0x05000000 0x0 0x400>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-1 = <&uart0_pins_b>;
uart0_port = <0>;
uart0_type = <2>;
status = "okay";
};
uart1: uart@05000400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart1";
reg = <0x0 0x05000400 0x0 0x400>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-1 = <&uart1_pins_b>;
uart1_port = <1>;
uart1_type = <4>;
use_dma = <1>;
status = "disabled";
};
uart2: uart@05000800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart2";
reg = <0x0 0x05000800 0x0 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_a>;
pinctrl-1 = <&uart2_pins_b>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@05000c00 {
compatible = "allwinner,sun8i-uart";
device_type = "uart3";
reg = <0x0 0x05000c00 0x0 0x400>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pins_a>;
pinctrl-1 = <&uart3_pins_b>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
uart4: uart@05001000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart4";
reg = <0x0 0x05001000 0x0 0x400>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_pins_b>;
uart4_port = <4>;
uart4_type = <4>;
status = "okay";
};
/* s_uart1 */
uart5: uart@07080400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart5";
reg = <0x0 0x07080400 0x0 0x400>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_cpuruart1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_uart1_pins_a>;
pinctrl-1 = <&s_uart1_pins_b>;
uart5_port = <5>;
uart5_type = <4>;
status = "disabled";
};
/* s_uart2 */
uart6: uart@07080800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart6";
reg = <0x0 0x07080800 0x0 0x400>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_cpuruart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_uart2_pins_a>;
pinctrl-1 = <&s_uart2_pins_b>;
uart6_port = <6>;
uart6_type = <4>;
status = "disabled";
};
/* s_uart3 */
uart7: uart@07080c00 {
compatible = "allwinner,sun8i-uart";
device_type = "uart7";
reg = <0x0 0x07080c00 0x0 0x400>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_cpuruart3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_uart3_pins_a>;
pinctrl-1 = <&s_uart3_pins_b>;
uart7_port = <7>;
uart7_type = <4>;
status = "disabled";
};
/* s_uart4 */
uart8: uart@07081000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart8";
reg = <0x0 0x07081000 0x0 0x400>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_cpuruart4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_uart4_pins_a>;
pinctrl-1 = <&s_uart4_pins_b>;
uart8_port = <8>;
uart8_type = <4>;
status = "disabled";
};
/* s_uart0 */
/*
uart9: uart@07080000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart9";
reg = <0x0 0x07080000 0x0 0x400>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_cpuruart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_uart0_pins_a>;
pinctrl-1 = <&s_uart0_pins_b>;
uart9_port = <9>;
uart9_type = <2>;
status = "disabled";
status = "okay";
};
*/
can0: can@0x05004000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-can";
device_type = "can0";
reg = <0x0 0x05004000 0x0 0x400>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_can>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&can0_pins_a>;
pinctrl-1 = <&can0_pins_b>;
status = "okay";
};
twi0: twi@0x05002000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi0";
reg = <0x0 0x05002000 0x0 0x400>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi0_pins_a>;
pinctrl-1 = <&twi0_pins_b>;
status = "disabled";
};
twi1: twi@0x05002400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi1";
reg = <0x0 0x05002400 0x0 0x400>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi1_pins_a>;
pinctrl-1 = <&twi1_pins_b>;
status = "disabled";
};
twi2: twi@0x05002800{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi2";
reg = <0x0 0x05002800 0x0 0x400>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi2>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi2_pins_a>;
pinctrl-1 = <&twi2_pins_b>;
status = "disabled";
};
twi3: twi@0x05002c00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi3";
reg = <0x0 0x05002c00 0x0 0x400>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi3>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi3_pins_a>;
pinctrl-1 = <&twi3_pins_b>;
status = "disabled";
};
twi4: twi@0x05003000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi4";
reg = <0x0 0x05003000 0x0 0x400>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi4>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi4_pins_a>;
pinctrl-1 = <&twi4_pins_b>;
status = "disabled";
};
twi5: twi@0x05003400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi5";
reg = <0x0 0x05003400 0x0 0x400>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi5>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi5_pins_a>;
pinctrl-1 = <&twi5_pins_b>;
status = "disabled";
};
twi6: twi@0x05003800{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi6";
reg = <0x0 0x05003800 0x0 0x400>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi6>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi6_pins_a>;
pinctrl-1 = <&twi6_pins_b>;
status = "disabled";
};
twi7: twi@0x07081800{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi7";
reg = <0x0 0x07081800 0x0 0x400>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_cpurtwi1>;
clock-frequency = <100000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi7_pins_a>;
pinctrl-1 = <&twi7_pins_b>;
status = "disabled";
};
ts0:ts0@05060000 {
compatible = "allwinner,sun8i-tsc";
device_type = "ts0";
reg = <0x0 0x05060000 0x0 0x1000>;
interrupts = <GIC_SPI 28 4>;
clocks = <&clk_pll_periph0>,<&clk_ts>;
pinctrl-names = "ts0-default", "ts0-sleep";
pinctrl-0 = <&ts0_pins_a>;
pinctrl-1 = <&ts0_pins_b>;
ts0config = <0x1>;
status = "okay";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <2>;
usb_detect_type = <1>;
usb_id_gpio;
usb_det_vbus_gpio;
usb_drv_vbus_gpio;
usb_host_init_state = <0>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_luns = <3>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
status = "okay";
};
udc:udc-controller@0x05100000 {
compatible = "allwinner,sunxi-udc";
reg = <0x0 0x05100000 0x0 0x1000>, /*udc base*/
<0x0 0x00000000 0x0 0x100>; /*sram base*/
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg>;
status = "okay";
};
ehci0:ehci0-controller@0x05101000 {
compatible = "allwinner,sunxi-ehci0";
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x05101400 {
compatible = "allwinner,sunxi-ohci0";
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <0>;
status = "okay";
};
usbc1:usbc1@0 {
device_type = "usbc1";
usb_drv_vbus_gpio;
usb_host_init_state = <1>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
status = "okay";
};
ehci1:ehci1-controller@0x05200000 {
compatible = "allwinner,sunxi-ehci1";
reg = <0x0 0x05200000 0x0 0xFFF>, /*hci1 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy1>, <&clk_usbehci1>;
hci_ctrl_no = <1>;
status = "okay";
};
ohci1:ohci1-controller@0x05200400 {
compatible = "allwinner,sunxi-ohci1";
reg = <0x0 0x05200000 0x0 0xFFF>, /*hci1 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy1>, <&clk_usbohci1>, <&clk_usbohci1_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <1>;
status = "okay";
};
usbc2:usbc2@0 {
device_type = "usbc2";
usb_drv_vbus_gpio;
usb_host_init_state = <1>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
status = "okay";
};
ehci2:ehci2-controller@0x05310000 {
compatible = "allwinner,sunxi-ehci2";
reg = <0x0 0x05310000 0x0 0xFFF>, /*hci2 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy2>, <&clk_usbehci2>;
hci_ctrl_no = <2>;
status = "okay";
};
ohci2:ohci2-controller@0x05310400 {
compatible = "allwinner,sunxi-ohci2";
reg = <0x0 0x05310000 0x0 0xFFF>, /*hci2 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy2>, <&clk_usbohci2>, <&clk_usbohci2_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <2>;
status = "okay";
};
usbc3:usbc3@0 {
device_type = "usbc3";
usb_drv_vbus_gpio;
usb_host_init_state = <1>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
status = "okay";
};
ehci3:ehci3-controller@0x05311000 {
compatible = "allwinner,sunxi-ehci3";
reg = <0x0 0x05311000 0x0 0xFFF>, /*hci3 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy3>, <&clk_usbehci3>, <&clk_usbhsic>, <&clk_usbhsic12m>, <&clk_pll_hsic>;
hci_ctrl_no = <3>;
status = "okay";
};
ohci3:ohci3-controller@0x05311400 {
compatible = "allwinner,sunxi-ohci3";
reg = <0x0 0x05311000 0x0 0xFFF>, /*hci3 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy3>, <&clk_usbohci3>, <&clk_usbohci3_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <3>;
status = "okay";
};
codec:codec@0x05096000 {
compatible = "allwinner,sunxi-internal-codec";
reg = <0x0 0x05096000 0x0 0x2bc>,/*digital baseadress*/
<0x0 0x07010280 0x0 0x4>;/*analog baseadress*/
clocks = <&clk_pll_audio>,<&clk_codec_1x>;
spkervol = <0x1f>;
adcagc_cfg = <0x0>;
adcdrc_cfg = <0x0>;
adchpf_cfg = <0x0>;
dacdrc_cfg = <0x0>;
dachpf_cfg = <0x0>;
pa_sleep_time = <0x15e>;
status = "okay";
};
cpudai:cpudai0-controller@0x05096000 {
compatible = "allwinner,sunxi-internal-cpudai";
reg = <0x0 0x05096000 0x0 0x2bc>;/*digital baseadress*/
status = "okay";
};
daudio0:daudio@0x05090000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05090000 0x0 0x74>;
clocks = <&clk_pll_audio>,<&clk_i2s0>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio0_pins_a>;
pinctrl-1 = <&daudio0_pins_b>;
pcm_lrck_period = <0x20>;
pcm_lrckr_period = <0x01>;
slot_width_select = <0x20>;
pcm_lsb_first = <0x0>;
tx_data_mode = <0x0>;
rx_data_mode = <0x0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x0>;
tdm_config = <0x01>;
tdm_num = <0x0>;
mclk_div = <0x0>;
status = "okay";
};
daudio1:daudio@0x05091000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05091000 0x0 0x74>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio1_pins_a>;
pinctrl-1 = <&daudio1_pins_b>;
clocks = <&clk_pll_audio>,<&clk_i2s1>;
pcm_lrck_period = <0x20>;
pcm_lrckr_period = <0x01>;
slot_width_select = <0x20>;
pcm_lsb_first = <0x0>;
tx_data_mode = <0x0>;
rx_data_mode = <0x0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x0>;
tdm_config = <0x01>;
tdm_num = <0x1>;
mclk_div = <0x0>;
status = "okay";
};
daudio2:daudio@0x05092000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05092000 0x0 0x74>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio2_pins_a>;
pinctrl-1 = <&daudio2_pins_b>;
clocks = <&clk_pll_audio>,<&clk_i2s2>;
pcm_lrck_period = <0x20>;
pcm_lrckr_period = <0x01>;
slot_width_select = <0x20>;
pcm_lsb_first = <0x0>;
tx_data_mode = <0x0>;
rx_data_mode = <0x0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x0>;
tdm_config = <0x01>;
tdm_num = <0x2>;
mclk_div = <0x0>;
status = "okay";
};
spdif:spdif-controller@0x05093000{
compatible = "allwinner,sunxi-spdif";
reg = <0x0 0x05093000 0x0 0x40>;
clocks = <&clk_pll_audio>,<&clk_spdif>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&spdif_pins_a>;
pinctrl-1 = <&spdif_pins_b>;
status = "okay";
};
dmic:dmic-controller@0x05095000{
compatible = "allwinner,sunxi-dmic";
reg = <0x0 0x05095000 0x0 0x50>;
clocks = <&clk_pll_audio>,<&clk_dmic>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&dmic_pins_a &dmic_pins_b>;
pinctrl-1 = <&dmic_pins_c>;
status = "disabled";
};
sndcodec:sound@0 {
compatible = "allwinner,sunxi-codec-machine";
sunxi,cpudai-controller = <&cpudai>;
sunxi,audio-codec = <&codec>;
status = "okay";
};
snddaudio0:sound@1{
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio0-controller = <&daudio0>;
status = "okay";
};
snddaudio1:sound@2{
compatible = "allwinner,sunxi-daudio1-machine";
sunxi,daudio1-controller = <&daudio1>;
status = "okay";
};
snddaudio2:sound@3{
compatible = "allwinner,sunxi-daudio2-machine";
sunxi,daudio1-controller = <&daudio2>;
status = "okay";
};
sndspdif:sound@4{
compatible = "allwinner,sunxi-spdif-machine";
sunxi,spdif-controller = <&spdif>;
status = "okay";
};
snddmic:sound@5{
compatible = "allwinner,sunxi-dmic-machine";
sunxi,dmic-controller = <&dmic>;
status = "disabled";
};
spi0: spi@05010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi0";
reg = <0x0 0x05010000 0x0 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
pinctrl-1 = <&spi0_pins_c>;
spi0_cs_number = <2>;
spi0_cs_bitmap = <3>;
status = "disabled";
};
spi1: spi@05011000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi1";
reg = <0x0 0x05011000 0x0 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi1>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
pinctrl-1 = <&spi1_pins_c>;
spi1_cs_number = <2>;
spi1_cs_bitmap = <3>;
status = "disabled";
};
sdc2: sdmmc@04022000 {
compatible = "allwinner,sunxi-mmc-v4p5x";
device_type = "sdc2";
reg = <0x0 0x04022000 0x0 0x1000>;
interrupts = <GIC_SPI 54 0x0104>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc2_mod>,
<&clk_sdmmc2_bus>,
<&clk_sdmmc2_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc2_pins_a>;
pinctrl-1 = <&sdc2_pins_b>;
bus-width = <8>;
cap-mmc-highspeed;
/*mmc-ddr-1_8v;*/
/*mmc-hs200-1_8v;*/
/*mmc-hs400-1_8v;*/
non-removable;
/*max-frequency = <200000000>;*/
max-frequency = <50000000>;
cap-erase;
mmc-high-capacity-erase-size;
no-sdio;
no-sd;
/*-- speed mode --*/
/*sm0: DS26_SDR12*/
/*sm1: HSSDR52_SDR25*/
/*sm2: HSDDR52_DDR50*/
/*sm3: HS200_SDR104*/
/*sm4: HS400*/
/*-- frequency point --*/
/*f0: CLK_400K*/
/*f1: CLK_25M*/
/*f2: CLK_50M*/
/*f3: CLK_100M*/
/*f4: CLK_150M*/
/*f5: CLK_200M*/
sdc_tm4_sm0_freq0 = <0>;
sdc_tm4_sm0_freq1 = <0>;
sdc_tm4_sm1_freq0 = <0x00000000>;
sdc_tm4_sm1_freq1 = <0>;
sdc_tm4_sm2_freq0 = <0x00000000>;
sdc_tm4_sm2_freq1 = <0>;
sdc_tm4_sm3_freq0 = <0x05000000>;
sdc_tm4_sm3_freq1 = <0x00000005>;
sdc_tm4_sm4_freq0 = <0x00050000>;
sdc_tm4_sm4_freq1 = <0x00000004>;
/*vmmc-supply = <&reg_3p3v>;*/
/*vqmc-supply = <&reg_3p3v>;*/
/*vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sunxi-power-save-mode;*/
/*status = "disabled";*/
status = "okay";
};
sdc0: sdmmc@04020000 {
compatible = "allwinner,sunxi-mmc-v4p1x";
device_type = "sdc0";
reg = <0x0 0x04020000 0x0 0x1000>;
interrupts = <GIC_SPI 52 0x0104>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc0_mod>,
<&clk_sdmmc0_bus>,
<&clk_sdmmc0_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc0_pins_a>;
pinctrl-1 = <&sdc0_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*non-removable;*/
/*broken-cd;*/
/*cd-inverted*/
cd-gpios = <&pio PF 6 0 1 2 0>;
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
no-sdio;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
/*sunxi-dly-104M = <1 0 0 0>;*/
/*sunxi-dly-208M = <1 0 0 0>;*/
/*sunxi-dly-104M-ddr = <1 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0>;*/
status = "okay";
};
sdc1: sdmmc@04021000 {
compatible = "allwinner,sunxi-mmc-v4p1x";
device_type = "sdc1";
reg = <0x0 0x04021000 0x0 0x1000>;
interrupts = <GIC_SPI 53 0x0104>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc1_mod>,
<&clk_sdmmc1_bus>,
<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
sunxi-dly-52M = <1 1 0 0 1>;
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
sunxi-dly-104M = <1 0 0 0 1>;
/*sunxi-dly-208M = <1 1 0 0 0>;*/
sunxi-dly-208M = <1 0 0 0 1>;
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
status = "disabled";
/*status = "okay";*/
};
sdc3: sdmmc@04023000 {
compatible = "allwinner,sunxi-mmc-v4p1x";
device_type = "sdc3";
reg = <0x0 0x04023000 0x0 0x1000>;
interrupts = <GIC_SPI 55 0x0104>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc3_mod>,
<&clk_sdmmc3_bus>,
<&clk_sdmmc3_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc3_pins_a>;
pinctrl-1 = <&sdc3_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
cap-sd-highspeed;
no-sdio;
no-mmc;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
/*sunxi-dly-208M = <1 1 0 0 0>;*/
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
status = "disabled";
/*status = "okay";*/
};
disp: disp@01000000 {
compatible = "allwinner,sunxi-disp";
reg = <0x0 0x01000000 0x0 0x013fffff>,/*de*/
<0x0 0x06510000 0x0 0xfff>,/*disp_if_top*/
<0x0 0x06511000 0x0 0xfff>,/*tcon_lcd0*/
<0x0 0x06512000 0x0 0xfff>,/*tcon_lcd1*/
<0x0 0x06515000 0x0 0xfff>,/*tcon_tv*/
<0x0 0x06504000 0x0 0x10fc>,/*dsi0*/
<0x0 0x06504000 0x0 0x10fc>;/*dsi*/
interrupts = <GIC_SPI 71 0x0104>, <GIC_SPI 72 0x0104>,
<GIC_SPI 73 0x0104>, <GIC_SPI 51 0x0104>,
<GIC_SPI 51 0x0104>;
clocks = <&clk_de>,
<&clk_display_top>,
<&clk_tcon_lcd0>,
<&clk_tcon_lcd1>,
<&clk_tcon_tv>,
<&clk_lvds>,
<&clk_mipi_host>,
<&clk_mipi_host>;
boot_disp = <0>;
fb_base = <0>;
status = "okay";
};
lcd0: lcd0@01c0c000 {
compatible = "allwinner,sunxi-lcd0";
pinctrl-names = "active","sleep";
status = "okay";
};
lcd1: lcd1@06512000 {
compatible = "allwinner,sunxi-lcd1";
pinctrl-names = "active","sleep";
status = "okay";
};
tv0: tv0@06524000 {
compatible = "allwinner,sunxi-tv";
reg = <0x0 0x06520000 0x0 0x100>,
<0x0 0x06524000 0x0 0x3fc>;
clocks = <&clk_tve_top>,<&clk_tve0>;
device_type = "tv0";
pinctrl-names = "active","sleep";
status = "okay";
};
tvd: tvd@06530000 {
compatible = "allwinner,sunxi-tvd";
reg = <0x0 0x06530000 0x0 0x00010000>;/*tvd_top*/
clocks = <&clk_tvd_top>;
interrupts = <GIC_SPI 61 0x0104>;
tvd-number = <4>;
tvds = <&tvd0>, <&tvd1>, <&tvd2>, <&tvd3>;
status = "okay";
};
tvd0: tvd0@06531000 {
compatible = "allwinner,sunxi-tvd0";
reg = <0x0 0x06531000 0x0 0x00010000>;
interrupts = <GIC_SPI 56 0x0104>;
clocks = <&clk_tvd0>;
tvd_used = <1>;
tvd_if = <0>;
status = "okay";
};
tvd1: tvd1@06532000 {
compatible = "allwinner,sunxi-tvd1";
reg = <0x0 0x06532000 0x0 0x00010000>;
interrupts = <GIC_SPI 57 0x0104>;
clocks = <&clk_tvd1>;
tvd_used = <1>;
tvd_if = <0>;
status = "okay";
};
tvd2: tvd2@06533000 {
compatible = "allwinner,sunxi-tvd2";
reg = <0x0 0x06533000 0x0 0x00010000>;
interrupts = <GIC_SPI 58 0x0104>;
clocks = <&clk_tvd2>;
tvd_used = <1>;
tvd_if = <0>;
status = "okay";
};
tvd3: tvd3@06534000 {
compatible = "allwinner,sunxi-tvd3";
reg = <0x0 0x06534000 0x0 0x00010000>;
interrupts = <GIC_SPI 59 0x0104>;
clocks = <&clk_tvd3>;
tvd_used = <1>;
tvd_if = <0>;
status = "okay";
};
soc_tr: tr@01000000 {
compatible = "allwinner,sun50i-tr";
reg = <0x0 0x01000000 0x0 0x000200bc>;
interrupts = <GIC_SPI 96 0x0104>;
clocks = <&clk_de>;
status = "okay";
};
g2d: g2d@01480000 {
compatible = "allwinner,sunxi-g2d";
reg = <0x0 0x01480000 0x0 0xbffff>;
interrupts = <GIC_SPI 21 0x0104>;
clocks = <&clk_g2d>;
status = "okay";
};
pwm: pwm@0300a000 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x0300a000 0x0 0x3c>;
clocks = <&clk_pwm>;
pwm-number = <2>;
pwm-base = <0x0>;
pwms = <&pwm0>,<&pwm1>;
};
pwm0: pwm0@0300a000 {
compatible = "allwinner,sunxi-pwm0";
pinctrl-names = "active", "sleep";
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x00>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x00>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x00>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x01>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x00>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x01>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x20>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x20>;
reg_bypass_shift = <0x05>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x20>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x20>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x30>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x30>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x00>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x00>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x60>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x60>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x60>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x60>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x60>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x64>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x64>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm1: pwm1@0300a000 {
compatible = "allwinner,sunxi-pwm1";
pinctrl-names = "active", "sleep";
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x01>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x01>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x02>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x03>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x02>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x03>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x20>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x20>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x20>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x20>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x30>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x30>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x01>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x01>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x80>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x80>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x80>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x80>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x80>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x84>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x84>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
s_pwm: s_pwm@0x07020c00 {
compatible = "allwinner,sunxi-s_pwm";
reg = <0x0 0x07020c00 0x0 0x3c>;
clocks = <&clk_cpurpwm>;
pwm-number = <8>;
pwm-base = <0x10>;
pwms = <&spwm0>, <&spwm1>, <&spwm2>, <&spwm3>, <&spwm4>,
<&spwm5>, <&spwm6>, <&spwm7>;
};
spwm0: spwm0@0x07020c00 {
compatible = "allwinner,sunxi-pwm16";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x00>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x00>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x00>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x01>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x00>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x01>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x20>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x20>;
reg_bypass_shift = <0x05>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x20>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x20>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x30>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x30>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x00>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x00>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x60>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x60>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x60>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x60>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x60>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x64>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x64>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm1: spwm1@0x07020c00 {
compatible = "allwinner,sunxi-pwm17";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x01>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x01>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x02>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x03>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x02>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x03>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x20>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x20>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x20>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x20>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x30>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x30>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x01>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x01>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x80>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x80>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x80>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x80>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x80>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x84>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x84>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm2: spwm2@0x07020c00 {
compatible = "allwinner,sunxi-pwm18";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x02>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x02>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x04>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x05>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x04>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x05>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x24>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x24>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x24>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x24>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x34>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x34>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x02>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x02>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0xa0>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0xa0>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0xa0>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0xa0>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0xa0>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0xa4>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0xa4>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm3: spwm3@0x07020c00 {
compatible = "allwinner,sunxi-pwm19";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x03>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x04>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x06>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x07>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x06>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x07>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x24>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x24>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x24>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x24>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x34>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x34>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x03>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x03>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0xc0>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0xc0>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0xc0>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0xc0>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0xc0>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0xc4>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0xc4>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm4: spwm4@0x07020c00 {
compatible = "allwinner,sunxi-pwm20";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x04>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x04>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x08>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x09>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x08>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x09>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x28>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x28>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x28>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x28>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x38>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x38>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x04>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x04>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0xe0>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0xe0>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0xe0>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0xe0>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0xe0>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0xe4>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0xe4>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm5: spwm5@0x07020c00 {
compatible = "allwinner,sunxi-pwm21";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x05>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x05>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x0a>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x0b>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x0a>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x0b>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x28>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x28>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x28>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x28>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x38>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x38>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x05>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x05>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x100>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x100>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x100>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x100>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x100>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x104>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x104>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm6: spwm6@0x07020c00 {
compatible = "allwinner,sunxi-pwm22";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x06>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x06>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x0c>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x0d>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x0c>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x0d>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x2c>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x2c>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x2c>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x2c>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x3c>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x3c>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x06>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x06>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x120>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x120>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x120>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x120>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x120>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x124>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x124>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
spwm7: spwm7@0x07020c00 {
compatible = "allwinner,sunxi-pwm23";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x07>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x07>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x0e>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x0f>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x0e>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x0f>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x2c>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x2c>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x2c>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x2c>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x3c>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x3c>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x07>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x07>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x140>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x140>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x140>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x140>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x140>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x144>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x144>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
boot_disp: boot_disp {
compatible = "allwinner,boot_disp";
};
ac200: ac200 {
compatible = "allwinner,sunxi-ac200";
/* clocks = <&clk_tcon0>; */
pinctrl-names = "active","sleep";
status = "okay";
};
vind0:vind@0 {
compatible = "allwinner,sunxi-vin-media", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_id = <0>;
vind0_clk = <432000000>;
reg = <0x0 0x06600000 0x0 0x1000>;
clocks = <&clk_csi_top>, <&clk_pll_isp>,
<&clk_csi_master0>, <&clk_hosc>, <&clk_pll_isp>,
<&clk_csi_master1>, <&clk_hosc>, <&clk_pll_isp>,
<&clk_csi_master2>, <&clk_hosc>, <&clk_pll_isp>,
<&clk_csi_master3>, <&clk_hosc>, <&clk_pll_isp>,
<&clk_isp>,
<&clk_mipi_rx>,<&clk_pll_isp>;
pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep",
"mclk2-default","mclk2-sleep","mclk3-default","mclk3-sleep";
pinctrl-0 = <&csi_mclk0_pins_a>;
pinctrl-1 = <&csi_mclk0_pins_b>;
pinctrl-2 = <&csi_mclk1_pins_a>;
pinctrl-3 = <&csi_mclk1_pins_b>;
pinctrl-4 = <&csi_mclk2_pins_a>;
pinctrl-5 = <&csi_mclk2_pins_b>;
pinctrl-6 = <&csi_mclk3_pins_a>;
pinctrl-7 = <&csi_mclk3_pins_b>;
status = "okay";
csi_cci0:cci@0 {
compatible = "allwinner,sunxi-csi_cci";
reg = <0x0 0x06614000 0x0 0x400>;
interrupts = <GIC_SPI 106 4>;
clocks = <&clk_csi_cci0>;
device_id = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&csi_cci0_pins_a>;
pinctrl-1 = <&csi_cci0_pins_b>;
status = "okay";
};
csi_cci1:cci@1 {
compatible = "allwinner,sunxi-csi_cci";
reg = <0x0 0x06614400 0x0 0x400>;
interrupts = <GIC_SPI 107 4>;
clocks = <&clk_csi_cci1>;
device_id = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&csi_cci1_pins_a>;
pinctrl-1 = <&csi_cci1_pins_b>;
status = "okay";
};
csi_cci2:cci@2 {
compatible = "allwinner,sunxi-csi_cci";
reg = <0x0 0x06614800 0x0 0x400>;
interrupts = <GIC_SPI 116 4>;
clocks = <&clk_csi_cci2>;
device_id = <2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&csi_cci2_pins_a>;
pinctrl-1 = <&csi_cci2_pins_b>;
status = "okay";
};
csi_cci3:cci@3 {
compatible = "allwinner,sunxi-csi_cci";
reg = <0x0 0x06614c00 0x0 0x400>;
interrupts = <GIC_SPI 117 4>;
clocks = <&clk_csi_cci3>;
device_id = <3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&csi_cci3_pins_a>;
pinctrl-1 = <&csi_cci3_pins_b>;
status = "okay";
};
csi0:csi@0 {
device_type = "csi0";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x06601000 0x0 0x1000>;
interrupts = <GIC_SPI 104 4>;
device_id = <0>;
status = "okay";
};
csi1:csi@1 {
device_type = "csi1";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x06602000 0x0 0x1000>;
interrupts = <GIC_SPI 105 4>;
device_id = <1>;
status = "okay";
};
csi2:csi@2 {
device_type = "csi2";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x06603000 0x0 0x1000>;
interrupts = <GIC_SPI 114 4>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&csi2_pins_a>;
pinctrl-1 = <&csi2_pins_b>;
device_id = <2>;
status = "okay";
};
csi3:csi@3 {
device_type = "csi3";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x06604000 0x0 0x1000>;
interrupts = <GIC_SPI 115 4>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&csi3_pins_a>;
pinctrl-1 = <&csi3_pins_b>;
device_id = <3>;
status = "okay";
};
mipi0:mipi@0 {
compatible = "allwinner,sunxi-mipi";
reg = <0x0 0x0660C000 0x0 0x2000>;
interrupts = <GIC_SPI 108 4>;
device_id = <0>;
status = "okay";
};
mipi1:mipi@1 {
compatible = "allwinner,sunxi-mipi";
reg = <0x0 0x0660E000 0x0 0x2000>;
interrupts = <GIC_SPI 109 4>;
device_id = <1>;
status = "okay";
};
isp0:isp@0 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x02100000 0x0 0x800>;
interrupts = <GIC_SPI 36 4>;
device_id = <0>;
status = "okay";
};
isp1:isp@1 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x02100800 0x0 0x800>;
interrupts = <GIC_SPI 37 4>;
device_id = <1>;
status = "okay";
};
isp2:isp@2 {
compatible = "allwinner,sunxi-isp";
device_id = <2>;
status = "okay";
};
isp3:isp@3 {
compatible = "allwinner,sunxi-isp";
device_id = <3>;
status = "okay";
};
scaler0:scaler@0 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101000 0x0 0x400>;
device_id = <0>;
status = "okay";
};
scaler1:scaler@1 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101400 0x0 0x400>;
device_id = <1>;
status = "okay";
};
scaler2:scaler@2 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101800 0x0 0x400>;
device_id = <2>;
status = "okay";
};
scaler3:scaler@3 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101C00 0x0 0x400>;
device_id = <3>;
status = "okay";
};
scaler4:scaler@4 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02102000 0x0 0x400>;
device_id = <4>;
status = "okay";
};
scaler5:scaler@5 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02102400 0x0 0x400>;
device_id = <5>;
status = "okay";
};
scaler6:scaler@6 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02102800 0x0 0x400>;
device_id = <6>;
status = "okay";
};
scaler7:scaler@7 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02102C00 0x0 0x400>;
device_id = <7>;
status = "okay";
};
actuator0:actuator@0 {
device_type = "actuator0";
compatible = "allwinner,sunxi-actuator";
actuator0_name = "ad5820_act";
actuator0_slave = <0x18>;
actuator0_af_pwdn = <>;
actuator0_afvdd = "afvcc-csi";
actuator0_afvdd_vol = <2800000>;
status = "disabled";
};
flash0:flash@0 {
device_type = "flash0";
compatible = "allwinner,sunxi-flash";
flash0_type = <2>;
flash0_en = <>;
flash0_mode = <>;
flash0_flvdd = "";
flash0_flvdd_vol = <>;
device_id = <0>;
status = "disabled";
};
sensor0:sensor@0 {
device_type = "sensor0";
sensor0_mname = "ov5640";
sensor0_twi_cci_id = <0>;
sensor0_twi_addr = <0x78>;
sensor0_pos = "rear";
sensor0_isp_used = <0>;
sensor0_fmt = <0>;
sensor0_stby_mode = <0>;
sensor0_vflip = <0>;
sensor0_hflip = <0>;
sensor0_iovdd = "iovdd-csi";
sensor0_iovdd_vol = <2800000>;
sensor0_avdd = "avdd-csi";
sensor0_avdd_vol = <2800000>;
sensor0_dvdd = "dvdd-csi-18";
sensor0_dvdd_vol = <1500000>;
sensor0_power_en = <>;
sensor0_reset = <&pio PE 14 1 0 1 0>;
sensor0_pwdn = <&pio PE 16 1 0 1 0>;
flash_handle = <&flash0>;
act_handle = <&actuator0>;
status = "okay";
};
sensor1:sensor@1 {
device_type = "sensor1";
sensor1_mname = "ov5647";
sensor1_twi_cci_id = <1>;
sensor1_twi_addr = <0x6c>;
sensor1_pos = "front";
sensor1_isp_used = <0>;
sensor1_fmt = <0>;
sensor1_stby_mode = <0>;
sensor1_vflip = <0>;
sensor1_hflip = <0>;
sensor1_iovdd = "iovdd-csi";
sensor1_iovdd_vol = <2800000>;
sensor1_avdd = "avdd-csi";
sensor1_avdd_vol = <2800000>;
sensor1_dvdd = "dvdd-csi-18";
sensor1_dvdd_vol = <1500000>;
sensor1_power_en = <>;
sensor1_reset = <&pio PE 14 1 0 1 0>;
sensor1_pwdn = <&pio PE 15 1 0 1 0>;
flash_handle = <>;
act_handle = <>;
status = "okay";
};
vinc0:vinc@0 {
device_type = "vinc0";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609000 0x0 0x200>;
interrupts = <GIC_SPI 100 4>;
vinc0_csi_sel = <3>;
vinc0_mipi_sel = <0xff>;
vinc0_isp_sel = <0>;
vinc0_rear_sensor_sel = <0>;
vinc0_front_sensor_sel = <1>;
vinc0_sensor_list = <0>;
device_id = <0>;
status = "okay";
};
vinc1:vinc@1 {
device_type = "vinc1";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609200 0x0 0x200>;
interrupts = <GIC_SPI 101 4>;
vinc1_csi_sel = <3>;
vinc1_mipi_sel = <0xff>;
vinc1_isp_sel = <0>;
vinc1_rear_sensor_sel = <0>;
vinc1_front_sensor_sel = <1>;
vinc1_sensor_list = <0>;
device_id = <1>;
status = "okay";
};
vinc2:vinc@2 {
device_type = "vinc2";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609400 0x0 0x200>;
interrupts = <GIC_SPI 102 4>;
vinc2_csi_sel = <3>;
vinc2_mipi_sel = <0xff>;
vinc2_isp_sel = <1>;
vinc2_rear_sensor_sel = <0>;
vinc2_front_sensor_sel = <1>;
vinc2_sensor_list = <0>;
device_id = <2>;
status = "okay";
};
vinc3:vinc@3 {
device_type = "vinc3";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609600 0x0 0x200>;
interrupts = <GIC_SPI 103 4>;
vinc3_csi_sel = <3>;
vinc3_mipi_sel = <0xff>;
vinc3_isp_sel = <1>;
vinc3_rear_sensor_sel = <0>;
vinc3_front_sensor_sel = <1>;
vinc3_sensor_list = <0>;
device_id = <3>;
status = "okay";
};
vinc4:vinc@4 {
device_type = "vinc4";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609800 0x0 0x200>;
interrupts = <GIC_SPI 110 4>;
vinc4_csi_sel = <2>;
vinc4_mipi_sel = <0xff>;
vinc4_isp_sel = <0>;
vinc4_rear_sensor_sel = <0>;
vinc4_front_sensor_sel = <1>;
vinc4_sensor_list = <0>;
device_id = <4>;
status = "disabled";
};
vinc5:vinc@5 {
device_type = "vinc5";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609A00 0x0 0x200>;
interrupts = <GIC_SPI 111 4>;
vinc5_csi_sel = <2>;
vinc5_mipi_sel = <0xff>;
vinc5_isp_sel = <0>;
vinc5_rear_sensor_sel = <0>;
vinc5_front_sensor_sel = <1>;
vinc5_sensor_list = <0>;
device_id = <5>;
status = "disabled";
};
vinc6:vinc@6 {
device_type = "vinc6";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609C00 0x0 0x200>;
interrupts = <GIC_SPI 112 4>;
vinc6_csi_sel = <2>;
vinc6_mipi_sel = <0xff>;
vinc6_isp_sel = <0>;
vinc6_rear_sensor_sel = <0>;
vinc6_front_sensor_sel = <1>;
vinc6_sensor_list = <0>;
device_id = <6>;
status = "disabled";
};
vinc7:vinc@7 {
device_type = "vinc7";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609E00 0x0 0x200>;
interrupts = <GIC_SPI 113 4>;
vinc7_csi_sel = <2>;
vinc7_mipi_sel = <0xff>;
vinc7_isp_sel = <0>;
vinc7_rear_sensor_sel = <0>;
vinc7_front_sensor_sel = <1>;
vinc7_sensor_list = <0>;
device_id = <7>;
status = "disabled";
};
};
Vdevice: vdevice@0 {
compatible = "allwinner,sun8i-vdevice";
device_type = "Vdevice";
pinctrl-names = "default";
pinctrl-0 = <&vdevice_pins_a>;
test-gpios = <&pio PB 6 1 2 2 1>;
status = "okay";
};
cryptoengine: ce@0x01904000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x01904000 0x0 0xA0>, /* non-secure space */
<0x0 0x01904800 0x0 0xA0>; /* secure space */
interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, /* non-secure space */
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; /* secure space */
clock-frequency = <300000000>;
clocks = <&clk_ce>, <&clk_pll_periph0x2>;
};
di:deinterlace@0x01420000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-deinterlace";
reg = <0x0 0x01420000 0x0 0x1ffff>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_di> ,<&clk_pll_periph0>;
status = "okay";
};
pmu0: pmu@0{
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
powerkey0: powerkey@0{
status = "okay";
};
regulator0: regulator@0{
status = "okay";
};
axp_gpio0: axp_gpio@0{
gpio-controller;
#size-cells = <0>;
#gpio-cells = <6>;
status = "okay";
};
charger0: charger@0{
status = "ok";
};
};
scr0:smartcard@0x05005000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-scr";
reg = <0x0 0x05005000 0x0 0x400>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_scr>, <&clk_apb2>;
clock-frequency = <24000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&scr0_pins_a &scr0_pins_b>;
pinctrl-1 = <&scr0_pins_c>;
status = "disable";
};
nmi:nmi@0x01f00c00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-nmi";
reg = <0x0 0x01f00c00 0x0 0x50>;
nmi_irq_ctrl = <0x0c>;
nmi_irq_en = <0x40>;
nmi_irq_status = <0x10>;
nmi_irq_mask = <0x50>;
status = "okay";
};
nand0:nand0@04011000 {
compatible = "allwinner,sun8iw17-nand";
device_type = "nand0";
reg = <0x0 0x04011000 0x0 0x1000>;/* nand0 */
interrupts = <GIC_SPI 34 0x04>;
clocks = <&clk_pll_periph0x2>,<&clk_nand0>,<&clk_nand1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
pinctrl-1 = <&nand0_pins_c>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
status = "okay";
};
sunxi_thermal_sensor:thermal_sensor{
compatible = "allwinner,thermal_sensor";
reg = <0x0 0x07030400 0x0 0x100>;
interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
clocks = <&clk_cpur_vm_ths>,<&clk_cpurths>;
sensor_num = <4>;
combine_num = <2>;
shut_temp= <120>;
status = "okay";
ths_combine0:ths_combine0{
compatible = "allwinner,ths_combine0";
#thermal-sensor-cells = <1>;
combine_sensor_num = <2>;
combine_sensor_type = "CPU";
combine_sensor_temp_type = "max";
combine_sensor_id = <0 1>;
};
ths_combine1:ths_combine1{
compatible = "allwinner,ths_combine1";
#thermal-sensor-cells = <1>;
combine_sensor_num = <1>;
combine_sensor_type = "GPU";
combine_sensor_temp_type = "max";
combine_sensor_id = <3>;
};
};
cpu_budget_cooling:cpu_budget_cool{
compatible = "allwinner,budget_cooling";
device_type = "cpu_budget_cooling";
#cooling-cells = <2>;
status = "okay";
state_cnt = <6>;
cluster_num = <2>;
state0 = <1104000 3 1104000 3>;
state1 = <1008000 3 1008000 3>;
state2 = <912000 3 912000 3>;
state3 = <912000 3 912000 0>;
state4 = <720000 2 720000 0>;
state5 = <600000 1 600000 0>;
};
gpu_cooling:gpu_cooling{
compatible = "allwinner,gpu_cooling";
device_type = "gpu_cooling";
reg = <0x0 0x0 0x0 0x0>;
#cooling-cells = <2>;
status = "okay";
state_cnt = <4>;
state0 = <4>;
state1 = <3>;
state2 = <2>;
state3 = <1>;
};
thermal-zones{
cpu_thermal_zone0{
polling-delay-passive = <1000>;
polling-delay = <2000>;
thermal-sensors = <&ths_combine0 0>;
trips{
cpu_trip0:t0{
temperature = <60>;
type = "passive";
hysteresis = <0>;
};
cpu_trip1:t1{
temperature = <70>;
type = "passive";
hysteresis = <0>;
};
cpu_trip2:t2{
temperature = <80>;
type = "passive";
hysteresis = <0>;
};
cpu_trip3:t3{
temperature = <90>;
type = "passive";
hysteresis = <0>;
};
cpu_trip4:t4{
temperature = <100>;
type = "passive";
hysteresis = <0>;
};
crt_trip0:t5{
temperature = <120>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps{
bind0{
contribution = <0>;
trip = <&cpu_trip0>;
cooling-device = <&cpu_budget_cooling 1 1>;
};
bind1{
contribution = <0>;
trip = <&cpu_trip1>;
cooling-device = <&cpu_budget_cooling 2 2>;
};
bind2{
contribution = <0>;
trip = <&cpu_trip2>;
cooling-device = <&cpu_budget_cooling 3 3>;
};
bind3{
contribution = <0>;
trip = <&cpu_trip3>;
cooling-device = <&cpu_budget_cooling 4 4>;
};
bind4{
contribution = <0>;
trip = <&cpu_trip4>;
cooling-device = <&cpu_budget_cooling 5 5>;
};
};
};
gpu_thermal_zone{
polling-delay-passive = <1000>;
polling-delay = <2000>;
thermal-sensors = <&ths_combine1 1>;
trips{
gpu_trip0:t0{
temperature = <95>;
type = "passive";
hysteresis = <0>;
};
gpu_trip1:t1{
temperature = <100>;
type = "passive";
hysteresis = <0>;
};
gpu_trip2:t2{
temperature = <105>;
type = "passive";
hysteresis = <0>;
};
crt_trip1:t3{
temperature = <120>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps{
bind0{
contribution = <0>;
trip = <&gpu_trip0>;
cooling-device = <&gpu_cooling 1 1>;
};
bind1{
contribution = <0>;
trip = <&gpu_trip1>;
cooling-device = <&gpu_cooling 2 2>;
};
bind2{
contribution = <0>;
trip = <&gpu_trip2>;
cooling-device = <&gpu_cooling 3 3>;
};
};
};
};
gpadc:gpadc{
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x05070000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_NONE>;
clocks = <&clk_gpadc>;
status = "okay";
};
keyboard0:keyboard{
compatible = "allwinner,keyboard_2000mv";
reg = <0x0 0x07030800 0x0 0x400>;
interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
status = "okay";
key_cnt = <5>;
key0 = <190 115>;
key1 = <390 114>;
key2 = <600 139>;
key3 = <800 28>;
key4 = <980 102>;
};
gmac0: eth@05020000 {
compatible = "allwinner,sunxi-gmac";
reg = <0x0 0x05020000 0x0 0xFFFF>,
<0x0 0x03000030 0x0 0x4>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gmacirq";
clocks = <&clk_gmac>;
clock-names = "gmac";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&gmac_pins_a>;
pinctrl-1 = <&gmac_pins_b>;
phy-mode = "rgmii";
tx-delay = <7>;
rx-delay = <31>;
phy-rst;
gmac-power0;
gmac-power1;
gmac-power2;
status = "disable";
};
cpucfg@09010000 {
compatible = "allwinner,sunxi-cpucfg";
reg = <0x0 0x09010000 0x0 0x400>;
};
cpucfg@09810000 {
compatible = "allwinner,sunxi-cpucfg";
reg = <0x0 0x09810000 0x0 0x400>;
};
sysctl@03000000 {
compatible = "allwinner,sunxi-sysctl";
reg = <0x0 0x03000000 0x0 0x1000>;
};
cci400@03000000 {
compatible = "allwinner,sunxi-cci";
reg = <0x0 0x030d0000 0x0 0x20000>;
};
};
};
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