97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
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*
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* include/linux/dma/sunxi/dma-sun50iw8.h
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*
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* Copyright (C) 2017 Allwinner.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __DMA_SUN50IW8__
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#define __DMA_SUN50IW8__
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/*
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* The source DRQ type and port corresponding relation
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*/
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#define DRQSRC_SRAM 0
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#define DRQSRC_SDRAM 0
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/* #define DRQSRC_RESEVER 2 */
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#define DRQSRC_DAUDIO_0_RX 3
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#define DRQSRC_DAUDIO_1_RX 4
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/* #define DRQSRC_DAUDIO_2_RX 5 */
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#define DRQSRC_AUDIO_CODEC 6
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#define DRQSRC_DMIC 7
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/* #define DRQSRC_RESEVER 8 */
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/* #define DRQSRC_RESEVER 9 */
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#define DRQSRC_NAND0 10
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/* #define DRQSRC_RESEVER 11 */
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#define DRQSRC_GPADC 12
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/* #define DRQSRC_RESEVER 13 */
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#define DRQSRC_UART0_RX 14
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#define DRQSRC_UART1_RX 15
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#define DRQSRC_UART2_RX 16
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#define DRQSRC_UART3_RX 17
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#define DRQSRC_UART4_RX 18
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/* #define DRQSRC_RESEVER 19 */
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/* #define DRQSRC_RESEVER 20 */
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/* #define DRQSRC_RESEVER 21 */
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#define DRQSRC_SPI0_RX 22
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#define DRQSRC_SPI1_RX 23
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/* #define DRQSRC_SPI2_RX 24 */
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/* #define DRQSRC_SPI3_RX 25 */
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/* #define DRQSRC_RESEVER 26 */
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/* #define DRQSRC_RESEVER 27 */
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/* #define DRQSRC_RESEVER 28 */
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/* #define DRQSRC_RESEVER 29 */
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#define DRQSRC_OTG_EP1 30
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#define DRQSRC_OTG_EP2 31
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#define DRQSRC_OTG_EP3 32
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#define DRQSRC_OTG_EP4 33
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#define DRQSRC_OTG_EP5 34
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/*
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* The destination DRQ type and port corresponding relation
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*/
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#define DRQDST_SRAM 0
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#define DRQDST_SDRAM 0
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/* #define DRQSRC_RESEVER 2 */
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#define DRQDST_DAUDIO_0_TX 3
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#define DRQDST_DAUDIO_1_TX 4
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/* #define DRQDST_DAUDIO_2_TX 5 */
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#define DRQDST_AUDIO_CODEC 6
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/* #define DRQSRC_RESEVER 7 */
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/* #define DRQSRC_RESEVER 8 */
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/* #define DRQSRC_RESEVER 9 */
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#define DRQDST_NAND0 10
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/* #define DRQSRC_RESEVER 11 */
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/* #define DRQSRC_RESEVER 12 */
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/* #define DRQDST_IR_TX 13 */
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#define DRQDST_UART0_TX 14
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#define DRQDST_UART1_TX 15
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#define DRQDST_UART2_TX 16
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#define DRQDST_UART3_TX 17
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#define DRQDST_UART4_TX 18
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/* #define DRQSRC_RESEVER 19 */
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/* #define DRQSRC_RESEVER 20 */
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/* #define DRQSRC_RESEVER 21 */
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#define DRQDST_SPI0_TX 22
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#define DRQDST_SPI1_TX 23
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/* #define DRQDST_SPI2_TX 24 */
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/* #define DRQDST_SPI3_TX 25 */
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/* #define DRQSRC_RESEVER 26 */
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/* #define DRQSRC_RESEVER 27 */
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/* #define DRQSRC_RESEVER 28 */
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/* #define DRQSRC_RESEVER 29 */
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#define DRQDST_OTG_EP1 30
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#define DRQDST_OTG_EP2 31
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#define DRQDST_OTG_EP3 32
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#define DRQDST_OTG_EP4 33
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#define DRQDST_OTG_EP5 34
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#endif /*__DMA_SUN50IW8__ */
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