114 lines
3.2 KiB
C
114 lines
3.2 KiB
C
/*
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* Allwinner sun50iw6p1 SoCs R_PIO pinctrl driver.
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*
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* Copyright(c) 2012-2016 Allwinnertech Co., Ltd.
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* Author: WimHuang <huangwei@allwinnertech.com>
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*
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DMA_SUN50IW6__
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#define __DMA_SUN50IW6__
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#define DRQSRC_SRAM 0
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#define DRQSRC_SDRAM DRQSRC_SRAM
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#define DRQSRC_DRAM 1
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#define DRQSRC_SPDIFRX 2
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#define DRQSRC_OWARX DRQSRC_SPDIFRX
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#define DRQSRC_DAUDIO_0_RX 3
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#define DRQSRC_DAI0_RX DRQSRC_DAUDIO_0_RX
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#define DRQSRC_DAUDIO_1_RX 4
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#define DRQSRC_DAI1_RX DRQSRC_DAUDIO_1_RX
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#define DRQSRC_DAUDIO_2_RX 5
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#define DRQSRC_DAI2_RX DRQSRC_DAUDIO_2_RX
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#define DRQSRC_DAUDIO_3_RX 6
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#define DRQSRC_DAI3_RX DRQSRC_DAUDIO_3_RX
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#define DRQSRC_DMIC 7
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/* #define DRQSRC_RESEVER 8 */
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#define DRQSRC_SS 9
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#define DRQSRC_CE_RX DRQSRC_SS
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#define DRQSRC_NAND0 10
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/* #define DRQSRC_RESEVER 11 */
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/* #define DRQSRC_RESEVER 12 */
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/* #define DRQSRC_RESEVER 13 */
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#define DRQSRC_UART0RX 14
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#define DRQSRC_UART1RX 15
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#define DRQSRC_UART2RX 16
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#define DRQSRC_UART3RX 17
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/* #define DRQSRC_RESEVER 18 */
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/* #define DRQSRC_RESEVER 19 */
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/* #define DRQSRC_RESEVER 20 */
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/* #define DRQSRC_RESEVER 21 */
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#define DRQSRC_SPI0_RX 22
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#define DRQSRC_SPI1_RX 23
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/* #define DRQSRC_RESEVER 24 */
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/* #define DRQSRC_RESEVER 25 */
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/* #define DRQSRC_RESEVER 26 */
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/* #define DRQSRC_RESEVER 27 */
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/* #define DRQSRC_RESEVER 28 */
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/* #define DRQSRC_RESEVER 29 */
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#define DRQSRC_OTG_EP1 30
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#define DRQSRC_OTG_EP2 31
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#define DRQSRC_OTG_EP3 32
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#define DRQSRC_OTG_EP4 33
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#define DRQSRC_OTG_EP5 34
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/* Add by wolfgang to support Audio Hub */
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#define DRQSRC_AHUB0_RX 43
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#define DRQSRC_AHUB1_RX 44
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#define DRQSRC_AHUB2_RX 45
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/*
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* The destination DRQ type and port corresponding relation
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*
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*/
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#define DRQDST_SRAM 0
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#define DRQDST_SDRAM DRQDST_SRAM
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#define DRQDST_DRAM 1
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#define DRQDST_SPDIFTX 2
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#define DRQDST_OWATX DRQDST_SPDIFTX
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#define DRQDST_DAUDIO_0_TX 3
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#define DRQDST_DAI0_TX DRQDST_DAUDIO_0_TX
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#define DRQDST_DAUDIO_1_TX 4
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#define DRQDST_DAI1_TX DRQDST_DAUDIO_1_TX
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#define DRQDST_DAUDIO_2_TX 5
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#define DRQDST_DAI2_TX DRQDST_DAUDIO_2_TX
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#define DRQDST_DAUDIO_3_TX 6
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#define DRQDST_DAI3_TX DRQDST_DAUDIO_3_TX
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/* #define DRQDST_RESEVER 7 */
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/* #define DRQDST_RESEVER 8 */
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#define DRQDST_SS 9
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#define DRQDST_CE_TX DRQDST_SS
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#define DRQDST_NAND0 10
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/* #define DRQDST_RESEVER 11 */
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/* #define DRQDST_RESEVER 12 */
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#define DRQDST_IR0TX 13
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#define DRQDST_UART0TX 14
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#define DRQDST_UART1TX 15
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#define DRQDST_UART2TX 16
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#define DRQDST_UART3TX 17
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/* #define DRQDST_RESEVER 18 */
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/* #define DRQDST_RESEVER 19 */
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/* #define DRQDST_RESEVER 20 */
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/* #define DRQDST_RESEVER 21 */
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#define DRQDST_SPI0_TX 22
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#define DRQDST_SPI1_TX 23
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/* #define DRQDST_RESEVER 24 */
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/* #define DRQDST_RESEVER 25 */
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/* #define DRQDST_RESEVER 26 */
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/* #define DRQDST_RESEVER 27 */
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/* #define DRQDST_RESEVER 28 */
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/* #define DRQDST_RESEVER 29 */
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#define DRQDST_OTG_EP1 30
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#define DRQDST_OTG_EP2 31
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#define DRQDST_OTG_EP3 32
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#define DRQDST_OTG_EP4 33
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#define DRQDST_OTG_EP5 34
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/* Add by wolfgang to support Audio Hub */
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#define DRQDST_AHUB0_TX 43
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#define DRQDST_AHUB1_TX 44
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#define DRQDST_AHUB2_TX 45
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#endif /*__DMA_SUN50IW6__ */
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