2103 lines
52 KiB
Plaintext
2103 lines
52 KiB
Plaintext
/*
|
|
* Allwinner Technology CO., Ltd. sun50iw3p1 platform
|
|
*
|
|
* modify base on juno.dts
|
|
*/
|
|
|
|
/* kernel used */
|
|
/memreserve/ 0x40020000 0x00001000; /* super standby range : [0x40020000~0x41021000], size = 4K */
|
|
/memreserve/ 0x48000000 0x02000000; /* atf : [0x48000000~0x4A000000], size = 32M */
|
|
|
|
/* tf used */
|
|
/memreserve/ 0x48100000 0x00004000; /* arisc dram code space range: [0x48100000~0x48104000], size = 16K */
|
|
/memreserve/ 0x48104000 0x00001000; /* arisc para cfg range : [0x481040ERR0x48105000], size = 4K */
|
|
/memreserve/ 0x48105000 0x00001000; /* arisc message pool range : [0x48105000~0x48106000], size = 4K */
|
|
/* ramoops used */
|
|
/memreserve/ 0x48106000 0x00060000; /* ramoops range : [0x48106000~0x48166000], size = 384K */
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include "sun50iw3p1-clk.dtsi"
|
|
#include "sun50iw3p1-pinctrl.dtsi"
|
|
/ {
|
|
model = "sun50iw3";
|
|
compatible = "arm,sun50iw3p1";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
serial2 = &uart2;
|
|
serial3 = &uart3;
|
|
twi0 = &twi0;
|
|
twi1 = &twi1;
|
|
twi2 = &twi2;
|
|
twi3 = &twi3;
|
|
twi4 = &twi4;
|
|
spi0 = &spi0;
|
|
spi1 = &spi1;
|
|
|
|
global_timer0 = &soc_timer0;
|
|
mmc0 = &sdc0;
|
|
mmc2 = &sdc2;
|
|
nand0 =&nand0;
|
|
disp = &disp;
|
|
lcd0 = &lcd0;
|
|
lcd1 = &lcd1;
|
|
edp0 = &edp0;
|
|
hdmi = &hdmi;
|
|
pwm = &pwm;
|
|
pwm0 = &pwm0;
|
|
tv0 = &tv0;
|
|
s_pwm = &s_pwm;
|
|
spwm0 = &spwm0;
|
|
boot_disp = &boot_disp;
|
|
charger0 = &charger0;
|
|
regulator0 = ®ulator0;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
|
|
linux,initrd-start = <0x0 0x0>;
|
|
linux,initrd-end = <0x0 0x0>;
|
|
};
|
|
|
|
firmware {
|
|
android {
|
|
compatible = "android,firmware";
|
|
name = "android";
|
|
fstab {
|
|
compatible = "android,fstab";
|
|
name = "fstab";
|
|
vendor {
|
|
compatible = "android,vendor";
|
|
dev = "/dev/block/by-name/vendor";
|
|
fsmgr_flags = "wait,verify=/dev/block/by-name/metadata";
|
|
mnt_flags = "ro,barrier=1";
|
|
name = "vendor";
|
|
status = "ok";
|
|
type = "ext4";
|
|
};
|
|
system {
|
|
compatible = "android,system";
|
|
dev = "/dev/block/by-name/system";
|
|
fsmgr_flags = "wait,verify=/dev/block/by-name/metadata";
|
|
mnt_flags = "ro,barrier=1";
|
|
name = "system";
|
|
status = "ok";
|
|
type = "ext4";
|
|
};
|
|
};
|
|
};
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53","arm,armv8";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
clocks = <&clk_pll_cpu>;
|
|
clock-latency = <2000000>;
|
|
clock-frequency = <1440000000>;
|
|
operating-points-v2 =
|
|
<&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
|
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53","arm,armv8";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
clocks = <&clk_pll_cpu>;
|
|
clock-frequency = <1440000000>;
|
|
operating-points-v2 =
|
|
<&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
|
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53","arm,armv8";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
clocks = <&clk_pll_cpu>;
|
|
clock-frequency = <1440000000>;
|
|
operating-points-v2 =
|
|
<&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
|
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53","arm,armv8";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
clocks = <&clk_pll_cpu>;
|
|
clock-frequency = <1440000000>;
|
|
operating-points-v2 =
|
|
<&cpu_opp_l_table0 &cpu_opp_l_table1 &cpu_opp_l_table2>;
|
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "arm,psci";
|
|
|
|
CPU_SLEEP_0: cpu-sleep-0 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x0010000>;
|
|
entry-latency-us = <40>;
|
|
exit-latency-us = <100>;
|
|
min-residency-us = <150>;
|
|
};
|
|
|
|
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x1010000>;
|
|
entry-latency-us = <500>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2500>;
|
|
};
|
|
|
|
SYS_SLEEP_0: sys-sleep-0 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x2010000>;
|
|
entry-latency-us = <1000>;
|
|
exit-latency-us = <2000>;
|
|
min-residency-us = <4500>;
|
|
};
|
|
};
|
|
};
|
|
|
|
psensor_table: psensor_table {
|
|
psensor_count = <3>;
|
|
prange_min_2 = <4800>;
|
|
prange_max_2 = <6500>;
|
|
prange_min_1 = <4500>;
|
|
prange_max_1 = <4800>;
|
|
prange_min_0 = <0>;
|
|
prange_max_0 = <4500>;
|
|
};
|
|
|
|
opp_dvfs_table:opp_dvfs_table {
|
|
cluster_num = <1>;
|
|
opp_table_count = <3>;
|
|
|
|
cpu_opp_l_table0: opp_l_table0 {
|
|
/* compatible = "operating-points-v2"; */
|
|
compatible = "allwinner,opp_l_table0";
|
|
opp_count = <10>;
|
|
opp-shared;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <480000000>;
|
|
opp-microvolt = <840000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <720000000>;
|
|
opp-microvolt = <840000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <816000000>;
|
|
opp-microvolt = <840000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <1008000000>;
|
|
opp-microvolt = <840000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <1200000000>;
|
|
opp-microvolt = <900000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <1416000000>;
|
|
opp-microvolt = <960000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <1440000000>;
|
|
opp-microvolt = <1000000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <1512000000>;
|
|
opp-microvolt = <1000000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp08 {
|
|
opp-hz = /bits/ 64 <1608000000>;
|
|
opp-microvolt = <1120000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp09 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <1120000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
};
|
|
|
|
cpu_opp_l_table1: opp_l_table1 {
|
|
/* compatible = "operating-points-v2"; */
|
|
compatible = "allwinner,opp_l_table1";
|
|
opp_count = <10>;
|
|
opp-shared;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <480000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <720000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <816000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <1008000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <1200000000>;
|
|
opp-microvolt = <840000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <1416000000>;
|
|
opp-microvolt = <920000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <1440000000>;
|
|
opp-microvolt = <960000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <1512000000>;
|
|
opp-microvolt = <960000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp08 {
|
|
opp-hz = /bits/ 64 <1608000000>;
|
|
opp-microvolt = <1040000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp09 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <1040000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
};
|
|
|
|
cpu_opp_l_table2: opp_l_table2 {
|
|
/* compatible = "operating-points-v2"; */
|
|
compatible = "allwinner,opp_l_table2";
|
|
opp_count = <10>;
|
|
opp-shared;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <480000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <720000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <816000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <1008000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <1200000000>;
|
|
opp-microvolt = <820000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <1416000000>;
|
|
opp-microvolt = <800000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <1440000000>;
|
|
opp-microvolt = <920000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <1512000000>;
|
|
opp-microvolt = <920000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp08 {
|
|
opp-hz = /bits/ 64 <1608000000>;
|
|
opp-microvolt = <1000000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
|
|
opp09 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <1000000>;
|
|
axi-bus-divide-ratio = <3>;
|
|
clock-latency-ns = <2000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
psci_version = <0x84000000>;
|
|
cpu_suspend = <0xc4000001>;
|
|
cpu_off = <0x84000002>;
|
|
cpu_on = <0xc4000003>;
|
|
affinity_info = <0xc4000004>;
|
|
migrate = <0xc4000005>;
|
|
migrate_info_type = <0x84000006>;
|
|
migrate_info_up_cpu = <0xc4000007>;
|
|
system_off = <0x84000008>;
|
|
system_reset = <0x84000009>;
|
|
};
|
|
|
|
n_brom {
|
|
compatible = "allwinner,n-brom";
|
|
reg = <0x0 0x0 0x0 0xc000>;
|
|
};
|
|
|
|
s_brom {
|
|
compatible = "allwinner,s-brom";
|
|
reg = <0x0 0x0 0x0 0x10000>;
|
|
};
|
|
|
|
sram_ctrl {
|
|
device_type = "sram_ctrl";
|
|
compatible = "allwinner,sram_ctrl";
|
|
reg = <0x0 0x03000000 0x0 0x100>;
|
|
};
|
|
|
|
sram_a1 {
|
|
compatible = "allwinner,sram_a1";
|
|
reg = <0x0 0x00020000 0x0 0x8000>;
|
|
};
|
|
|
|
sram_a2 {
|
|
compatible = "allwinner,sram_a2";
|
|
reg = <0x0 0x00100000 0x0 0x40000>;
|
|
};
|
|
|
|
prcm {
|
|
compatible = "allwinner,prcm";
|
|
reg = <0x0 0x07010000 0x0 0x400>;
|
|
};
|
|
|
|
s_cpuscfg {
|
|
compatible = "allwinner,s_cpuscfg";
|
|
reg = <0x0 0x07000400 0x0 0x800>;
|
|
};
|
|
|
|
ion {
|
|
compatible = "allwinner,sunxi-ion";
|
|
/*types is list here:
|
|
ION_HEAP_TYPE_SYSTEM = 0,
|
|
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
|
|
ION_HEAP_TYPE_CARVEOUT = 2,
|
|
ION_HEAP_TYPE_CHUNK = 3,
|
|
ION_HEAP_TYPE_DMA = 4,
|
|
ION_HEAP_TYPE_SECURE = 5,
|
|
**/
|
|
heap_sys_user@0{
|
|
compatible = "allwinner,sys_user";
|
|
heap-name = "sys_user";
|
|
heap-id = <0x0>;
|
|
heap-base = <0x0>;
|
|
heap-size = <0x0>;
|
|
heap-type = "ion_system";
|
|
};
|
|
heap_sys_contig@0{
|
|
compatible = "allwinner,sys_contig";
|
|
heap-name = "sys_contig";
|
|
heap-id = <0x1>;
|
|
heap-base = <0x0>;
|
|
heap-size = <0x0>;
|
|
heap-type = "ion_contig";
|
|
};
|
|
heap_cma@0{
|
|
compatible = "allwinner,cma";
|
|
heap-name = "cma";
|
|
heap-id = <0x4>;
|
|
heap-base = <0x0>;
|
|
heap-size = <0x0>;
|
|
heap-type = "ion_cma";
|
|
};
|
|
heap_secure@0{
|
|
compatible = "allwinner,secure";
|
|
heap-name = "secure";
|
|
heap-id = <0x5>;
|
|
heap-base = <0x0>;
|
|
heap-size = <0x0>;
|
|
heap-type = "ion_secure";
|
|
};
|
|
};
|
|
|
|
dram: dram {
|
|
compatible = "allwinner,dram";
|
|
clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>;
|
|
clock-names = "pll_ddr0", "pll_ddr1";
|
|
dram_clk = <672>;
|
|
dram_type = <3>;
|
|
dram_zq = <0x003F3FDD>;
|
|
dram_odt_en = <1>;
|
|
dram_para1 = <0x10f41000>;
|
|
dram_para2 = <0x00001200>;
|
|
dram_mr0 = <0x1A50>;
|
|
dram_mr1 = <0x40>;
|
|
dram_mr2 = <0x10>;
|
|
dram_mr3 = <0>;
|
|
dram_tpr0 = <0x04E214EA>;
|
|
dram_tpr1 = <0x004214AD>;
|
|
dram_tpr2 = <0x10A75030>;
|
|
dram_tpr3 = <0>;
|
|
dram_tpr4 = <0>;
|
|
dram_tpr5 = <0>;
|
|
dram_tpr6 = <0>;
|
|
dram_tpr7 = <0>;
|
|
dram_tpr8 = <0>;
|
|
dram_tpr9 = <0>;
|
|
dram_tpr10 = <0>;
|
|
dram_tpr11 = <0>;
|
|
dram_tpr12 = <168>;
|
|
dram_tpr13 = <0x823>;
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x40000000 0x00000000 0x3f000000>;
|
|
};
|
|
|
|
gic: interrupt-controller@03020000 {
|
|
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
device_type = "gic";
|
|
interrupt-controller;
|
|
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
|
|
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
|
|
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
|
|
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
|
|
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
|
|
};
|
|
|
|
wakeupgen: interrupt-controller {
|
|
compatible = "allwinner,sunxi-wakeupgen";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
space1 = <0x40020800 0x800>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
sid: sunxi-sid@03006000 {
|
|
compatible = "allwinner,sunxi-sid";
|
|
device_type = "sid";
|
|
reg = <0x0 0x03006000 0 0x1000>;
|
|
};
|
|
|
|
chipid: sunxi-chipid@03006200 {
|
|
compatible = "allwinner,sunxi-chipid";
|
|
device_type = "chipid";
|
|
reg = <0x0 0x03006200 0 0x0200>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <24000000>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_SPI 140 4>,
|
|
<GIC_SPI 141 4>,
|
|
<GIC_SPI 142 4>,
|
|
<GIC_SPI 143 4>;
|
|
};
|
|
|
|
dramfreq {
|
|
compatible = "allwinner,sunxi-dramfreq";
|
|
reg = <0x0 0x04002000 0x0 0x160>,
|
|
<0x0 0x04003000 0x0 0x4d0>,
|
|
<0x0 0x03001000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 31 0x4>;
|
|
clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>, <&clk_ahb1>;
|
|
status = "okay";
|
|
};
|
|
|
|
uboot: uboot {
|
|
};
|
|
|
|
mmu_aw: iommu@030f0000 {
|
|
compatible = "allwinner,sunxi-iommu";
|
|
reg = <0x0 0x030f0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "iommu-irq";
|
|
clocks = <&clk_iommu>;
|
|
clock-names = "iommu";
|
|
/* clock-frequency = <24000000>; */
|
|
#iommu-cells = <2>;
|
|
status = "okay";
|
|
};
|
|
|
|
soc: soc@03000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
device_type = "soc";
|
|
|
|
dma0:dma-controller@03002000 {
|
|
compatible = "allwinner,sun50i-dma";
|
|
reg = <0x0 0x03002000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_dma>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
mbus0: mbus-controller@04002000 {
|
|
compatible = "allwinner,sun50i-mbus";
|
|
reg = <0x0 0x04002000 0x0 0x1000>;
|
|
#mbus-cells = <1>;
|
|
};
|
|
|
|
arisc {
|
|
compatible = "allwinner,sunxi-arisc";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>;
|
|
clock-names = "losc", "iosc", "hosc", "pll_periph0";
|
|
powchk_used = <0x0>;
|
|
power_reg = <0x02309621>;
|
|
system_power = <50>;
|
|
};
|
|
|
|
arisc_space {
|
|
compatible = "allwinner,arisc_space";
|
|
/* num dst offset size */
|
|
space1 = <0x48040000 0x00000000 0x00014000>; /* srama2 code space */
|
|
space2 = <0x48100000 0x00018000 0x00004000>; /* dram code space */
|
|
space3 = <0x48104000 0x00000000 0x00001000>; /* para space */
|
|
space4 = <0x48105000 0x00000000 0x00001000>; /* msgpool space */
|
|
};
|
|
|
|
nanohub: nanohub@0 {
|
|
compatible = "allwinner,nanohub";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
|
|
status = "okay";
|
|
};
|
|
|
|
standby_space {
|
|
compatible = "allwinner,sun50iw3-superstandby";
|
|
/* num dst offset size */
|
|
space1 = <0x40020000 0x00000000 0x00000800>; /* super standby para space */
|
|
};
|
|
|
|
msgbox: msgbox@03003000 {
|
|
compatible = "allwinner,msgbox";
|
|
clocks = <&clk_msgbox>;
|
|
clock-names = "clk_msgbox";
|
|
reg = <0x0 0x03003000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
|
|
status = "okay";
|
|
};
|
|
|
|
hwspinlock: hwspinlock@03004000 {
|
|
compatible = "allwinner,sunxi-hwspinlock";
|
|
clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>;
|
|
clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
|
|
reg = <0x0 0x03004000 0x0 0x1000>;
|
|
num-locks = <8>; /* the number hwspinlock we needed, max 32 */
|
|
status = "okay";
|
|
};
|
|
|
|
s_uart0: s_uart@07080000 {
|
|
compatible = "allwinner,s_uart";
|
|
reg = <0x0 0x07080000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_uart0_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
s_twi0: s_twi@07081400 {
|
|
compatible = "allwinner,s_twi";
|
|
reg = <0x0 0x07081400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_twi0_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
s_twi1: s_twi@07081800 {
|
|
compatible = "allwinner,s_twi";
|
|
reg = <0x0 0x07081800 0x0 0x400>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_twi1_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
s_twi2: s_twi@07081c00 {
|
|
compatible = "allwinner,s_twi";
|
|
reg = <0x0 0x07081c00 0x0 0x400>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_twi2_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
s_rsb0: s_rsb@07083000 {
|
|
compatible = "allwinner,s_rsb";
|
|
reg = <0x0 0x07083000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_rsb0_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
s_spi0: s_spi@07013000 {
|
|
compatible = "allwinner,s_spi";
|
|
reg = <0x0 0x07013000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_spi0_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
s_jtag0: s_jtag0 {
|
|
compatible = "allwinner,s_jtag";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&s_jtag0_pins_a>;
|
|
status = "disable";
|
|
};
|
|
|
|
box_start_os: box_start_os0 {
|
|
compatible = "allwinner,box_start_os";
|
|
start_type = <0x0>;
|
|
irkey_used = <0x0>;
|
|
pmukey_used = <0x0>;
|
|
pmukey_num = <0x0>;
|
|
led_power = <0x0>;
|
|
led_state = <0x0>;
|
|
status = "disable";
|
|
};
|
|
|
|
soc_timer0: timer@03009000 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
device_type = "soc_timer";
|
|
reg = <0x0 0x03009000 0x0 0x94>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <24000000>;
|
|
timer-prescale = <16>;
|
|
clocks = <&clk_losc>, <&clk_hosc>;
|
|
};
|
|
|
|
rtc: rtc@07000000 {
|
|
compatible = "allwinner,sun50iw3-rtc";
|
|
device_type = "rtc";
|
|
reg = <0x0 0x7000000 0x0 0x220>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpr_offset = <0x100>;
|
|
gpr_len = <8>;
|
|
gpr_cur_pos = <6>;
|
|
};
|
|
|
|
wdt: watchdog@030090a0 {
|
|
compatible = "allwinner,sun50i-wdt";
|
|
reg = <0x0 0x030090a0 0x0 0x20>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ve: ve@01c0e000 {
|
|
compatible = "allwinner,sunxi-cedar-ve";
|
|
reg = <0x0 0x01c0e000 0x0 0x1000>,
|
|
<0x0 0x03000000 0x0 0x10>,
|
|
<0x0 0x03001000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_pll_ve>, <&clk_ve>;
|
|
/* iommus = <&mmu_aw 3 1>; */
|
|
};
|
|
vp9: vp9@01c00000 {
|
|
compatible = "allwinner,sunxi-google-vp9";
|
|
reg = <0x0 0x01c00000 0x0 0x1000>,
|
|
<0x0 0x03000000 0x0 0x10>,
|
|
<0x0 0x03001000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
#clocks = <&clk_pll_ve>, <&clk_vp9>;
|
|
clocks = <&clk_pll_periph0x2>, <&clk_vp9>;
|
|
/* iommus = <&mmu_aw 5 1>; */
|
|
};
|
|
|
|
uart0: uart@05000000 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
device_type = "uart0";
|
|
reg = <0x0 0x05000000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_uart0>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&uart0_pins_a>;
|
|
pinctrl-1 = <&uart0_pins_b>;
|
|
uart0_port = <0>;
|
|
uart0_type = <2>;
|
|
status = "okay";
|
|
};
|
|
|
|
uart1: uart@05000400 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
device_type = "uart1";
|
|
reg = <0x0 0x05000400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_uart1>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&uart1_pins_a>;
|
|
pinctrl-1 = <&uart1_pins_b>;
|
|
uart1_port = <1>;
|
|
uart1_type = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: uart@05000800 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
device_type = "uart2";
|
|
reg = <0x0 0x05000800 0x0 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_uart2>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&uart2_pins_a>;
|
|
pinctrl-1 = <&uart2_pins_b>;
|
|
uart2_port = <2>;
|
|
uart2_type = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: uart@05000c00 {
|
|
compatible = "allwinner,sun50i-uart";
|
|
device_type = "uart3";
|
|
reg = <0x0 0x05000c00 0x0 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_uart3>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&uart3_pins_a>;
|
|
pinctrl-1 = <&uart3_pins_b>;
|
|
uart3_port = <3>;
|
|
uart3_type = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
twi0: twi@0x05002000{
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi0";
|
|
reg = <0x0 0x05002000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_twi0>;
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&twi0_pins_a>;
|
|
pinctrl-1 = <&twi0_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
|
|
twi1: twi@0x05002400{
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi1";
|
|
reg = <0x0 0x05002400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_twi1>;
|
|
clock-frequency = <200000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&twi1_pins_a>;
|
|
pinctrl-1 = <&twi1_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
|
|
twi2: twi@0x05002800{
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi2";
|
|
reg = <0x0 0x05002800 0x0 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_twi2>;
|
|
clock-frequency = <200000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&twi2_pins_a>;
|
|
pinctrl-1 = <&twi2_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
twi3: twi@0x05002c00{
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi3";
|
|
reg = <0x0 0x05002c00 0x0 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_twi3>;
|
|
clock-frequency = <200000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&twi3_pins_a>;
|
|
pinctrl-1 = <&twi3_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
|
|
twi4: twi@0x05003000{
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-twi";
|
|
device_type = "twi4";
|
|
reg = <0x0 0x05003000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_twi4>;
|
|
clock-frequency = <200000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&twi4_pins_a>;
|
|
pinctrl-1 = <&twi4_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbc0:usbc0@0 {
|
|
device_type = "usbc0";
|
|
compatible = "allwinner,sunxi-otg-manager";
|
|
usb_port_type = <2>;
|
|
usb_detect_type = <1>;
|
|
usb_id_gpio;
|
|
usb_det_vbus_gpio;
|
|
usb_drv_vbus_gpio;
|
|
usb_host_init_state = <0>;
|
|
usb_regulator_io = "nocare";
|
|
usb_wakeup_suspend = <0>;
|
|
usb_luns = <3>;
|
|
usb_serial_unique = <0>;
|
|
usb_serial_number = "20080411";
|
|
rndis_wceis = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
udc:udc-controller@0x05100000 {
|
|
compatible = "allwinner,sunxi-udc";
|
|
reg = <0x0 0x05100000 0x0 0x1000>, /*udc base*/
|
|
<0x0 0x00000000 0x0 0x100>; /*sram base*/
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_usbphy0>, <&clk_usbotg>;
|
|
status = "okay";
|
|
};
|
|
|
|
ehci0:ehci0-controller@0x05101000 {
|
|
compatible = "allwinner,sunxi-ehci0";
|
|
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
|
|
<0x0 0x00000000 0x0 0x100>, /*sram base*/
|
|
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
|
|
hci_ctrl_no = <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
ohci0:ohci0-controller@0x05101400 {
|
|
compatible = "allwinner,sunxi-ohci0";
|
|
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
|
|
<0x0 0x00000000 0x0 0x100>, /*sram base*/
|
|
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
|
|
hci_ctrl_no = <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
usbc1:usbc1@0 {
|
|
device_type = "usbc1";
|
|
usb_drv_vbus_gpio;
|
|
usb_host_init_state = <1>;
|
|
usb_regulator_io = "nocare";
|
|
usb_wakeup_suspend = <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
ehci1:ehci1-controller@0x05200000 {
|
|
compatible = "allwinner,sunxi-ehci1";
|
|
reg = <0x0 0x05200000 0x0 0xFFF>,/*hci1 base*/
|
|
<0x0 0x00000000 0x0 0x100>, /*sram base*/
|
|
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_usbphy1>, <&clk_usbehci1>;
|
|
hci_ctrl_no = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
ohci1:ohci1-controller@0x05200400 {
|
|
compatible = "allwinner,sunxi-ohci1";
|
|
reg = <0x0 0x05200000 0x0 0xFFF>, /*hci1 base*/
|
|
<0x0 0x00000000 0x0 0x100>, /*sram base*/
|
|
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_usbphy1>, <&clk_usbohci1>, <&clk_usbohci1_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
|
|
hci_ctrl_no = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
codec:codec@0x05096000 {
|
|
compatible = "allwinner,sunxi-internal-codec";
|
|
reg = <0x0 0x05096000 0x0 0x478>,/*digital baseadress*/
|
|
<0x0 0x07010280 0x0 0x4>;/*analog baseadress*/
|
|
clocks = <&clk_pll_audio>,<&clk_codec_1x>;
|
|
|
|
pinctrl-names = "aif2-default","aif3-default","aif2-sleep","aif3-sleep";
|
|
pinctrl-0 = <&aif2_pins_a>;
|
|
pinctrl-1 = <&aif3_pins_a>;
|
|
pinctrl-2 = <&aif2_pins_b>;
|
|
pinctrl-3 = <&aif3_pins_b>;
|
|
|
|
/*gpio-spk=<&pio 6 7 0>;*/
|
|
gpio-spk = <&pio PH 7 1 1 1 1>;
|
|
|
|
headphonevol = <0x3b>;
|
|
spkervol = <0x1b>;
|
|
earpiecevol = <0x1e>;
|
|
maingain = <0x4>;
|
|
headsetmicgain = <0x4>;
|
|
adcagc_cfg = <0x0>;
|
|
adcdrc_cfg = <0x0>;
|
|
adchpf_cfg = <0x0>;
|
|
dacdrc_cfg = <0x0>;
|
|
dachpf_cfg = <0x0>;
|
|
aif1_lrlk_div = <0x40>;
|
|
aif2_lrlk_div = <0x40>;
|
|
aif2config = <0x0>;
|
|
aif3config = <0x0>;
|
|
pa_sleep_time = <0x15e>;
|
|
dac_digital_vol = <0xa0a0>;
|
|
status = "okay";
|
|
};
|
|
|
|
i2s:i2s0-controller@0x05096000 {
|
|
compatible = "allwinner,sunxi-internal-i2s";
|
|
reg = <0x0 0x05096000 0x0 0x478>;/*digital baseadress*/
|
|
clocks = <&clk_pll_audio>,<&clk_codec_1x>;
|
|
status = "okay";
|
|
};
|
|
|
|
daudio0:daudio@0x05090000 {
|
|
compatible = "allwinner,sunxi-daudio";
|
|
reg = <0x0 0x05090000 0x0 0x58>;
|
|
clocks = <&clk_pll_audio>,<&clk_i2s0>;
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&daudio0_pins_a>;
|
|
pinctrl-1 = <&daudio0_pins_b>;
|
|
pcm_lrck_period = <0x20>;
|
|
pcm_lrckr_period = <0x01>;
|
|
slot_width_select = <0x20>;
|
|
daudio_master = <0x04>;
|
|
audio_format = <0x01>;
|
|
signal_inversion = <0x01>;
|
|
frametype = <0x0>;
|
|
tdm_config = <0x01>;
|
|
tdm_num = <0x0>;
|
|
mclk_div = <0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
daudio1:daudio@0x05091000 {
|
|
compatible = "allwinner,sunxi-daudio";
|
|
reg = <0x0 0x05091000 0x0 0x58>;
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&daudio1_pins_a>;
|
|
pinctrl-1 = <&daudio1_pins_b>;
|
|
clocks = <&clk_pll_audio>,<&clk_i2s1>;
|
|
pcm_lrck_period = <0x20>;
|
|
pcm_lrckr_period = <0x01>;
|
|
slot_width_select = <0x20>;
|
|
daudio_master = <0x04>;
|
|
audio_format = <0x01>;
|
|
signal_inversion = <0x01>;
|
|
frametype = <0x0>;
|
|
tdm_config = <0x01>;
|
|
tdm_num = <0x1>;
|
|
mclk_div = <0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
daudio2:daudio@0x05092000 {
|
|
compatible = "allwinner,sunxi-daudio";
|
|
reg = <0x0 0x05092000 0x0 0x58>;
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&daudio2_pins_a>;
|
|
pinctrl-1 = <&daudio2_pins_b>;
|
|
clocks = <&clk_pll_audio>,<&clk_i2s2>;
|
|
pcm_lrck_period = <0x20>;
|
|
pcm_lrckr_period = <0x01>;
|
|
slot_width_select = <0x20>;
|
|
daudio_master = <0x04>;
|
|
audio_format = <0x01>;
|
|
signal_inversion = <0x01>;
|
|
frametype = <0x0>;
|
|
tdm_config = <0x01>;
|
|
tdm_num = <0x2>;
|
|
mclk_div = <0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmic:dmic-controller@0x05095000{
|
|
compatible = "allwinner,sunxi-dmic";
|
|
reg = <0x0 0x05095000 0x0 0x34>;
|
|
clocks = <&clk_pll_audio>,<&clk_dmic>;
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&dmic_pins_a>;
|
|
pinctrl-1 = <&dmic_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sndcodec:sound@0 {
|
|
compatible = "allwinner,sunxi-codec-machine";
|
|
interrupts = <GIC_SPI 20 4>;
|
|
sunxi,i2s-controller = <&i2s>;
|
|
sunxi,audio-codec = <&codec>;
|
|
aif2fmt = <3>;
|
|
aif3fmt = <3>;
|
|
aif2master = <1>;
|
|
hp_detect_case = <0x00>;
|
|
status = "okay";
|
|
};
|
|
|
|
snddaudio0:sound@1{
|
|
compatible = "allwinner,sunxi-daudio0-machine";
|
|
sunxi,daudio-controller = <&daudio0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
snddaudio1:sound@2{
|
|
compatible = "allwinner,sunxi-daudio1-machine";
|
|
sunxi,daudio-controller = <&daudio1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
snddaudio2:sound@3{
|
|
compatible = "allwinner,sunxi-daudio2-machine";
|
|
sunxi,daudio-controller = <&daudio2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
snddmic:sound@5{
|
|
compatible = "allwinner,sunxi-dmic-machine";
|
|
sunxi,dmic-controller = <&dmic>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@0x05010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-spi";
|
|
device_type = "spi0";
|
|
reg = <0x0 0x05010000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_pll_periph0>, <&clk_spi0>;
|
|
clock-frequency = <100000000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
|
|
pinctrl-1 = <&spi0_pins_c>;
|
|
spi0_cs_number = <1>;
|
|
spi0_cs_bitmap = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@0x05011000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun50i-spi";
|
|
device_type = "spi1";
|
|
reg = <0x0 0x05011000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_pll_periph0>, <&clk_spi1>;
|
|
clock-frequency = <100000000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
|
|
pinctrl-1 = <&spi1_pins_c>;
|
|
spi1_cs_number = <1>;
|
|
spi1_cs_bitmap = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdc2: sdmmc@04022000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p6x";
|
|
device_type = "sdc2";
|
|
reg = <0x0 0x04022000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 35 0x0104>;
|
|
clocks = <&clk_hosc>,
|
|
<&clk_pll_periph1x2>,
|
|
<&clk_sdmmc2_mod>,
|
|
<&clk_sdmmc2_bus>,
|
|
<&clk_sdmmc2_rst>;
|
|
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&sdc2_pins_a>;
|
|
pinctrl-1 = <&sdc2_pins_b>;
|
|
bus-width = <8>;
|
|
cap-mmc-highspeed;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
non-removable;
|
|
/*max-frequency = <200000000>;*/
|
|
max-frequency = <150000000>;
|
|
cap-erase;
|
|
mmc-high-capacity-erase-size;
|
|
no-sdio;
|
|
no-sd;
|
|
/*-- speed mode --*/
|
|
/*sm0: DS26_SDR12*/
|
|
/*sm1: HSSDR52_SDR25*/
|
|
/*sm2: HSDDR52_DDR50*/
|
|
/*sm3: HS200_SDR104*/
|
|
/*sm4: HS400*/
|
|
/*-- frequency point --
|
|
/*f0: CLK_400K*/
|
|
/*f1: CLK_25M*/
|
|
/*f2: CLK_50M*/
|
|
/*f3: CLK_100M*/
|
|
/*f4: CLK_150M*/
|
|
/*f5: CLK_200M*/
|
|
|
|
sdc_tm4_sm0_freq0 = <0>;
|
|
sdc_tm4_sm0_freq1 = <0>;
|
|
sdc_tm4_sm1_freq0 = <0x00000000>;
|
|
sdc_tm4_sm1_freq1 = <0>;
|
|
sdc_tm4_sm2_freq0 = <0x00000000>;
|
|
sdc_tm4_sm2_freq1 = <0>;
|
|
sdc_tm4_sm3_freq0 = <0x05000000>;
|
|
sdc_tm4_sm3_freq1 = <0x00000005>;
|
|
sdc_tm4_sm4_freq0 = <0x00050000>;
|
|
sdc_tm4_sm4_freq1 = <0x00000004>;
|
|
|
|
/*vmmc-supply = <®_3p3v>;*/
|
|
/*vqmc-supply = <®_3p3v>;*/
|
|
/*vdmc-supply = <®_3p3v>;*/
|
|
/*vmmc = "vcc-card";*/
|
|
/*vqmc = "";*/
|
|
/*vdmc = "";*/
|
|
/*sunxi-power-save-mode;*/
|
|
/*status = "disabled";*/
|
|
status = "okay";
|
|
};
|
|
|
|
sdc0: sdmmc@04020000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p1x";
|
|
device_type = "sdc0";
|
|
reg = <0x0 0x04020000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 33 0x0104>;
|
|
clocks = <&clk_hosc>,
|
|
<&clk_pll_periph1x2>,
|
|
<&clk_sdmmc0_mod>,
|
|
<&clk_sdmmc0_bus>,
|
|
<&clk_sdmmc0_rst>;
|
|
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&sdc0_pins_a>;
|
|
pinctrl-1 = <&sdc0_pins_b>;
|
|
max-frequency = <50000000>;
|
|
bus-width = <4>;
|
|
/*non-removable;*/
|
|
/*broken-cd;*/
|
|
/*cd-inverted*/
|
|
cd-gpios = <&pio PF 6 0 1 2 0>;
|
|
/* vmmc-supply = <®_3p3v>;*/
|
|
/* vqmc-supply = <®_3p3v>;*/
|
|
/* vdmc-supply = <®_3p3v>;*/
|
|
/*vmmc = "vcc-card";*/
|
|
/*vqmc = "";*/
|
|
/*vdmc = "";*/
|
|
cap-sd-highspeed;
|
|
cap-wait-while-busy;
|
|
no-sdio;
|
|
no-mmc;
|
|
/*sd-uhs-sdr50;*/
|
|
/*sd-uhs-ddr50;*/
|
|
/*cap-sdio-irq;*/
|
|
/*keep-power-in-suspend;*/
|
|
/*ignore-pm-notify;*/
|
|
/*sunxi-power-save-mode;*/
|
|
/*sunxi-dly-400k = <1 0 0 0>; */
|
|
/*sunxi-dly-26M = <1 0 0 0>;*/
|
|
/*sunxi-dly-52M = <1 0 0 0>;*/
|
|
/*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
|
|
/*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
|
|
sunxi-dly-104M = <1 1 0 0 0 0>;
|
|
sunxi-dly-208M = <1 1 0 0 0 0>;
|
|
/*sunxi-dly-104M-ddr = <1 0 0 0>;*/
|
|
/*sunxi-dly-208M-ddr = <1 0 0 0>;*/
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
sdc1: sdmmc@04021000 {
|
|
compatible = "allwinner,sunxi-mmc-v4p1x";
|
|
device_type = "sdc1";
|
|
reg = <0x0 0x04021000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 34 0x0104>;
|
|
clocks = <&clk_hosc>,
|
|
<&clk_pll_periph1x2>,
|
|
<&clk_sdmmc1_mod>,
|
|
<&clk_sdmmc1_bus>,
|
|
<&clk_sdmmc1_rst>;
|
|
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&sdc1_pins_a>;
|
|
pinctrl-1 = <&sdc1_pins_b>;
|
|
max-frequency = <50000000>;
|
|
bus-width = <4>;
|
|
/*broken-cd;*/
|
|
/*cd-inverted*/
|
|
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
|
|
/* vmmc-supply = <®_3p3v>;*/
|
|
/* vqmc-supply = <®_3p3v>;*/
|
|
/* vdmc-supply = <®_3p3v>;*/
|
|
/*vmmc = "vcc-card";*/
|
|
/*vqmc = "";*/
|
|
/*vdmc = "";*/
|
|
cap-sd-highspeed;
|
|
no-mmc;
|
|
/*sd-uhs-sdr50;*/
|
|
/*sd-uhs-ddr50;*/
|
|
/*sd-uhs-sdr104;*/
|
|
/*cap-sdio-irq;*/
|
|
/*keep-power-in-suspend;*/
|
|
/*ignore-pm-notify;*/
|
|
/*sunxi-power-save-mode;*/
|
|
/*sunxi-dly-400k = <1 0 0 0 0>; */
|
|
/*sunxi-dly-26M = <1 0 0 0 0>;*/
|
|
/*sunxi-dly-52M = <1 0 0 0 0>;*/
|
|
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
|
|
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
|
|
sunxi-dly-104M = <1 0 0 0 1>;
|
|
/*sunxi-dly-208M = <1 1 0 0 0>;*/
|
|
sunxi-dly-208M = <1 0 0 0 1>;
|
|
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
|
|
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
disp: disp@01000000 {
|
|
compatible = "allwinner,sunxi-disp";
|
|
reg = <0x0 0x01000000 0x0 0x01400000>,/*de*/
|
|
<0x0 0x06510000 0x0 0x200>,/*tcon-top*/
|
|
<0x0 0x06511000 0x0 0x1000>,/*tcon0*/
|
|
<0x0 0x06512000 0x0 0x1000>,/*tcon1*/
|
|
<0x0 0x06540000 0x0 0x1000>,/*edp*/
|
|
<0x0 0x06504000 0x0 0x2000>,/*dsi0*/
|
|
<0x0 0x06506000 0x0 0x2000>;/*dsi1*/
|
|
interrupts = <GIC_SPI 54 0x0104>, /*tcon0*/
|
|
<GIC_SPI 55 0x0104>, /*tcon1*/
|
|
<GIC_SPI 56 0x0104>, /*edp*/
|
|
<GIC_SPI 52 0x0104>, /*dsi0*/
|
|
<GIC_SPI 53 0x0104>; /*dsi1*/
|
|
clocks = <&clk_de>,
|
|
<&clk_display_top>,
|
|
<&clk_tcon_lcd0>,
|
|
<&clk_tcon_lcd1>,
|
|
<&clk_edp>,
|
|
<&clk_mipi_dphy0>,
|
|
<&clk_mipi_host0>,
|
|
<&clk_mipi_dphy1>,
|
|
<&clk_mipi_host1>;
|
|
boot_disp = <0>;
|
|
fb_base = <0>;
|
|
/*iommus = <&mmu_aw 0 0>;*/
|
|
dma-coherent;
|
|
status = "okay";
|
|
};
|
|
|
|
edp0: edp0@06540000 {
|
|
compatible = "allwinner,sunxi-edp0";
|
|
reg = <0x0 0x06540000 0x0 0x1000>;
|
|
clocks = <&clk_edp>;
|
|
device_type = "edp0";
|
|
pinctrl-names = "active","sleep";
|
|
interrupts = <GIC_SPI 56 0x0104>;
|
|
status = "okay";
|
|
};
|
|
|
|
lcd0: lcd0@01c0c000 {
|
|
compatible = "allwinner,sunxi-lcd0";
|
|
pinctrl-names = "active","sleep";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
lcd1: lcd1@01c0c001 {
|
|
compatible = "allwinner,sunxi-lcd1";
|
|
pinctrl-names = "active","sleep";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
hdmi: hdmi@01ee0000 {
|
|
compatible = "allwinner,sunxi-hdmi";
|
|
reg = <0x0 0x01ee0000 0x0 0x20000>;
|
|
/* clocks = <&clk_hdmi>,<&clk_hdmi_slow>; */
|
|
};
|
|
|
|
tv0: tv0@01c94000 {
|
|
compatible = "allwinner,sunxi-tv";
|
|
reg = <0x0 0x01e40000 0x0 0x1000>;
|
|
/* clocks = <&clk_tve>; */
|
|
status = "disabled";
|
|
};
|
|
|
|
soc_tr: tr@01000000 {
|
|
compatible = "allwinner,sun8iw11-tr";
|
|
reg = <0x0 0x01000000 0x0 0x000200bc>;
|
|
interrupts = <GIC_SPI 69 0x0104>;
|
|
clocks = <&clk_de>;
|
|
dma-coherent;
|
|
status = "okay";
|
|
};
|
|
|
|
pwm: pwm@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm";
|
|
reg = <0x0 0x0300a000 0x0 0x3c>;
|
|
clocks = <&clk_pwm>;
|
|
pwm-number = <2>;
|
|
pwm-base = <0x0>;
|
|
pwms = <&pwm0>, <&pwm1>;
|
|
};
|
|
|
|
pwm0: pwm0@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm0";
|
|
pinctrl-names = "active", "sleep";
|
|
reg_base = <0x0300a000>;
|
|
reg_busy_offset = <0x00>;
|
|
reg_busy_shift = <28>;
|
|
reg_enable_offset = <0x00>;
|
|
reg_enable_shift = <4>;
|
|
reg_clk_gating_offset = <0x00>;
|
|
reg_clk_gating_shift = <6>;
|
|
reg_bypass_offset = <0x00>;
|
|
reg_bypass_shift = <9>;
|
|
reg_pulse_start_offset = <0x00>;
|
|
reg_pulse_start_shift = <8>;
|
|
reg_mode_offset = <0x00>;
|
|
reg_mode_shift = <7>;
|
|
reg_polarity_offset = <0x00>;
|
|
reg_polarity_shift = <5>;
|
|
reg_period_offset = <0x04>;
|
|
reg_period_shift = <16>;
|
|
reg_period_width = <16>;
|
|
reg_active_offset = <0x04>;
|
|
reg_active_shift = <0>;
|
|
reg_active_width = <16>;
|
|
reg_prescal_offset = <0x00>;
|
|
reg_prescal_shift = <0>;
|
|
reg_prescal_width = <4>;
|
|
};
|
|
|
|
pwm1: pwm1@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm1";
|
|
pinctrl-names = "active", "sleep";
|
|
reg_base = <0x0300a000>;
|
|
reg_busy_offset = <0x00>;
|
|
reg_busy_shift = <29>;
|
|
reg_enable_offset = <0x00>;
|
|
reg_enable_shift = <19>;
|
|
reg_clk_gating_offset = <0x00>;
|
|
reg_clk_gating_shift = <21>;
|
|
reg_bypass_offset = <0x00>;
|
|
reg_bypass_shift = <24>;
|
|
reg_pulse_start_offset = <0x00>;
|
|
reg_pulse_start_shift = <23>;
|
|
reg_mode_offset = <0x00>;
|
|
reg_mode_shift = <22>;
|
|
reg_polarity_offset = <0x00>;
|
|
reg_polarity_shift = <20>;
|
|
reg_period_offset = <0x08>;
|
|
reg_period_shift = <16>;
|
|
reg_period_width = <16>;
|
|
reg_active_offset = <0x08>;
|
|
reg_active_shift = <0>;
|
|
reg_active_width = <16>;
|
|
reg_prescal_offset = <0x00>;
|
|
reg_prescal_shift = <15>;
|
|
reg_prescal_width = <4>;
|
|
};
|
|
s_pwm: s_pwm@07020c00 {
|
|
compatible = "allwinner,sunxi-s_pwm";
|
|
reg = <0x0 0x07020c00 0x0 0x3c>;
|
|
clocks = <&clk_spwm>;
|
|
pwm-number = <1>;
|
|
pwm-base = <0x10>;
|
|
pwms = <&spwm0>;
|
|
};
|
|
|
|
spwm0: spwm0@07020c00 {
|
|
compatible = "allwinner,sunxi-pwm16";
|
|
pinctrl-names = "active", "sleep";
|
|
reg_base = <0x07020c00>;
|
|
reg_busy_offset = <0x00>;
|
|
reg_busy_shift = <28>;
|
|
reg_enable_offset = <0x00>;
|
|
reg_enable_shift = <4>;
|
|
reg_clk_gating_offset = <0x00>;
|
|
reg_clk_gating_shift = <6>;
|
|
reg_bypass_offset = <0x00>;
|
|
reg_bypass_shift = <9>;
|
|
reg_pulse_start_offset = <0x00>;
|
|
reg_pulse_start_shift = <8>;
|
|
reg_mode_offset = <0x00>;
|
|
reg_mode_shift = <7>;
|
|
reg_polarity_offset = <0x00>;
|
|
reg_polarity_shift = <5>;
|
|
reg_period_offset = <0x04>;
|
|
reg_period_shift = <16>;
|
|
reg_period_width = <16>;
|
|
reg_active_offset = <0x04>;
|
|
reg_active_shift = <0>;
|
|
reg_active_width = <16>;
|
|
reg_prescal_offset = <0x00>;
|
|
reg_prescal_shift = <0>;
|
|
reg_prescal_width = <4>;
|
|
};
|
|
|
|
boot_disp: boot_disp {
|
|
compatible = "allwinner,boot_disp";
|
|
};
|
|
|
|
ac200: ac200 {
|
|
compatible = "allwinner,sunxi-ac200";
|
|
/* clocks = <&clk_tcon0>; */
|
|
pinctrl-names = "active","sleep";
|
|
status = "okay";
|
|
};
|
|
|
|
vind0:vind@0 {
|
|
compatible = "allwinner,sunxi-vin-media", "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
device_id = <0>;
|
|
vind0_clk = <200000000>;
|
|
reg = <0x0 0x06620000 0x0 0x1000>;
|
|
clocks = <&clk_csi_top>, <&clk_pll_periph0>,
|
|
<&clk_csi_master>, <&clk_hosc>, <&clk_pll_periph0>;
|
|
pinctrl-names = "mclk0-default","mclk0-sleep";
|
|
pinctrl-0 = <&csi_mclk0_pins_a>;
|
|
pinctrl-1 = <&csi_mclk0_pins_b>;
|
|
status = "okay";
|
|
|
|
csi_cci0:cci@0x0662e000 {
|
|
compatible = "allwinner,sunxi-csi_cci";
|
|
reg = <0x0 0x0662e000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 63 4>;
|
|
clocks = <&clk_csi_misc>;
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&csi_cci0_pins_a>;
|
|
pinctrl-1 = <&csi_cci0_pins_b>;
|
|
device_id = <0>;
|
|
status = "okay";
|
|
};
|
|
csi0:csi@0x06621000 {
|
|
device_type = "csi0";
|
|
compatible = "allwinner,sunxi-csi";
|
|
reg = <0x0 0x06621000 0x0 0x1000>;
|
|
pinctrl-names = "default","sleep";
|
|
pinctrl-0 = <&csi0_pins_a>;
|
|
pinctrl-1 = <&csi0_pins_b>;
|
|
device_id = <0>;
|
|
/* iommus = <&mmu_aw 4 1>; */
|
|
status = "okay";
|
|
};
|
|
csi1:csi@1 {
|
|
device_type = "csi1";
|
|
compatible = "allwinner,sunxi-csi";
|
|
device_id = <1>;
|
|
/* iommus = <&mmu_aw 4 1>; */
|
|
status = "disabled";
|
|
};
|
|
mipi0:mipi@0 {
|
|
compatible = "allwinner,sunxi-mipi";
|
|
device_id = <0>;
|
|
status = "disabled";
|
|
};
|
|
mipi1:mipi@1 {
|
|
compatible = "allwinner,sunxi-mipi";
|
|
device_id = <1>;
|
|
status = "disabled";
|
|
};
|
|
isp0:isp@0 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
device_id = <0>;
|
|
status = "okay";
|
|
};
|
|
isp1:isp@1 {
|
|
compatible = "allwinner,sunxi-isp";
|
|
device_id = <1>;
|
|
status = "disabled";
|
|
};
|
|
scaler0:scaler@0x02101000 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x0 0x02101000 0x0 0x400>;
|
|
device_id = <0>;
|
|
status = "okay";
|
|
};
|
|
scaler1:scaler@0x02101400 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
reg = <0x0 0x02101400 0x0 0x400>;
|
|
device_id = <1>;
|
|
status = "okay";
|
|
};
|
|
scaler2:scaler@2 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
device_id = <2>;
|
|
status = "disabled";
|
|
};
|
|
scaler3:scaler@3 {
|
|
compatible = "allwinner,sunxi-scaler";
|
|
device_id = <3>;
|
|
status = "disabled";
|
|
};
|
|
actuator0:actuator@0 {
|
|
device_type = "actuator0";
|
|
compatible = "allwinner,sunxi-actuator";
|
|
actuator0_name = "ad5820_act";
|
|
actuator0_slave = <0x18>;
|
|
actuator0_af_pwdn = <>;
|
|
actuator0_afvdd = "afvcc-csi";
|
|
actuator0_afvdd_vol = <2800000>;
|
|
status = "disabled";
|
|
};
|
|
flash0:flash@0 {
|
|
device_type = "flash0";
|
|
compatible = "allwinner,sunxi-flash";
|
|
flash0_type = <2>;
|
|
flash0_en = <>;
|
|
flash0_mode = <>;
|
|
flash0_flvdd = "";
|
|
flash0_flvdd_vol = <>;
|
|
device_id = <0>;
|
|
status = "disabled";
|
|
};
|
|
sensor0:sensor@0 {
|
|
device_type = "sensor0";
|
|
sensor0_mname = "ov5640";
|
|
sensor0_twi_cci_id = <0>;
|
|
sensor0_twi_addr = <0x78>;
|
|
sensor0_pos = "rear";
|
|
sensor0_isp_used = <0>;
|
|
sensor0_fmt = <0>;
|
|
sensor0_stby_mode = <0>;
|
|
sensor0_vflip = <0>;
|
|
sensor0_hflip = <0>;
|
|
sensor0_cameravdd = "vcc33-camera";
|
|
sensor0_cameravdd_vol = <3300000>;
|
|
sensor0_iovdd = "iovdd-csi";
|
|
sensor0_iovdd_vol = <2800000>;
|
|
sensor0_avdd = "avdd-csi";
|
|
sensor0_avdd_vol = <2800000>;
|
|
sensor0_dvdd = "dvdd-csi-18";
|
|
sensor0_dvdd_vol = <1500000>;
|
|
sensor0_power_en = <>;
|
|
sensor0_reset = <&pio PE 16 1 0 1 0>;
|
|
sensor0_pwdn = <&pio PE 17 1 0 1 0>;
|
|
flash_handle = <&flash0>;
|
|
act_handle = <&actuator0>;
|
|
status = "okay";
|
|
};
|
|
sensor1:sensor@1 {
|
|
device_type = "sensor1";
|
|
sensor1_mname = "ov5647";
|
|
sensor1_twi_cci_id = <0>;
|
|
sensor1_twi_addr = <0x6c>;
|
|
sensor1_pos = "front";
|
|
sensor1_isp_used = <0>;
|
|
sensor1_fmt = <0>;
|
|
sensor1_stby_mode = <0>;
|
|
sensor1_vflip = <0>;
|
|
sensor1_hflip = <0>;
|
|
sensor1_cameravdd = "vcc33-camera";
|
|
sensor1_cameravdd_vol = <3300000>;
|
|
sensor1_iovdd = "iovdd-csi";
|
|
sensor1_iovdd_vol = <2800000>;
|
|
sensor1_avdd = "avdd-csi";
|
|
sensor1_avdd_vol = <2800000>;
|
|
sensor1_dvdd = "dvdd-csi-18";
|
|
sensor1_dvdd_vol = <1500000>;
|
|
sensor1_power_en = <>;
|
|
sensor1_reset = <&pio PE 16 1 0 1 0>;
|
|
sensor1_pwdn = <&pio PE 17 1 0 1 0>;
|
|
flash_handle = <>;
|
|
act_handle = <>;
|
|
status = "okay";
|
|
};
|
|
vinc0:vinc@0x06623000 {
|
|
device_type = "vinc0";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x0 0x06623000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 57 4>;
|
|
vinc0_csi_sel = <0>;
|
|
vinc0_mipi_sel = <0xff>;
|
|
vinc0_isp_sel = <0>;
|
|
vinc0_sensor_sel = <0>;
|
|
vinc0_sensor_list = <0>;
|
|
isp_handle = <&isp0 &isp1>;
|
|
sensor_handle = <&sensor0 &sensor1>;
|
|
device_id = <0>;
|
|
status = "okay";
|
|
};
|
|
vinc1:vinc@0x06623100 {
|
|
device_type = "vinc1";
|
|
compatible = "allwinner,sunxi-vin-core";
|
|
reg = <0x0 0x06623100 0x0 0x100>;
|
|
interrupts = <GIC_SPI 58 4>;
|
|
vinc1_csi_sel = <0>;
|
|
vinc1_mipi_sel = <0xff>;
|
|
vinc1_isp_sel = <0>;
|
|
vinc1_sensor_sel = <1>;
|
|
vinc1_sensor_list = <0>;
|
|
isp_handle = <&isp0 &isp1>;
|
|
sensor_handle = <&sensor0 &sensor1>;
|
|
device_id = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
Vdevice: vdevice@0 {
|
|
compatible = "allwinner,sun50i-vdevice";
|
|
device_type = "Vdevice";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&vdevice_pins_a>;
|
|
test-gpios = <&pio PB 0 1 2 2 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emce: emce@01905000 {
|
|
compatible = "allwinner,sunxi-emce";
|
|
device_name = "emce";
|
|
reg = <0x0 0x01905000 0 0x100>;
|
|
clock-frequency = <300000000>;
|
|
clocks = <&clk_emce>, <&clk_pll_periph0x2>;
|
|
};
|
|
|
|
cryptoengine: ce@1904000 {
|
|
compatible = "allwinner,sunxi-ce";
|
|
device_name = "ce";
|
|
reg = <0x0 0x01904000 0x0 0xa0>, /* non-secure space */
|
|
<0x0 0x01904800 0x0 0xa0>; /* secure space */
|
|
interrupts = <GIC_SPI 74 0xff01>, /* non-secure space */
|
|
<GIC_SPI 75 0xff01>; /* secure space */
|
|
clock-frequency = <300000000>; /* 300MHz */
|
|
clocks = <&clk_ce>, <&clk_pll_periph0x2>;
|
|
};
|
|
|
|
pmu0: pmu@0{
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "okay";
|
|
|
|
powerkey0: powerkey@0{
|
|
status = "okay";
|
|
};
|
|
|
|
regulator0: regulator@0{
|
|
status = "okay";
|
|
};
|
|
|
|
axp_gpio0: axp_gpio@0{
|
|
gpio-controller;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <6>;
|
|
status = "okay";
|
|
};
|
|
|
|
charger0: charger@0{
|
|
status = "ok";
|
|
};
|
|
};
|
|
|
|
nmi:nmi@0x07010320{
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sunxi-nmi";
|
|
reg = <0x0 0x07010320 0x0 0x10>;
|
|
nmi_irq_ctrl = <0x0>;
|
|
nmi_irq_en = <0x4>;
|
|
nmi_irq_status = <0x8>;
|
|
status = "okay";
|
|
};
|
|
|
|
nand0:nand0@04011000{
|
|
compatible = "allwinner,sun50iw3-nand";
|
|
device_type = "nand0";
|
|
reg = <0x0 0x04011000 0x0 0x1000>;/* nand0 */
|
|
interrupts = <GIC_SPI 32 0x04>;
|
|
clocks = <&clk_pll_periph1x2>,<&clk_nand0>,<&clk_nand1>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
|
|
pinctrl-1 = <&nand0_pins_c>;
|
|
nand0_regulator1 = "vcc-nand";
|
|
nand0_regulator2 = "none";
|
|
nand0_cache_level = <0x55aaaa55>;
|
|
nand0_flush_cache_num = <0x55aaaa55>;
|
|
nand0_capacity_level = <0x55aaaa55>;
|
|
nand0_id_number_ctl = <0x55aaaa55>;
|
|
nand0_print_level = <0x55aaaa55>;
|
|
nand0_p0 = <0x55aaaa55>;
|
|
nand0_p1 = <0x55aaaa55>;
|
|
nand0_p2 = <0x55aaaa55>;
|
|
nand0_p3 = <0x55aaaa55>;
|
|
status = "okay";
|
|
};
|
|
|
|
sunxi_thermal_sensor:thermal_sensor{
|
|
compatible = "allwinner,thermal_sensor";
|
|
reg = <0x0 0x05070400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_NONE>;
|
|
clocks = <&clk_hosc>,<&clk_ths>;
|
|
sensor_num = <3>;
|
|
combine_num = <2>;
|
|
shut_temp= <110>;
|
|
status = "okay";
|
|
|
|
ths_combine0:ths_combine0{
|
|
compatible = "allwinner,ths_combine0";
|
|
#thermal-sensor-cells = <1>;
|
|
combine_sensor_num = <1>;
|
|
combine_sensor_type = "CPU";
|
|
combine_sensor_temp_type = "max";
|
|
combine_sensor_id = <2>;
|
|
};
|
|
|
|
ths_combine1:ths_combine1{
|
|
compatible = "allwinner,ths_combine1";
|
|
#thermal-sensor-cells = <1>;
|
|
combine_sensor_num = <2>;
|
|
combine_sensor_type = "GPU&VE";
|
|
combine_sensor_temp_type = "max";
|
|
combine_sensor_id = <0 1>;
|
|
};
|
|
|
|
};
|
|
|
|
cpu_budget_cooling:cpu_budget_cool{
|
|
compatible = "allwinner,budget_cooling";
|
|
device_type = "cpu_budget_cooling";
|
|
#cooling-cells = <2>;
|
|
status = "okay";
|
|
state_cnt = <7>;
|
|
cluster_num = <1>;
|
|
state0 = <1800000 4>;
|
|
state1 = <1512000 4>;
|
|
state2 = <1416000 4>;
|
|
state3 = <1200000 4>;
|
|
state4 = <1008000 3>;
|
|
state5 = <1008000 2>;
|
|
state6 = <1008000 1>;
|
|
};
|
|
|
|
gpu_cooling:gpu_cooling{
|
|
compatible = "allwinner,gpu_cooling";
|
|
device_type = "gpu_cooling";
|
|
reg = <0x0 0x0 0x0 0x0>;
|
|
#cooling-cells = <2>;
|
|
status = "okay";
|
|
state_cnt = <4>;
|
|
state0 = <0>;
|
|
state1 = <1>;
|
|
state2 = <2>;
|
|
state3 = <3>;
|
|
};
|
|
|
|
thermal-zones{
|
|
cpu_thermal_zone{
|
|
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&ths_combine0 0>;
|
|
|
|
trips{
|
|
cpu_trip0:t0{
|
|
temperature = <65>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
cpu_trip1:t1{
|
|
temperature = <75>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
cpu_trip2:t2{
|
|
temperature = <85>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
cpu_trip3:t3{
|
|
temperature = <95>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
cpu_trip4:t4{
|
|
temperature = <105>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
crt_trip0:t5{
|
|
temperature = <110>;
|
|
type = "critical";
|
|
hysteresis = <0>;
|
|
};
|
|
};
|
|
|
|
cooling-maps{
|
|
bind0{
|
|
contribution = <0>;
|
|
trip = <&cpu_trip0>;
|
|
cooling-device = <&cpu_budget_cooling 1 1>;
|
|
};
|
|
bind1{
|
|
contribution = <0>;
|
|
trip = <&cpu_trip1>;
|
|
cooling-device = <&cpu_budget_cooling 2 2>;
|
|
};
|
|
bind2{
|
|
contribution = <0>;
|
|
trip = <&cpu_trip2>;
|
|
cooling-device = <&cpu_budget_cooling 3 4>;
|
|
};
|
|
bind3{
|
|
contribution = <0>;
|
|
trip = <&cpu_trip3>;
|
|
cooling-device = <&cpu_budget_cooling 5 5>;
|
|
};
|
|
bind4{
|
|
contribution = <0>;
|
|
trip = <&cpu_trip4>;
|
|
cooling-device = <&cpu_budget_cooling 6 6>;
|
|
};
|
|
};
|
|
};
|
|
gpu_thermal_zone{
|
|
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <2000>;
|
|
thermal-sensors = <&ths_combine1 1>;
|
|
|
|
trips{
|
|
gpu_trip0:t0{
|
|
temperature = <95>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
gpu_trip1:t1{
|
|
temperature = <100>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
gpu_trip2:t2{
|
|
temperature = <105>;
|
|
type = "passive";
|
|
hysteresis = <0>;
|
|
};
|
|
crt_trip1:t3{
|
|
temperature = <110>;
|
|
type = "critical";
|
|
hysteresis = <0>;
|
|
};
|
|
};
|
|
|
|
cooling-maps{
|
|
bind0{
|
|
contribution = <0>;
|
|
trip = <&gpu_trip0>;
|
|
cooling-device = <&gpu_cooling 1 1>;
|
|
};
|
|
bind1{
|
|
contribution = <0>;
|
|
trip = <&gpu_trip1>;
|
|
cooling-device = <&gpu_cooling 2 2>;
|
|
};
|
|
bind2{
|
|
contribution = <0>;
|
|
trip = <&gpu_trip2>;
|
|
cooling-device = <&gpu_cooling 3 3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gpadc:gpadc{
|
|
compatible = "allwinner,sunxi-gpadc";
|
|
reg = <0x0 0x05070000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_NONE>;
|
|
clocks = <&clk_gpadc>;
|
|
status = "disable";
|
|
};
|
|
|
|
keyboard0:keyboard{
|
|
compatible = "allwinner,keyboard_1200mv";
|
|
reg = <0x0 0x05070800 0x0 0x400>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_NONE>;
|
|
status = "okay";
|
|
key_cnt = <5>;
|
|
key0 = <114 115>;
|
|
key1 = <235 114>;
|
|
key2 = <330 139>;
|
|
key3 = <420 28>;
|
|
key4 = <520 102>;
|
|
};
|
|
|
|
ramoops@0x48106000 {
|
|
compatible = "ramoops";
|
|
reg = <0x0 0x48106000 0x0 0x60000>;
|
|
record-size = <0x00020000>;
|
|
console-size = <0x00020000>;
|
|
pmsg-size = <0x00020000>;
|
|
};
|
|
|
|
gmac0: eth@01c30000 {
|
|
compatible = "allwinner,sunxi-gmac";
|
|
reg = <0x0 0x01c30000 0x0 0x40000>,
|
|
<0x0 0x01c00030 0x0 0x1>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gmacirq";
|
|
/* clocks = <&clk_gmac>, <&clk_ephy>; */
|
|
clock-names = "gmac", "ephy";
|
|
phy-mode = "rgmii";
|
|
tx-delay = <7>;
|
|
rx-delay = <31>;
|
|
phy-rst;
|
|
gmac-power0;
|
|
gmac-power1;
|
|
gmac-power2;
|
|
status = "disable";
|
|
};
|
|
};
|
|
|
|
gpu: gpu@0x01800000 {
|
|
compatible = "arm,mali-t760", "arm,mali-midgard";
|
|
reg = <0x0 0x01800000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 71 4>, <GIC_SPI 72 4>, <GIC_SPI 73 4>;
|
|
interrupt-names = "GPU", "JOB", "MMU";
|
|
clocks = <&clk_pll_gpu>, <&clk_gpu>;
|
|
clock-names = "clk_parent", "clk_mali";
|
|
operating-points = <
|
|
/* KHz uV */
|
|
732000 970000
|
|
708000 950000
|
|
660000 900000
|
|
648000 890000
|
|
636000 880000
|
|
624000 870000
|
|
612000 860000
|
|
588000 850000
|
|
576000 840000
|
|
552000 830000
|
|
528000 820000
|
|
504000 810000
|
|
480000 810000
|
|
456000 810000
|
|
432000 810000
|
|
408000 810000
|
|
384000 810000
|
|
360000 810000
|
|
336000 810000
|
|
312000 810000
|
|
288000 810000
|
|
264000 810000
|
|
240000 810000
|
|
216000 810000
|
|
192000 810000
|
|
>;
|
|
};
|
|
};
|