678 lines
15 KiB
C
678 lines
15 KiB
C
/*
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/intc.h>
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#include <asm/arch/ccmu.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#define SUNXI_DMA_MAX 16
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#define SUNXI_DMA_CHANNAL_BASE (SUNXI_DMA_BASE + 0x100)
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#define SUNXI_DMA_CHANANL_SIZE (0x40)
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#ifndef SUNXI_DMA_LINK_NULL
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#define SUNXI_DMA_LINK_NULL (0xfffff800)
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#endif
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struct dma_irq_handler
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{
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void *m_data;
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void (*m_func)( void * data);
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};
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typedef struct
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{
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unsigned int irq_en0;
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unsigned int irq_en1;
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unsigned int reserved0[2];
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unsigned int irq_pending0;
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unsigned int irq_pending1;
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unsigned int reserved1[2];
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unsigned int reserved2[4];
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unsigned int status;
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}
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sunxi_dma_int_set;
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typedef struct sunxi_dma_channal_set_t
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{
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volatile unsigned int enable;
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volatile unsigned int pause;
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volatile unsigned int start_addr; //起始地址
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volatile unsigned int config;
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volatile unsigned int cur_src_addr; //当前传输地址
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volatile unsigned int cur_dst_addr;
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volatile unsigned int left_bytes; //剩余未传字节数
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volatile unsigned int parameters; //参数
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}
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sunxi_dma_channal_set;
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typedef struct sunxi_dma_source_t
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{
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volatile unsigned int used;
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volatile unsigned int channal_count;
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volatile sunxi_dma_channal_set *channal;
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volatile unsigned int reserved;
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volatile sunxi_dma_start_t *config;
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volatile struct dma_irq_handler dma_func;
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}
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sunxi_dma_source;
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#define DMA_PKG_HALF_INT (1<<0)
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#define DMA_PKG_END_INT (1<<1)
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#define DMA_QUEUE_END_INT (1<<2)
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static int dma_int_count = 0;
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static sunxi_dma_source dma_channal_source[SUNXI_DMA_MAX];
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extern void *malloc_noncache(uint num_bytes);
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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static void sunxi_dma_int_func(void *p)
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{
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int i;
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uint pending;
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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for(i=0; i<8; i++)
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{
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if(dma_channal_source[i].dma_func.m_func)
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{
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pending = (DMA_PKG_END_INT << (i * 4));
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if(dma_int->irq_pending0 & pending)
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{
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dma_int->irq_pending0 = pending;
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dma_channal_source[i].dma_func.m_func(dma_channal_source[i].dma_func.m_data);
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}
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}
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}
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for(i=8;i<15;i++)
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{
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if(dma_channal_source[i].dma_func.m_func)
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{
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pending = (DMA_PKG_END_INT << (i * 4));
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if(dma_int->irq_pending1 & pending)
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{
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dma_int->irq_pending1 = pending;
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dma_channal_source[i].dma_func.m_func(dma_channal_source[i].dma_func.m_data);
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}
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}
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}
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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void sunxi_dma_init(void)
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{
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int i;
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u32 reg_val;
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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dma_int->irq_en0 = 0;
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dma_int->irq_en1 = 0;
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dma_int->irq_pending0 = 0xffffffff;
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dma_int->irq_pending1 = 0xffffffff;
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memset((void *)dma_channal_source, 0, SUNXI_DMA_MAX * sizeof(struct sunxi_dma_source_t));
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for(i=0;i<SUNXI_DMA_MAX;i++)
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{
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dma_channal_source[i].used = 0;
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dma_channal_source[i].channal = (struct sunxi_dma_channal_set_t *)(ulong)(SUNXI_DMA_BASE + i * SUNXI_DMA_CHANANL_SIZE + 0x100);
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dma_channal_source[i].config = (sunxi_dma_start_t *)malloc_noncache(sizeof(sunxi_dma_start_t));
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}
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dma_int_count = 0;
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irq_install_handler(AW_IRQ_DMA, sunxi_dma_int_func, 0);
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#if 1
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//auto MCLK gating disable
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//reg_val = *(volatile unsigned int *)(SUNXI_DMA_BASE + 0x20);
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reg_val = *(volatile unsigned int *)(DMA_AUTO_GATE_REG);
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reg_val &= ~7;
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reg_val |= 4;
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*(volatile unsigned int *)(DMA_AUTO_GATE_REG) = reg_val;
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#endif
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return ;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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void sunxi_dma_exit(void)
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{
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int i;
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ulong hdma;
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unsigned int reg_val = 0;
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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//free dma channal if other module not free it
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for(i=0;i<SUNXI_DMA_MAX;i++)
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{
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if(dma_channal_source[i].used == 1)
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{
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hdma = (ulong)&dma_channal_source[i];
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sunxi_dma_disable_int(hdma);
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sunxi_dma_free_int(hdma);
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dma_channal_source[i].channal->enable = 0;
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dma_channal_source[i].used = 0;
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}
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}
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//irp disable
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dma_int->irq_en0 = 0;
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dma_int->irq_en1 = 0;
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dma_int->irq_pending0 = 0xffffffff;
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dma_int->irq_pending1 = 0xffffffff;
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irq_free_handler(AW_IRQ_DMA);
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/*close dma clock when dma exit*/
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reg_val = readl(DMA_GATING_BASE);
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reg_val &= ~(DMA_GATING_PASS << DMA_GATING_BIT);
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writel(reg_val , DMA_GATING_BASE);
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}
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/*
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****************************************************************************************************
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*
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* DMAC_RequestDma
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*
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* Description:
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* request dma
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*
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* Parameters:
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* type 0: normal timer
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* 1: special timer
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* Return value:
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* dma handler
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* if 0, fail
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****************************************************************************************************
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*/
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ulong sunxi_dma_request(uint dmatype)
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{
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int i;
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for(i=0;i<SUNXI_DMA_MAX;i++)
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{
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if(dma_channal_source[i].used == 0)
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{
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dma_channal_source[i].used = 1;
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dma_channal_source[i].channal_count = i;
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return (ulong)&dma_channal_source[i];
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}
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}
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return 0;
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}
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/*
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****************************************************************************************************
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*
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* DMAC_ReleaseDma
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*
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* Description:
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* release dma
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*
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* Parameters:
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* hDma dma handler
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*
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* Return value:
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* EPDK_OK/FAIL
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****************************************************************************************************
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*/
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int sunxi_dma_release(ulong hdma)
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{
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struct sunxi_dma_source_t *dma_channal = (struct sunxi_dma_source_t *)hdma;
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if(!dma_channal->used)
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{
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return -1;
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}
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sunxi_dma_disable_int(hdma);
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sunxi_dma_free_int(hdma);
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dma_channal->channal->enable = 0;
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dma_channal->used = 0;
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return 0;
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}
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/*
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****************************************************************************************************
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*
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* sunxi_dma_setting
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*
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* Description:
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* start interrupt
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*
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* Parameters:
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*
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*
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*
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*
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*
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*
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* Return value:
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*
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_setting(ulong hdma, sunxi_dma_setting_t *cfg)
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{
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uint *config_addr;
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uint commit_para;
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sunxi_dma_setting_t *dma_set = cfg;
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struct sunxi_dma_source_t *dma_source = (struct sunxi_dma_source_t *)hdma;
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if(!dma_source->used)
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{
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return -1;
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}
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config_addr = (uint *)&(dma_set->cfg);
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if(dma_set->loop_mode)
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{
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dma_source->config->link = (uint)(ulong )(dma_source->config);
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}
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else
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{
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dma_source->config->link = SUNXI_DMA_LINK_NULL;
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}
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commit_para = (dma_set->wait_cyc & 0xff);
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commit_para |= (dma_set->data_block_size & 0xff ) << 8;
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dma_source->config->commit_para = commit_para;
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dma_source->config->config = *config_addr;
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* sunxi_dma_start
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*
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* Description:
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*
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*
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* Parameters:
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*
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*
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* Return value:
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*
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*
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****************************************************************************************************
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*/
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int sunxi_dma_start(ulong hdma, uint saddr, uint daddr, uint bytes)
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{
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struct sunxi_dma_source_t *dma_source = (struct sunxi_dma_source_t *)hdma;
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if(!dma_source->used)
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{
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return -1;
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}
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dma_source->config->source_addr = saddr;
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dma_source->config->dest_addr = daddr;
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dma_source->config->byte_count = bytes;
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dma_source->channal->start_addr = (uint)(ulong)(dma_source->config);
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//guarantee pre data access opration was fisnished here
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asm volatile("dmb sy");
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//flush_cache((uint)&(dma_channal->config), sizeof(sunxi_dma_start_t));
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dma_source->channal->enable = 1;
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* sunxi_dma_stop
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*
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* Description:
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*
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*
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* Parameters:
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*
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*
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* Return value:
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*
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_stop(ulong hdma)
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{
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struct sunxi_dma_source_t *dma_channal = (struct sunxi_dma_source_t *)hdma;
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if(!dma_channal->used)
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{
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return -1;
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}
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dma_channal->channal->enable = 0;
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return 0;
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}
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/*
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**********************************************************************************************************************
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*
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* sunxi_dma_querystatus
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*
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* Description:
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*
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*
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* Parameters:
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*
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*
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* Return value:
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*
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*
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**********************************************************************************************************************
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*/
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int sunxi_dma_querystatus(ulong hdma)
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{
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uint channal_count;
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struct sunxi_dma_source_t *dma_channal = (struct sunxi_dma_source_t *)hdma;
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sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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if(!dma_channal->used)
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{
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return -1;
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}
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channal_count = dma_channal->channal_count;
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return (dma_int->status >> channal_count) & 0x01;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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int sunxi_dma_install_int(ulong hdma, interrupt_handler_t dma_int_func, void *p)
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{
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sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
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sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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uint channal_count;
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if(!dma_channal->used)
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{
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return -1;
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}
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channal_count = dma_channal->channal_count;
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if(channal_count < 8)
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{
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dma_status->irq_pending0 = (7 << channal_count*4);
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}
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else
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{
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dma_status->irq_pending1 = (7 << (channal_count - 8)*4);
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}
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if(!dma_channal->dma_func.m_func)
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{
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dma_channal->dma_func.m_func = dma_int_func;
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dma_channal->dma_func.m_data = p;
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}
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else
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{
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printf("dma 0x%lx int is used already, you have to free it first\n", hdma);
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return -1;
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}
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return 0;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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int sunxi_dma_enable_int(ulong hdma)
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{
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sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
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sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
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uint channal_count;
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if(!dma_channal->used)
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{
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return -1;
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}
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channal_count = dma_channal->channal_count;
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if(channal_count < 8)
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{
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if(dma_status->irq_en0 & (DMA_PKG_END_INT << channal_count*4))
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{
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printf("dma 0x%lx int is avaible already\n", hdma);
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return 0;
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}
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dma_status->irq_en0 |= (DMA_PKG_END_INT << channal_count*4);
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}
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else
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{
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if(dma_status->irq_en1 & (DMA_PKG_END_INT << (channal_count - 8)*4))
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{
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printf("dma 0x%lx int is avaible already\n", hdma);
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return 0;
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}
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dma_status->irq_en1 |= (DMA_PKG_END_INT << (channal_count - 8)*4);
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}
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if(!dma_int_count)
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{
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irq_enable(AW_IRQ_DMA);
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}
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dma_int_count ++;
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return 0;
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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int sunxi_dma_disable_int(ulong hdma)
|
|
{
|
|
sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
|
|
sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
|
|
uint channal_count;
|
|
|
|
if(!dma_channal->used)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
channal_count = dma_channal->channal_count;
|
|
if(channal_count < 8)
|
|
{
|
|
if(!(dma_status->irq_en0 & (DMA_PKG_END_INT << channal_count*4)))
|
|
{
|
|
debug("dma 0x%lx int is not used yet\n", hdma);
|
|
return 0;
|
|
}
|
|
dma_status->irq_en0 &= ~(DMA_PKG_END_INT << channal_count*4);
|
|
}
|
|
else
|
|
{
|
|
if(!(dma_status->irq_en1 & (DMA_PKG_END_INT << (channal_count - 8)*4)))
|
|
{
|
|
debug("dma 0x%lx int is not used yet\n", hdma);
|
|
return 0;
|
|
}
|
|
dma_status->irq_en1 &= ~(DMA_PKG_END_INT << (channal_count - 8)*4);
|
|
}
|
|
|
|
//disable golbal int
|
|
if(dma_int_count > 0)
|
|
{
|
|
dma_int_count --;
|
|
}
|
|
if(!dma_int_count)
|
|
{
|
|
irq_disable(AW_IRQ_DMA);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
/*
|
|
************************************************************************************************************
|
|
*
|
|
* function
|
|
*
|
|
* name :
|
|
*
|
|
* parmeters :
|
|
*
|
|
* return :
|
|
*
|
|
* note :
|
|
*
|
|
*
|
|
************************************************************************************************************
|
|
*/
|
|
int sunxi_dma_free_int(ulong hdma)
|
|
{
|
|
sunxi_dma_source *dma_channal = (sunxi_dma_source *)hdma;
|
|
sunxi_dma_int_set *dma_status = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
|
|
uint channal_count;
|
|
|
|
if(!dma_channal->used)
|
|
{
|
|
return -1;
|
|
}
|
|
channal_count = dma_channal->channal_count;
|
|
if(channal_count < 8)
|
|
{
|
|
dma_status->irq_pending0 = (7 << channal_count);
|
|
}
|
|
else
|
|
{
|
|
dma_status->irq_pending1 = (7 << (channal_count - 8));
|
|
}
|
|
|
|
if(dma_channal->dma_func.m_func)
|
|
{
|
|
dma_channal->dma_func.m_func = NULL;
|
|
dma_channal->dma_func.m_data = NULL;
|
|
}
|
|
else
|
|
{
|
|
debug("dma 0x%lx int is free, you do not need to free it again\n", hdma);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|