548 lines
18 KiB
C
Executable File
548 lines
18 KiB
C
Executable File
/*
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* Copyright (c) 2008-2016 Allwinner Technology Co. Ltd.
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* All rights reserved.
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*
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* File : display.h
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* Description : display de
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* History :
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*/
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#ifndef __SUNXI_DISPLAY_H__
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#define __SUNXI_DISPLAY_H__
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struct disp_manager;
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struct disp_device;
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struct disp_smbl;
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struct disp_enhance;
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struct disp_capture;
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typedef struct disp_color
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{
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unsigned char alpha;
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unsigned char red;
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unsigned char green;
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unsigned char blue;
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} disp_color;
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typedef struct disp_rect
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{
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int x;
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int y;
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unsigned int width;
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unsigned int height;
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} disp_rect;
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typedef struct disp_rectsz
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{
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unsigned int width;
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unsigned int height;
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} disp_rectsz;
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typedef struct disp_position
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{
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int x;
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int y;
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} disp_position;
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typedef unsigned int u32;
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typedef enum {
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DISP_FORMAT_ARGB_8888 = 0x00,//MSB A-R-G-B LSB
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DISP_FORMAT_ABGR_8888 = 0x01,
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DISP_FORMAT_RGBA_8888 = 0x02,
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DISP_FORMAT_BGRA_8888 = 0x03,
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DISP_FORMAT_XRGB_8888 = 0x04,
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DISP_FORMAT_XBGR_8888 = 0x05,
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DISP_FORMAT_RGBX_8888 = 0x06,
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DISP_FORMAT_BGRX_8888 = 0x07,
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DISP_FORMAT_RGB_888 = 0x08,
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DISP_FORMAT_BGR_888 = 0x09,
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DISP_FORMAT_RGB_565 = 0x0a,
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DISP_FORMAT_BGR_565 = 0x0b,
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DISP_FORMAT_ARGB_4444 = 0x0c,
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DISP_FORMAT_ABGR_4444 = 0x0d,
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DISP_FORMAT_RGBA_4444 = 0x0e,
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DISP_FORMAT_BGRA_4444 = 0x0f,
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DISP_FORMAT_ARGB_1555 = 0x10,
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DISP_FORMAT_ABGR_1555 = 0x11,
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DISP_FORMAT_RGBA_5551 = 0x12,
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DISP_FORMAT_BGRA_5551 = 0x13,
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/* SP: semi-planar, P:planar, I:interleaved
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* UVUV: U in the LSBs; VUVU: V in the LSBs */
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DISP_FORMAT_YUV444_I_AYUV = 0x40,//MSB A-Y-U-V LSB, reserved
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DISP_FORMAT_YUV444_I_VUYA = 0x41,//MSB V-U-Y-A LSB
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DISP_FORMAT_YUV422_I_YVYU = 0x42,//MSB Y-V-Y-U LSB
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DISP_FORMAT_YUV422_I_YUYV = 0x43,//MSB Y-U-Y-V LSB
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DISP_FORMAT_YUV422_I_UYVY = 0x44,//MSB U-Y-V-Y LSB
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DISP_FORMAT_YUV422_I_VYUY = 0x45,//MSB V-Y-U-Y LSB
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DISP_FORMAT_YUV444_P = 0x46,//MSB P3-2-1-0 LSB, YYYY UUUU VVVV, reserved
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DISP_FORMAT_YUV422_P = 0x47,//MSB P3-2-1-0 LSB YYYY UU VV
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DISP_FORMAT_YUV420_P = 0x48,//MSB P3-2-1-0 LSB YYYY U V
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DISP_FORMAT_YUV411_P = 0x49,//MSB P3-2-1-0 LSB YYYY U V
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DISP_FORMAT_YUV422_SP_UVUV = 0x4a,//MSB V-U-V-U LSB
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DISP_FORMAT_YUV422_SP_VUVU = 0x4b,//MSB U-V-U-V LSB
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DISP_FORMAT_YUV420_SP_UVUV = 0x4c,
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DISP_FORMAT_YUV420_SP_VUVU = 0x4d,
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DISP_FORMAT_YUV411_SP_UVUV = 0x4e,
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DISP_FORMAT_YUV411_SP_VUVU = 0x4f,
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} disp_pixel_format;
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typedef enum {
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DISP_3D_OUT_MODE_CI_1 = 0x5,//column interlaved 1
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DISP_3D_OUT_MODE_CI_2 = 0x6,//column interlaved 2
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DISP_3D_OUT_MODE_CI_3 = 0x7,//column interlaved 3
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DISP_3D_OUT_MODE_CI_4 = 0x8,//column interlaved 4
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DISP_3D_OUT_MODE_LIRGB = 0x9,//line interleaved rgb
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DISP_3D_OUT_MODE_TB = 0x0,//top bottom
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DISP_3D_OUT_MODE_FP = 0x1,//frame packing
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DISP_3D_OUT_MODE_SSF = 0x2,//side by side full
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DISP_3D_OUT_MODE_SSH = 0x3,//side by side half
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DISP_3D_OUT_MODE_LI = 0x4,//line interleaved
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DISP_3D_OUT_MODE_FA = 0xa,//field alternative
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} disp_3d_out_mode;
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typedef enum {
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DISP_BT601 = 0,
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DISP_BT709 = 1,
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DISP_YCC = 2,
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} disp_color_space;
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typedef enum {
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DISP_CSC_TYPE_RGB = 0,
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DISP_CSC_TYPE_YUV1 = 1,//HDMI
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DISP_CSC_TYPE_YUV2 = 2,//TV
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} disp_csc_type;
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typedef enum {
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DISP_COLOR_RANGE_16_255 = 0,
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DISP_COLOR_RANGE_0_255 = 1,
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DISP_COLOR_RANGE_16_235 = 2,
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} disp_color_range;
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typedef enum {
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DISP_OUTPUT_TYPE_NONE = 0,
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DISP_OUTPUT_TYPE_LCD = 1,
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DISP_OUTPUT_TYPE_TV = 2,
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DISP_OUTPUT_TYPE_HDMI = 4,
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DISP_OUTPUT_TYPE_VGA = 8,
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} disp_output_type;
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typedef enum {
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DISP_TV_MOD_480I = 0,
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DISP_TV_MOD_576I = 1,
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DISP_TV_MOD_480P = 2,
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DISP_TV_MOD_576P = 3,
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DISP_TV_MOD_720P_50HZ = 4,
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DISP_TV_MOD_720P_60HZ = 5,
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DISP_TV_MOD_1080I_50HZ = 6,
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DISP_TV_MOD_1080I_60HZ = 7,
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DISP_TV_MOD_1080P_24HZ = 8,
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DISP_TV_MOD_1080P_50HZ = 9,
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DISP_TV_MOD_1080P_60HZ = 0xa,
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DISP_TV_MOD_1080P_24HZ_3D_FP = 0x17,
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DISP_TV_MOD_720P_50HZ_3D_FP = 0x18,
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DISP_TV_MOD_720P_60HZ_3D_FP = 0x19,
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DISP_TV_MOD_1080P_25HZ = 0x1a,
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DISP_TV_MOD_1080P_30HZ = 0x1b,
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DISP_TV_MOD_PAL = 0xb,
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DISP_TV_MOD_PAL_SVIDEO = 0xc,
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DISP_TV_MOD_NTSC = 0xe,
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DISP_TV_MOD_NTSC_SVIDEO = 0xf,
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DISP_TV_MOD_PAL_M = 0x11,
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DISP_TV_MOD_PAL_M_SVIDEO = 0x12,
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DISP_TV_MOD_PAL_NC = 0x14,
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DISP_TV_MOD_PAL_NC_SVIDEO = 0x15,
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DISP_TV_MOD_3840_2160P_30HZ = 0x1c,
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DISP_TV_MOD_3840_2160P_25HZ = 0x1d,
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DISP_TV_MOD_3840_2160P_24HZ = 0x1e,
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DISP_TV_MODE_NUM = 0x1f,
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} disp_tv_mode;
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//FIXME:still need?
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typedef enum {
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DISP_EXIT_MODE_CLEAN_ALL = 0,
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DISP_EXIT_MODE_CLEAN_PARTLY = 1,//only clean interrupt temply
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} disp_exit_mode;
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typedef enum {
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DISP_BF_NORMAL = 0,//non-stereo
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DISP_BF_STEREO_TB = 1 << 0,//stereo top-bottom
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DISP_BF_STEREO_FP = 1 << 1,//stereo frame packing
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DISP_BF_STEREO_SSH = 1 << 2,//stereo side by side half
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DISP_BF_STEREO_SSF = 1 << 3,//stereo side by side full
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DISP_BF_STEREO_LI = 1 << 4,//stereo line interlace
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} disp_buffer_flags;
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typedef enum {
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LAYER_MODE_BUFFER = 0,
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LAYER_MODE_COLOR = 1,
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} disp_layer_mode;
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typedef enum {
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DISP_SCAN_PROGRESSIVE = 0,//non interlace
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DISP_SCAN_INTERLACED_ODD_FLD_FIRST = 1 << 0,//interlace ,odd field first
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DISP_SCAN_INTERLACED_EVEN_FLD_FIRST = 1 << 1,//interlace,even field first
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} disp_scan_flags;
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typedef struct disp_output
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{
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unsigned int type;
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unsigned int mode;
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} disp_output;
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typedef struct disp_rect64
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{
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long long x;
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long long y;
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long long width;
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long long height;
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} disp_rect64;
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typedef struct disp_fb_info
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{
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unsigned long long addr[3]; /* address of frame buffer,
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single addr for interleaved fomart,
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double addr for semi-planar fomart
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triple addr for planar format */
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disp_rectsz size[3]; //size for 3 component,unit: pixels
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unsigned int align[3]; //align for 3 comonent,unit: bytes(
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//align=2^n,i.e. 1/2/4/8/16/32..)
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disp_pixel_format format;
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disp_color_space color_space; //color space
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unsigned int trd_right_addr[3];/* right address of 3d fb,
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used when in frame packing 3d mode */
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unsigned char pre_multiply; //true: pre-multiply fb
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disp_rect64 crop; //crop rectangle boundaries
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disp_buffer_flags flags; //indicate stereo or non-stereo buffer
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disp_scan_flags scan; //scan type & scan order
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} disp_fb_info;
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typedef struct disp_layer_info
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{
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disp_layer_mode mode;
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unsigned char zorder; /*specifies the front-to-back ordering
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of the layers on the screen,
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the top layer having the highest Z value
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can't set zorder, but can get */
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unsigned char alpha_mode; //0: pixel alpha;
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//1: global alpha;
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//2: global pixel alpha
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unsigned char alpha_value; //global alpha value
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disp_rect screen_win; //display window on the screen
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unsigned char b_trd_out; //3d display
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disp_3d_out_mode out_trd_mode;//3d display mode
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union {
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unsigned int color; //valid when LAYER_MODE_COLOR
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disp_fb_info fb; //framebuffer, valid when LAYER_MODE_BUFFER
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};
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unsigned int id; /* frame id, can get the id of frame display currently
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by DISP_LAYER_GET_FRAME_ID */
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} disp_layer_info;
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typedef struct disp_layer_config
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{
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disp_layer_info info;
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unsigned char enable;
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unsigned int channel;
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unsigned int layer_id;
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} disp_layer_config;
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typedef struct disp_colorkey
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{
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disp_color ck_max;
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disp_color ck_min;
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unsigned int red_match_rule;//0/1:always match; 2:match if min<=color<=max;
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//3:match if color>max or color<min
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unsigned int green_match_rule;//0/1:always match; 2:match if min<=color<=max;
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//3:match if color>max or color<min
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unsigned int blue_match_rule;//0/1:always match; 2:match if min<=color<=max;
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//3:match if color>max or color<min
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} disp_colorkey;
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typedef struct disp_s_frame
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{
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disp_pixel_format format;
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disp_rectsz size[3];
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disp_rect crop;
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unsigned long long addr[3];
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} disp_s_frame;
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typedef struct disp_capture_info
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{
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disp_rect window; // capture window, rectangle of screen to be captured
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//capture the whole screen if window eq ZERO
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disp_s_frame out_frame;
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} disp_capture_info;
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typedef struct disp_video_timings
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{
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unsigned int vic; //video infomation code
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unsigned int tv_mode;
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unsigned int pixel_clk;
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unsigned int pixel_repeat;//pixel repeat (pixel_repeat+1) times
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unsigned int x_res;
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unsigned int y_res;
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unsigned int hor_total_time;
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unsigned int hor_back_porch;
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unsigned int hor_front_porch;
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unsigned int hor_sync_time;
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unsigned int ver_total_time;
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unsigned int ver_back_porch;
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unsigned int ver_front_porch;
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unsigned int ver_sync_time;
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unsigned int hor_sync_polarity;//0: negative, 1: positive
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unsigned int ver_sync_polarity;//0: negative, 1: positive
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unsigned char b_interlace;
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unsigned int vactive_space;
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unsigned int trd_mode;
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} disp_video_timings;
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typedef enum {
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FB_MODE_SCREEN0 = 0,
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FB_MODE_SCREEN1 = 1,
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FB_MODE_SCREEN2 = 2,
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FB_MODE_DUAL_SAME_SCREEN_TB = 3,//two screen, top buffer for screen0, bottom buffer for screen1
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FB_MODE_DUAL_DIFF_SCREEN_SAME_CONTENTS = 4,//two screen, they have same contents;
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} disp_fb_mode;
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typedef struct disp_fb_create_info
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{
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disp_fb_mode fb_mode;
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disp_layer_mode mode;
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unsigned int buffer_num;
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unsigned int width;
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unsigned int height;
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unsigned int output_width;//used when scaler mode
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unsigned int output_height;//used when scaler mode
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} disp_fb_create_info;
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typedef enum {
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DISP_INIT_MODE_SCREEN0 = 0,//fb0 for screen0
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DISP_INIT_MODE_SCREEN1 = 1,//fb0 for screen1
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DISP_INIT_MODE_SCREEN2 = 2,//fb0 for screen1
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DISP_INIT_MODE_TWO_DIFF_SCREEN = 3,//fb0 for screen0 and fb1 for screen1
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DISP_INIT_MODE_TWO_SAME_SCREEN = 4,//fb0(up buffer for screen0, down buffer for screen1)
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DISP_INIT_MODE_TWO_DIFF_SCREEN_SAME_CONTENTS = 5,//fb0 for two different screen
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//(screen0 layer is normal layer,
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//screen1 layer is scaler layer);
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} disp_init_mode;
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typedef struct disp_hdmi_func
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{
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int (*hdmi_open)(void);
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int (*hdmi_close)(void);
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int (*hdmi_set_mode)(disp_tv_mode mode);
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int (*hdmi_mode_support)(disp_tv_mode mode);
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int (*hdmi_get_HPD_status)(void);
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int (*hdmi_set_pll)(unsigned int pll, unsigned int clk);
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int (*hdmi_dvi_enable)(unsigned int mode);
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int (*hdmi_dvi_support)(void);
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int (*hdmi_get_input_csc)(void);
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int (*hdmi_get_hdcp_enable)(void);
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int (*hdmi_get_video_timing_info)(disp_video_timings **video_info);
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int (*hdmi_suspend)(void);
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int (*hdmi_resume)(void);
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int (*hdmi_early_suspend)(void);
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int (*hdmi_late_resume)(void);
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int (*hdmi_get_edid)(void);
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} disp_hdmi_func;
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typedef struct disp_tv_func
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{
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int (*tv_enable)(u32 sel);
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int (*tv_disable)(u32 sel);
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int (*tv_suspend)(void);
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int (*tv_resume)(void);
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int (*tv_get_mode)(u32 sel);
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int (*tv_set_mode)(u32 sel, disp_tv_mode tv_mod);
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int (*tv_get_input_csc) (void);
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int (* tv_get_video_timing_info) (u32 sel, disp_video_timings **video_info);
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int (*tv_mode_support) (disp_tv_mode mode);
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int (*tv_hot_plugging_detect)(u32 state);
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int (*tv_set_enhance_mode)(u32 sel, u32 mode);
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} disp_tv_func;
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/* disp_vdevice_interface_para - vdevice interaface parameter
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*
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* @intf:interface
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* 0:hv, 1:cpu, 3:lvds, 4:dsi
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* @sub_intf: sub interface
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* rgb interface: 0:parallel hv, 8:serial hv, 10:dummy rgb, 11: rgb dummy, 12: ccir656
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* cpu interface: 0:18 pin, 10:9pin, 12:6pin, 8:16pin, 14:8pin
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* lvds interface:0:single link, 1:dual link
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* dsi inerafce: 0:video mode, 1:command mode, 2: video burst mode
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* @sequence:output sequence
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* rgb output: 0:rgb rgb, 1:rgb brg, 2:rgb gbr, 4:brg rgb, 5:brg brg, 6:brg gbr
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* 8:grb rgb, 9:grb brg, 10:grb gbr
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* yuv output:0:yuyv, 1: yvyu, 2:uyvy, 3:vyuy
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* @fdelay:yuv eav/sav F line delay
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* 0: F toggle right after active video line
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* 1: delay 2 line(CCIR NTSC)
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* 2: delay 3 line(CCIR PAL)
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* @clk_phase:clk phase
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* 0: 0 degree, 1:90 degree, 2: 180 degree, 3:270 degree
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* @sync_polarity:sync signals polarity
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* 0: vsync active low,hsync active low
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* 1: vsync active high,hsync active low
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* 2: vsync active low,hsync active high
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* 3: vsync active high,hsync active high
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*/
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typedef struct disp_vdevice_interface_para
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{
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unsigned int intf;
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unsigned int sub_intf;
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unsigned int sequence;
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unsigned int fdelay;
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unsigned int clk_phase;
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unsigned int sync_polarity;
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} disp_vdevice_interface_para;
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typedef struct disp_vdevice_source_ops
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{
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int (*tcon_enable)(struct disp_device *dispdev);
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int (*tcon_disable)(struct disp_device *dispdev);
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} disp_vdevice_source_ops;
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typedef struct disp_device_func
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{
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int (*enable)(void);
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int (*disable)(void);
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int (*set_mode)(u32 mode);
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int (*mode_support)(u32 mode);
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int (*get_HPD_status)(void);
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int (*get_input_csc)(void);
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int (*get_video_timing_info)(disp_video_timings **video_info);
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int (*suspend)(void);
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int (*resume)(void);
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int (*early_suspend)(void);
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int (*late_resume)(void);
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int (*get_interface_para)(void *para);
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} disp_device_func;
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typedef struct disp_vdevice_init_data
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{
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char name[32];
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u32 disp;
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u32 fix_timing;
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disp_output_type type;
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disp_device_func func;
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} disp_vdevice_init_data;
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typedef enum disp_tv_dac_source
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{
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DISP_TV_DAC_SRC_COMPOSITE = 0,
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DISP_TV_DAC_SRC_LUMA = 1,
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DISP_TV_DAC_SRC_CHROMA = 2,
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DISP_TV_DAC_SRC_Y = 4,
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DISP_TV_DAC_SRC_PB = 5,
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DISP_TV_DAC_SRC_PR = 6,
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DISP_TV_DAC_SRC_NONE = 7,
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} disp_tv_dac_source;
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typedef enum {
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DISP_TV_NONE = 0,
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DISP_TV_CVBS = 1,
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DISP_TV_YPBPR = 2,
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DISP_TV_SVIDEO = 4,
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} disp_tv_output;
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typedef enum tag_DISP_CMD
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{
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//----disp global----
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DISP_RESERVE0 = 0x00,
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DISP_RESERVE1 = 0x01,
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DISP_SET_BKCOLOR = 0x03,
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DISP_GET_BKCOLOR = 0x04,
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DISP_SET_COLORKEY = 0x05,
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DISP_GET_COLORKEY = 0x06,
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DISP_GET_SCN_WIDTH = 0x07,
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DISP_GET_SCN_HEIGHT = 0x08,
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DISP_GET_OUTPUT_TYPE = 0x09,
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DISP_SET_EXIT_MODE = 0x0A,
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DISP_VSYNC_EVENT_EN = 0x0B,
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DISP_BLANK = 0x0C,
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DISP_SHADOW_PROTECT = 0x0D,
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DISP_HWC_COMMIT = 0x0E,
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DISP_DEVICE_SWITCH = 0x0F,
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DISP_GET_OUTPUT = 0x10,
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DISP_SET_COLOR_RANGE = 0x11,
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DISP_GET_COLOR_RANGE = 0x12,
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|
|
|
//----layer----
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DISP_LAYER_ENABLE = 0x40,
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DISP_LAYER_DISABLE = 0x41,
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DISP_LAYER_SET_INFO = 0x42,
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DISP_LAYER_GET_INFO = 0x43,
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DISP_LAYER_TOP = 0x44,
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DISP_LAYER_BOTTOM = 0x45,
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DISP_LAYER_GET_FRAME_ID = 0x46,
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DISP_LAYER_SET_CONFIG = 0x47,
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|
DISP_LAYER_GET_CONFIG = 0x48,
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|
|
|
//----hdmi----
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DISP_HDMI_SUPPORT_MODE = 0xc4,
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DISP_SET_TV_HPD = 0xc5,
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DISP_HDMI_GET_EDID = 0xc6,
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|
|
|
//----lcd----
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|
DISP_LCD_ENABLE = 0x100,
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DISP_LCD_DISABLE = 0x101,
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|
DISP_LCD_SET_BRIGHTNESS = 0x102,
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|
DISP_LCD_GET_BRIGHTNESS = 0x103,
|
|
DISP_LCD_BACKLIGHT_ENABLE = 0x104,
|
|
DISP_LCD_BACKLIGHT_DISABLE = 0x105,
|
|
DISP_LCD_SET_SRC = 0x106,
|
|
DISP_LCD_SET_FPS = 0x107,
|
|
DISP_LCD_GET_FPS = 0x108,
|
|
DISP_LCD_GET_SIZE = 0x109,
|
|
DISP_LCD_GET_MODEL_NAME = 0x10a,
|
|
DISP_LCD_SET_GAMMA_TABLE = 0x10b,
|
|
DISP_LCD_GAMMA_CORRECTION_ENABLE = 0x10c,
|
|
DISP_LCD_GAMMA_CORRECTION_DISABLE = 0x10d,
|
|
DISP_LCD_USER_DEFINED_FUNC = 0x10e,
|
|
DISP_LCD_CHECK_OPEN_FINISH = 0x10f,
|
|
DISP_LCD_CHECK_CLOSE_FINISH = 0x110,
|
|
|
|
//---- capture ---
|
|
DISP_CAPTURE_START = 0x140,//caputre screen and scaler to dram
|
|
DISP_CAPTURE_STOP = 0x141,
|
|
DISP_CAPTURE_COMMIT = 0x142,
|
|
|
|
//---enhance ---
|
|
DISP_ENHANCE_ENABLE = 0x180,
|
|
DISP_ENHANCE_DISABLE = 0x181,
|
|
DISP_ENHANCE_GET_EN = 0x182,
|
|
DISP_ENHANCE_SET_WINDOW = 0x183,
|
|
DISP_ENHANCE_GET_WINDOW = 0x184,
|
|
DISP_ENHANCE_SET_MODE = 0x185,
|
|
DISP_ENHANCE_GET_MODE = 0x186,
|
|
DISP_ENHANCE_DEMO_ENABLE = 0x187,
|
|
DISP_ENHANCE_DEMO_DISABLE = 0x188,
|
|
|
|
//---smart backlight ---
|
|
DISP_SMBL_ENABLE = 0x200,
|
|
DISP_SMBL_DISABLE = 0x201,
|
|
DISP_SMBL_GET_EN = 0x202,
|
|
DISP_SMBL_SET_WINDOW = 0x203,
|
|
DISP_SMBL_GET_WINDOW = 0x204,
|
|
|
|
//---- for test
|
|
DISP_FB_REQUEST = 0x280,
|
|
DISP_FB_RELEASE = 0x281,
|
|
|
|
DISP_MEM_REQUEST = 0x2c0,
|
|
DISP_MEM_RELEASE = 0x2c1,
|
|
DISP_MEM_GETADR = 0x2c2,
|
|
} __DISP_t;
|
|
|
|
#define FBIOGET_LAYER_HDL_0 0x4700
|
|
#define FBIOGET_LAYER_HDL_1 0x4701
|
|
|
|
#endif
|