293 lines
6.3 KiB
C
Executable File
293 lines
6.3 KiB
C
Executable File
/*
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* include/linux/dma/sunxi-dma.h
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*
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* Copyright (C) 2015-2020 Allwinnertech Co., Ltd
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*
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* Author: Wim Hwang <huangwei@allwinnertech.com>
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*
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* Sunxi DMA controller driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/*
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* The source DRQ type and port corresponding relation
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*
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*/
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#ifndef __SUNXI_DMA_H__
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#define __SUNXI_DMA_H__
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#include <linux/dmaengine.h>
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#if defined(CONFIG_ARCH_SUN8IW10)
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#include "sunxi/dma-sun8iw10.h"
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#elif defined(CONFIG_ARCH_SUN8IW11)
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#include "sunxi/dma-sun8iw11.h"
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#elif defined(CONFIG_ARCH_SUN8IW17)
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#include "sunxi/dma-sun8iw17.h"
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#elif defined(CONFIG_ARCH_SUN50IW2P1)
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#include "sunxi/dma-sun50iw2.h"
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#elif defined(CONFIG_ARCH_SUN50IW3P1)
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#include "sunxi/dma-sun50iw3.h"
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#elif defined(CONFIG_ARCH_SUN50IW6P1)
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#include "sunxi/dma-sun50iw6.h"
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#elif defined(CONFIG_ARCH_SUN3IW1P1)
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#include "sunxi/dma-sun3iw1.h"
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#elif defined(CONFIG_ARCH_SUN8IW7)
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#include "sunxi/dma-sun8iw7.h"
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#elif defined(CONFIG_ARCH_SUN8IW12)
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#include "sunxi/dma-sun8iw12.h"
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#elif defined(CONFIG_ARCH_SUN8IW15)
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#include "sunxi/dma-sun8iw15.h"
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#elif defined(CONFIG_ARCH_SUN50IW8)
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#include "sunxi/dma-sun50iw8.h"
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#elif defined(CONFIG_ARCH_SUN8IW18)
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#include "sunxi/dma-sun8iw18.h"
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#elif defined(CONFIG_ARCH_SUN50IW5T)
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#include "sunxi/dma-sun50iw5t.h"
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#else
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#define DRQSRC_SRAM 0
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#define DRQSRC_SDRAM 0
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#if !defined(CONFIG_ARCH_SUN8IW5) \
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&& !defined(CONFIG_ARCH_SUN8IW3) \
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&& !defined(CONFIG_ARCH_SUN8IW8) \
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&& !defined(CONFIG_ARCH_SUN8IW9)
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#define DRQSRC_SPDIFRX 2
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW9)
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#define DRQSRC_DAUDIO_0_RX 3
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#endif
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#if !defined(CONFIG_ARCH_SUN9I) \
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&& !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQSRC_DAUDIO_1_RX 4
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#define DRQSRC_NAND0 5
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#endif
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#define DRQSRC_UART0RX 6
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#define DRQSRC_UART1RX 7
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#define DRQSRC_UART2RX 8
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#ifndef CONFIG_ARCH_SUN8IW8
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#define DRQSRC_UART3RX 9
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#define DRQSRC_UART4RX 10
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#endif
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/* #define DRQSRC_RESEVER 11 */
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/* #define DRQSRC_RESEVER 12 */
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#ifndef CONFIG_ARCH_SUN9I
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#ifdef CONFIG_ARCH_SUN8IW1
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#define DRQSRC_HDMI_DDC 13
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#define DRQSRC_HDMI_AUDIO 14
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW6)
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#define DRQSRC_AUDIO_CODEC 15
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#if defined(CONFIG_ARCH_SUN50I)
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#define DRQSRC_CODEC DRQSRC_AUDIO_CODEC
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#endif
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW3) \
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&& !defined(CONFIG_ARCH_SUN8IW6)
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#define DRQSRC_SS 16
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#if defined(CONFIG_ARCH_SUN50I)
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#define DRQSRC_CE_RX DRQSRC_SS
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#endif
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#endif
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#define DRQSRC_OTG_EP1 17
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#define DRQSRC_OTG_EP2 18
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#define DRQSRC_OTG_EP3 19
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#define DRQSRC_OTG_EP4 20
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#if !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQSRC_OTG_EP5 21
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#endif
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#else
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#define DRQSRC_AC97 18
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1) \
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|| defined(CONFIG_ARCH_SUN9I)
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#define DRQSRC_UART5RX 22
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#endif
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#define DRQSRC_SPI0_RX 23
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#if !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQSRC_SPI1_RX 24
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1) \
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|| defined(CONFIG_ARCH_SUN9I)
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#define DRQSRC_SPI2_RX 25
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#define DRQSRC_SPI3_RX 26
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1)
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#define DRQSRC_TP 27
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#define DRQSRC_NAND1 28
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#define DRQSRC_MTC_ACC 29
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#define DRQSRC_DIGITAL_MIC 30
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#elif defined(CONFIG_ARCH_SUN8IW6) \
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|| defined(CONFIG_ARCH_SUN8IW7)
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#define DRQDST_TDMRX 28
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#endif
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/*
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* The source and destination DRQ type and port corresponding relation
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*/
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#define DRQDST_SRAM 0
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#define DRQDST_SDRAM 0
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#if !defined(CONFIG_ARCH_SUN8IW5) \
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&& !defined(CONFIG_ARCH_SUN8IW5) \
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&& !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQDST_SPDIFTX 2
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW9)
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#define DRQDST_DAUDIO_0_TX 3
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW8) \
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&& !defined(CONFIG_ARCH_SUN8IW9)
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#define DRQDST_DAUDIO_1_TX 4
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#endif
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#if !defined(CONFIG_ARCH_SUN9I) \
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&& !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQDST_NAND0 5
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#endif
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#define DRQDST_UART0TX 6
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#define DRQDST_UART1TX 7
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#define DRQDST_UART2TX 8
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#if !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQDST_UART3TX 9
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#define DRQDST_UART4TX 10
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#endif
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#if defined(CONFIG_ARCH_SUN8IW3) \
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|| defined(CONFIG_ARCH_SUN8IW5) \
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|| defined(CONFIG_ARCH_SUN8IW8) \
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|| defined(CONFIG_ARCH_SUN8IW9)
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#define DRQSRC_TCON0 12
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#endif
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#ifndef CONFIG_ARCH_SUN9I
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#if defined(CONFIG_ARCH_SUN8IW1)
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#define DRQDST_HDMI_DDC 13
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#define DRQDST_HDMI_AUDIO 14
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW6)
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#define DRQDST_AUDIO_CODEC 15
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#if defined(CONFIG_ARCH_SUN50I)
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#define DRQDST_CODEC DRQDST_AUDIO_CODEC
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#endif
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#endif
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#if !defined(CONFIG_ARCH_SUN8IW3) \
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&& !defined(CONFIG_ARCH_SUN8IW6)
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#define DRQDST_SS 16
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#if defined(CONFIG_ARCH_SUN50I)
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#define DRQDST_CE_TX DRQDST_SS
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#endif
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#endif
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#define DRQDST_OTG_EP1 17
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#define DRQDST_OTG_EP2 18
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#define DRQDST_OTG_EP3 19
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#define DRQDST_OTG_EP4 20
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#if !defined(CONFIG_ARCH_SUN8IW8)
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#define DRQDST_OTG_EP5 21
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#endif
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#else
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#define DRQDST_CIR_TX 15
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#define DRQDST_AC97 18
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1) \
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|| defined(CONFIG_ARCH_SUN9I)
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#define DRQDST_UART5TX 22
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#endif
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#define DRQDST_SPI0_TX 23
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#define DRQDST_SPI1_TX 24
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#if defined(CONFIG_ARCH_SUN8IW1) \
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&& defined(CONFIG_ARCH_SUN9I)
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#define DRQDST_SPI2TX 25
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#define DRQDST_SPI3TX 26
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1)
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#define DRQDST_NAND1 28
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#define DRQDST_MTC_ACC 29
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#define DRQDST_DIGITAL_MIC 30
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#elif defined(CONFIG_ARCH_SUN8IW6) \
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|| defined(CONFIG_ARCH_SUN8IW7)
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#define DRQDST_DAUDIO_2_TX 27
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#define DRQDST_TDM_TX 28
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#define DRQDST_CIR_TX 29
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#elif defined(CONFIG_ARCH_SUN50I)
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#define DRQDST_DAUDIO_2_TX 27
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#endif
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#endif /* CONFIG_ARCH_SUN8IW10 */
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#define sunxi_slave_id(d, s) (((d)<<16) | (s))
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#define GET_SRC_DRQ(x) ((x) & 0x000000ff)
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#define GET_DST_DRQ(x) ((x) & 0x00ff0000)
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/*
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* The following DRQ type just for CPUs.
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*/
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#ifdef CONFIG_ARCH_SUN9I
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#define DRQSRC_R_DAUDIO_0_RX 1
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#define DRQSRC_R_UART_RX 2
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#define DRQSRC_R_CIR_RX 3
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#define DRQSRC_R_DAUDIO_1_RX 4
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#define DRQSRC_SPI3_RX 5
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#define DRQDST_R_DAUDIO_0_TX 1
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#define DRQDST_R_UART_TX 2
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#define DRQDST_R_CIR_TX 3
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#define DRQDST_R_DAUDIO_1_TX 4
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#define DRQDST_SPI3_TX 5
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#endif
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#define SUNXI_DMA_DRV "sunxi_dmac"
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#define SUNXI_RDMA_DRV "sunxi_rdmac"
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#define SUNXI_FILTER(name) name##_filter_fn
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bool sunxi_rdma_filter_fn(struct dma_chan *chan, void *param);
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bool sunxi_dma_filter_fn(struct dma_chan *chan, void *param);
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struct sunxi_dma_info {
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char name[16];
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u32 port;
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struct device *use_dev;
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};
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#endif /* __SUNXI_DMA_H__ */
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