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SmartAudio/lichee/linux-4.9/drivers/pinctrl/sunxi/pinctrl-sun8iw17p1-r.c

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/*
* Allwinner sun8iw17p1 SoCs R_PIO pinctrl driver.
*
* Copyright(c) 2016-2020 Allwinnertech Co., Ltd.
* Author: superm <superm@allwinnertech.com>
* Author: zhouhuacai <zhouhuacai@allwinnertech.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8iw17p1_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb0"), /* SCK */
SUNXI_FUNCTION(0x3, "s_twi0"), /* SCK */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb0"), /* SDA */
SUNXI_FUNCTION(0x3, "s_twi0"), /* SDA */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag0"), /* MS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag0"), /* CK */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag0"), /* DO */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag0"), /* DI */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_spi0"), /* CLK */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_spi0"), /* CS */
SUNXI_FUNCTION(0x3, "s_pwm1"), /* PWM1 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "s_pwm2"), /* PWM2 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "s_pwm3"), /* PWM3 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart1"), /* TX */
SUNXI_FUNCTION(0x3, "s_pwm4"), /* PWM4 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart1"), /* RX */
SUNXI_FUNCTION(0x3, "s_pwm5"), /* PWM5 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart1"), /* RTS */
SUNXI_FUNCTION(0x3, "s_pwm6"), /* PWM6 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart1"), /* CTS */
SUNXI_FUNCTION(0x3, "s_pwm7"), /* PWM7 */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart2"), /* TX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart2"), /* RX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart2"), /* RTS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart2"), /* CTS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_can0"), /* TX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_can0"), /* RX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_cir0"), /* RX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart3"), /* TX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart3"), /* RX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart3"), /* RTS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart3"), /* CTS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart4"), /* TX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart4"), /* RX */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart4"), /* RTS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart4"), /* CTS */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi0"), /* SCK */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi0"), /* SDA */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi1"), /* SCK */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi1"), /* SDA */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 28),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi2"), /* SCK */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 29),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi2"), /* SDA */
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 29)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 30),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_watchdog_sig"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 30)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 31),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_r_watchdog_sig"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 31)),
};
#define IRQ_BANK_NUM 2
static const unsigned sun8iw17p1_r_irq_bank_base[IRQ_BANK_NUM] = {0};
static const struct sunxi_pinctrl_desc sun8iw17p1_r_pinctrl_data = {
.pins = sun8iw17p1_r_pins,
.npins = ARRAY_SIZE(sun8iw17p1_r_pins),
.pin_base = PL_BASE,
.irq_banks = IRQ_BANK_NUM,
.irq_bank_base = sun8iw17p1_r_irq_bank_base,
};
static int sun8iw17p1_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev, &sun8iw17p1_r_pinctrl_data);
}
static struct of_device_id sun8iw17p1_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun8iw17p1-r-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, sun8iw17p1_r_pinctrl_match);
static struct platform_driver sun8iw17p1_r_pinctrl_driver = {
.probe = sun8iw17p1_r_pinctrl_probe,
.driver = {
.name = "sun8iw17p1-r-pinctrl",
.owner = THIS_MODULE,
.of_match_table = sun8iw17p1_r_pinctrl_match,
},
};
static int __init sun8iw17p1_r_pio_init(void)
{
int ret;
ret = platform_driver_register(&sun8iw17p1_r_pinctrl_driver);
if (IS_ERR_VALUE(ret)) {
pr_debug("register sun50i r-pio controller failed\n");
return -EINVAL;
}
return 0;
}
postcore_initcall(sun8iw17p1_r_pio_init);
MODULE_AUTHOR("superm<superm@allwinnertech.com>");
MODULE_AUTHOR("zhouhuacai<zhouhuacai@allwinnertech.com>");
MODULE_DESCRIPTION("Allwinner sun8iw17p1 R_PIO pinctrl driver");
MODULE_LICENSE("GPL");
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