229 lines
7.7 KiB
C
Executable File
229 lines
7.7 KiB
C
Executable File
/*
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* Copyright (C) 2013 Allwinnertech, kevin.z.m <kevin@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable factor-based clock implementation
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*/
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#ifndef __MACH_SUNXI_CLK_SUN8IW17_H
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#define __MACH_SUNXI_CLK_SUN8IW17_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include "clk-factors.h"
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#define IO_ADDRESS(x) (void __iomem *)(((x) & 0x0fffffff) + \
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(((x) >> 4) & 0x0f000000) + \
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0xf0000000)
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/* CCMU Register List */
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#define PLL_CPU0 0x0000
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#define PLL_CPU1 0x0008
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#define PLL_DDR0 0x0010
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#define PLL_DDR1 0x0018
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#define PLL_PERIPH0 0x0020
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#define PLL_PERIPH1 0x0028
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#define PLL_GPU 0x0030
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#define PLL_VIDEO0 0x0040
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#define PLL_VIDEO1 0x0048
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#define PLL_VE 0x0058
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#define PLL_DE 0x0060
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#define PLL_ISP 0x0068
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#define PLL_HSIC 0x0070
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#define PLL_AUDIO 0x0078
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#define PLL_MIPI 0x0080
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#define PLL_EVE 0x00C0
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#define PLL_CPU0PAT 0x0100
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#define PLL_CPU1PAT 0x0108
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#define PLL_DDR0PAT 0x0110
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#define PLL_DDR1PAT 0x0118
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#define PLL_PERI1PAT 0x0128
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#define PLL_GPUPAT 0x0130
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#define PLL_VIDEO0PAT 0x0140
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#define PLL_VIDEO1PAT 0x0148
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#define PLL_VIDEO2PAT 0x0150
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#define PLL_VEPAT 0x0158
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#define PLL_DEPAT 0x0160
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#define PLL_ISPPAT 0x0168
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#define PLL_HSICPAT 0x0170
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#define PLL_AUDIOPAT 0x0178
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#define PLL_MIPIPAT 0x0180
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#define PLL_EVEPAT 0x01C0
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#define PLL_DDR1_SSC_LIN 0x0218
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#define CPU0_CFG 0x0500
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#define CPU1_CFG 0x0504
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#define PSI_CFG 0x0510
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#define AHB3_CFG 0x051C
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#define APB1_CFG 0x0520
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#define APB2_CFG 0x0524
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#define CCI400_CFG 0x0530
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#define MBUS_CFG 0x0540
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/* Accelerator */
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#define DE_CFG 0x0600
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#define DE_GATE 0x060C
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#define DI_CFG 0x0620
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#define DI_GATE 0x062C
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#define G2D_CFG 0x0630
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#define G2D_GATE 0x063C
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#define EVE_CFG 0x0650
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#define EVE_GATE 0x065C
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#define GPU_CFG 0x0670
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#define GPU_GATE 0x067C
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#define CE_CFG 0x0680
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#define CE_GATE 0x068C
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#define VE_CFG 0x0690
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#define VE_GATE 0x069C
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/* SYS Resource */
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#define DMA_GATE 0x070C
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#define MSGBOX_GATE 0x071C
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#define SPINLOCK_GATE 0x072C
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#define HSTIMER_GATE 0x073C
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#define AVS_CFG 0x0740
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#define DBGSYS_GATE 0x078C
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#define PSI_GATE 0x079C
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#define PWM_GATE 0x07AC
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/* Storage Medium */
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#define DRAM_CFG 0x0800
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#define MBUS_GATE 0x0804
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#define DRAM_GATE 0x080C
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#define NAND0_CFG 0x0810
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#define NAND1_CFG 0x0814
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#define NAND_GATE 0x082C
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#define SMHC0_CFG 0x0830
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#define SMHC1_CFG 0x0834
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#define SMHC2_CFG 0x0838
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#define SMHC3_CFG 0x083C
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#define SMHC_GATE 0x084C
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/* Common Interface */
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#define UART_GATE 0x090C
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#define TWI_GATE 0x091C
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#define CAN_GATE 0x092C
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#define SCR_GATE 0x093C
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#define SPI0_CFG 0x0940
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#define SPI1_CFG 0x0944
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#define SPI_GATE 0x096C
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#define GMAC_GATE 0x097C
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#define TS_CFG 0x09B0
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#define TS_GATE 0x09BC
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#define GPADC_GATE 0x09EC
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#define I2S0_CFG 0x0A10
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#define I2S1_CFG 0x0A14
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#define I2S2_CFG 0x0A18
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#define I2S_GATE 0x0A1C
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#define SPDIF_CFG 0x0A20
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#define SPDIF_GATE 0x0A2C
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#define DMIC_CFG 0x0A40
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#define DMIC_GATE 0x0A4C
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#define CODEC_1X_CFG 0x0A50
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#define CODEC_4X_CFG 0x0A54
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#define CODEC_GATE 0x0A5C
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#define USB0_CFG 0x0A70
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#define USB1_CFG 0x0A74
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#define USB2_CFG 0x0A78
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#define USB3_CFG 0x0A7C
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#define USB_GATE 0x0A8C
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/* Display Interface */
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#define MIPI_DSI_HOST_CFG 0x0B24
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#define MIPI_GATE 0x0B4C
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#define DISPLAY_TOP_GATE 0x0B5C
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#define TCON_LCD0_CFG 0x0B60
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#define TCON_LCD1_CFG 0x0B64
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#define TCON_LCD_GATE 0x0B7C
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#define TCON_TV_GATE 0x0B9C
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#define TVE_CFG 0x0BB0
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#define TVE_GATE 0x0BBC
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#define LVDS_GATE 0x0BAC
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#define TVD0_CFG 0x0BC0
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#define TVD1_CFG 0x0BC4
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#define TVD2_CFG 0x0BC8
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#define TVD3_CFG 0x0BCC
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#define TVD_GATE 0x0BDC
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#define CSI_MISC_CFG 0x0C00
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#define CSI_TOP_CFG 0x0C04
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#define CSI_MASTER0_CFG 0x0C08
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#define CSI_MASTER1_CFG 0x0C0C
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#define CSI_MASTER2_CFG 0x0C10
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#define CSI_MASTER3_CFG 0x0C14
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#define CSI_GATE 0x0C2C
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#define MIPI_RX_CFG 0x0C30
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/* others */
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#define CCMU_SEC_SWITCH 0x0F00
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#define PLL_LOCK_CTRL 0x0F04
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#define FRE_DET_CTRL 0x0F08
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#define FRE_UP_LIM_CTRL 0x0F0C
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#define FRE_DOWN_LIM_CTRL 0x0F10
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#define HOSC_CLK_OUTPUT 0x0F20
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#define CCMU_VERSION 0x0FF0
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#define SUNXI_CLK_MAX_REG 0x0FF0
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/* PRCM Register List */
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#define CPUS_CFG 0x0000
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#define CPUS_APBS1_CFG 0x000C
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#define CPUS_APBS2_CFG 0x0010
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#define CPUS_TIMER_GATE 0x011C
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#define CPUS_TWDOG_GATE 0x012C
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#define CPUS_PWM_GATE 0x013C
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#define CPUS_VM_CFG 0x0140
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#define CPUS_VM_GATE 0x014C
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#define CPUS_THS_GATE 0x015C
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#define CPUS_LRADC_GATE 0x016C
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#define CPUS_UART_GATE 0x018C
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#define CPUS_TWI_GATE 0x019C
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#define CPUS_CAN_GATE 0x01AC
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#define CPUS_RSB_GATE 0x01BC
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#define CPUS_CIR_CFG 0x01C0
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#define CPUS_CIR_GATE 0x01CC
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#define CPUS_SPI_CFG 0x01F0
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#define CPUS_SPI_GATE 0x01FC
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#define CPUS_RTC_GATE 0x020C
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#define CPUS_PLL_CTRL0 0x0240
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#define CPUS_PLL_CTRL1 0x0244
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#define CPUS_CLK_MAX_REG 0x0244
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/* RTC Register List */
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#define LOSC_OUT_GATE 0x0060
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#define F_N8X7_M0X4(nv, mv) FACTOR_ALL(nv, 8, 7, 0, 0, 0, mv, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X5_K4X2(nv, kv) FACTOR_ALL(nv, 8, 5, kv, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X7_M0X2(nv, mv) FACTOR_ALL(nv, 8, 7, 0, 0, 0, mv, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X5_K4X2_M0X2(nv, kv, mv) FACTOR_ALL(nv, 8, 5, kv, 4, 2, mv, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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#define F_N8X5_K4X2_M0X2_P16x2(nv, kv, mv, pv) \
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FACTOR_ALL(nv, 8, 5, \
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kv, 4, 2, \
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mv, 0, 2, \
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pv, 16, 2, \
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0, 0, 0, 0, 0, 0)
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#define F_N8X7_M0X5_P16x4(nv, mv, pv) \
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FACTOR_ALL(nv, 8, 7, 0, 0, 0, mv, 0, 5, \
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pv, 16, 4, 0, 0, 0, 0, 0, 0)
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#define PLLCPU0(n, k, m, p, freq) {F_N8X5_K4X2_M0X2_P16x2(n, k, m, p), freq}
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#define PLLCPU1(n, k, m, p, freq) {F_N8X5_K4X2_M0X2_P16x2(n, k, m, p), freq}
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#define PLLDDR0(n, m, freq) {F_N8X7_M0X2(n, m), freq}
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#define PLLDDR1(n, m, freq) {F_N8X7_M0X2(n, m), freq}
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#define PLLPERIPH0(n, k, freq) {F_N8X5_K4X2(n, k), freq}
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#define PLLPERIPH1(n, k, freq) {F_N8X5_K4X2(n, k), freq}
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#define PLLGPU(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLVIDEO0(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLVIDEO1(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLVE(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLDE(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLISP(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLHSIC(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#define PLLAUDIO(n, m, p, freq) {F_N8X7_M0X5_P16x4(n, m, p), freq}
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#define PLLEVE(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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#endif
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