534 lines
13 KiB
C
Executable File
534 lines
13 KiB
C
Executable File
/*
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* Allwinner SoCs de-interlace driver.
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*
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* Copyright (C) 2016 Allwinner.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include "di_ebios.h"
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#include "di_ebios_data.h"
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#include <linux/slab.h>
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#include <asm/io.h>
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extern volatile __di_dev_t *di_dev;
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__u32 DI_VAtoPA(__u32 va)
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{
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if ((va) > 0x40000000)
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return (va) - 0x40000000;
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return va;
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}
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/* should initial some registers for memory-to-memory de-interlace used */
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__s32 DI_Init(void)
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{
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#if defined CONFIG_ARCH_SUN9IW1
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di_dev->trd_ctrl.dwval = 0;
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di_dev->ch0_horzphase.bits.phase = 0;
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di_dev->ch1_horzphase.bits.phase = 0;
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di_dev->ch0_vertphase0.bits.phase = 0;
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di_dev->ch0_vertphase1.bits.phase = 0;
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di_dev->ch1_vertphase0.bits.phase = 0;
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di_dev->ch1_vertphase1.bits.phase = 0;
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di_dev->output_fmt.bits.byte_seq = 0;
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di_dev->input_fmt.bits.byte_seq = 0;
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#endif
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di_dev->bypass.bits.csc_bypass_en = 1; /* bypass CSC */
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di_dev->wb_linestrd_en.dwval = 0x1;
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di_dev->frm_ctrl.bits.out_ctrl = 1;
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di_dev->output_fmt.bits.alpha_en = 0x0;
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di_dev->bypass.bits.sram_map_sel = 0; /* normal mode */
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di_dev->agth_sel.bits.linebuf_agth = 1;
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DI_Set_Di_Ctrl(1, 3, 1, 1);
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return 0;
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}
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__s32 DI_Config_Src(__di_buf_addr_t *addr, __di_src_size_t *size,
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__di_src_type_t *type)
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{
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/* __u8 w_shift, h_shift; */
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__u32 image_w0, image_w1;
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/* __u32 x_off0, y_off0, x_off1, y_off1; */
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__u32 in_w0, in_h0, in_w1, in_h1;
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/* __u8 rgb16mode = 0; */
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image_w0 = size->src_width;
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in_w0 = size->scal_width;
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in_h0 = size->scal_height;
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image_w1 = (image_w0 + 0x1)>>1;
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in_w1 = (in_w0 + 0x1)>>1;
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in_h1 = (in_h0 + 0x1)>>1;
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/* added no-zero limited */
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in_h0 = (in_h0 != 0) ? in_h0 : 1;
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in_h1 = (in_h1 != 0) ? in_h1 : 1;
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in_w0 = (in_w0 != 0) ? in_w0 : 1;
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in_w1 = (in_w1 != 0) ? in_w1 : 1;
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if (type->mod == DI_UVCOMBINED) {
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di_dev->linestrd0.dwval = image_w0;
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di_dev->linestrd1.dwval = image_w1<<1;
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di_dev->linestrd2.dwval = 0x0;
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di_dev->buf_addr0.dwval = addr->ch0_addr;
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di_dev->buf_addr1.dwval = addr->ch1_addr;
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di_dev->buf_addr2.dwval = 0x0;
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} else if (type->mod == DI_UVCOMBINEDMB) {
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image_w0 = (image_w0 + 0x1f)&0xffffffe0;
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image_w1 = (image_w1 + 0x0f)&0xfffffff0;
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/* block offset */
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di_dev->tb_off0.bits.x_offset0 = 0;
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di_dev->tb_off0.bits.y_offset0 = 0;
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di_dev->tb_off0.bits.x_offset1 = (in_w0 + 0x1f) & 0x1f;
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di_dev->tb_off1.bits.x_offset0 = 0;
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di_dev->tb_off1.bits.y_offset0 = 0;
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di_dev->tb_off1.bits.x_offset1 = (((in_w1)<<1) + 0x1f) & 0x1f;
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di_dev->linestrd0.dwval =
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(((image_w0 + 0x1f)&0xffe0) - 0x1f)<<0x05;
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di_dev->linestrd1.dwval =
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(((((image_w1)<<1)+0x1f)&0xffe0) - 0x1f) << 0x05;
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di_dev->linestrd2.dwval = 0x00;
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di_dev->buf_addr0.dwval = addr->ch0_addr;
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di_dev->buf_addr1.dwval = addr->ch1_addr;
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di_dev->buf_addr2.dwval = 0x0;
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}
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di_dev->input_fmt.bits.data_mod = type->mod;
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di_dev->input_fmt.bits.data_fmt = type->fmt;
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di_dev->input_fmt.bits.data_ps = type->ps;
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di_dev->ch0_insize.bits.in_width = in_w0 - 1;
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di_dev->ch0_insize.bits.in_height = in_h0 - 1;
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di_dev->ch1_insize.bits.in_width = in_w1 - 1;
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di_dev->ch1_insize.bits.in_height = in_h1 - 1;
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return 0;
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}
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__s32 DI_Set_Scaling_Factor(__di_src_size_t *in_size,
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__di_out_size_t *out_size)
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{
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__s32 in_w0, in_h0, out_w0, out_h0;
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__s32 ch0_hstep, ch0_vstep;
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in_w0 = in_size->scal_width;
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in_h0 = in_size->scal_height;
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out_w0 = out_size->width;
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out_h0 = out_size->height;
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/* added no-zero limited */
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in_h0 = (in_h0 != 0) ? in_h0 : 1;
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in_w0 = (in_w0 != 0) ? in_w0 : 1;
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out_h0 = (out_h0 != 0) ? out_h0 : 1;
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out_w0 = (out_w0 != 0) ? out_w0 : 1;
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/* step factor */
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ch0_hstep = (in_w0<<16)/out_w0;
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ch0_vstep = (in_h0<<16)/out_h0;
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di_dev->ch0_horzfact.dwval = ch0_hstep;
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di_dev->ch0_vertfact.dwval = ch0_vstep;
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di_dev->ch1_horzfact.dwval = ch0_hstep;
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di_dev->ch1_vertfact.dwval = ch0_vstep;
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return 0;
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}
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__s32 DI_Set_Scaling_Coef(__di_src_size_t *in_size, __di_out_size_t *out_size,
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__di_src_type_t *in_type, __di_out_type_t *out_type)
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{
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__s32 in_w0, in_h0, out_w0, out_h0;
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__u32 int_part, float_part;
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__u32 zoom0_size, zoom1_size, zoom2_size, zoom3_size, zoom4_size;
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__u32 zoom5_size, al1_size;
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__u32 ch0h_sc, ch0v_sc;
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__u32 ch0v_fir_coef_addr, ch0h_fir_coef_addr;
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__u32 ch1v_fir_coef_addr, ch1h_fir_coef_addr;
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__u32 ch0v_fir_coef_ofst, ch0h_fir_coef_ofst;
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#if defined CONFIG_ARCH_SUN9IW1
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__u32 ch3h_fir_coef_addr, ch3v_fir_coef_addr;
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#else
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__u32 loop_count = 0;
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#endif
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#if defined SCALE_NO_SUPPORT
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__s32 i;
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#endif
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in_w0 = in_size->scal_width;
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in_h0 = in_size->scal_height;
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out_w0 = out_size->width;
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out_h0 = out_size->height;
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zoom0_size = 1;
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zoom1_size = 2;
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zoom2_size = 2;
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zoom3_size = 1;
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zoom4_size = 1;
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zoom5_size = 1;
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al1_size = zoom0_size + zoom1_size + zoom2_size + zoom3_size
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+ zoom4_size + zoom5_size;
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/* added no-zero limited */
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in_h0 = (in_h0 != 0) ? in_h0 : 1;
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in_w0 = (in_w0 != 0) ? in_w0 : 1;
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out_h0 = (out_h0 != 0) ? out_h0 : 1;
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out_w0 = (out_w0 != 0) ? out_w0 : 1;
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ch0h_sc = (in_w0<<1)/out_w0;
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ch0v_sc = (in_h0<<1)/out_h0;
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/* comput the fir coefficient offset in coefficient table */
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int_part = ch0h_sc>>1;
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float_part = ch0h_sc & 0x1;
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ch0h_fir_coef_ofst = (int_part == 0) ? zoom0_size :
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(int_part == 1) ? zoom0_size + float_part :
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(int_part == 2) ? zoom0_size + zoom1_size + float_part :
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(int_part == 3) ? zoom0_size + zoom1_size + zoom2_size :
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(int_part == 4) ? zoom0_size + zoom1_size + zoom2_size + zoom3_size :
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zoom0_size + zoom1_size + zoom2_size + zoom3_size + zoom4_size;
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int_part = ch0v_sc>>1;
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float_part = ch0v_sc & 0x1;
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ch0v_fir_coef_ofst = (int_part == 0) ? zoom0_size :
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(int_part == 1) ? zoom0_size + float_part :
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(int_part == 2) ? zoom0_size + zoom1_size + float_part :
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(int_part == 3) ? zoom0_size + zoom1_size + zoom2_size :
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(int_part == 4) ? zoom0_size + zoom1_size + zoom2_size + zoom3_size :
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zoom0_size + zoom1_size + zoom2_size + zoom3_size + zoom4_size;
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#if defined CONFIG_ARCH_SUN9IW1
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/* compute the fir coeficient address for each channel in horizontal
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* and vertical direction
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*/
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ch0h_fir_coef_addr = ch0h_fir_coef_ofst<<5;
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ch0v_fir_coef_addr = ch0v_fir_coef_ofst<<5;
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ch1h_fir_coef_addr = ch0h_fir_coef_ofst<<5;
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ch1v_fir_coef_addr = ch0v_fir_coef_ofst<<5;
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ch3h_fir_coef_addr = ch0h_fir_coef_addr<<5;
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ch3v_fir_coef_addr = ch0v_fir_coef_addr<<5;
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memcpy(&di_dev->ch0_horzcoef0,
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lan3coefftab32_left + ch0h_fir_coef_addr, 256);
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memcpy(&di_dev->ch0_horzcoef1,
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lan3coefftab32_right + ch0h_fir_coef_addr, 256);
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memcpy(&di_dev->ch0_vertcoef,
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lan2coefftab32 + ch0v_fir_coef_addr, 256);
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if ((out_type->fmt == DI_OUTUVCYUV420) ||
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(in_type->fmt == DI_INYUV420)) {
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memcpy(&di_dev->ch1_horzcoef0,
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bicubic8coefftab32_left + ch1h_fir_coef_addr, 256);
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memcpy(&di_dev->ch1_horzcoef1,
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bicubic8coefftab32_right + ch1h_fir_coef_addr, 256);
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memcpy(&di_dev->ch1_vertcoef,
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bicubic4coefftab32 + ch1v_fir_coef_addr, 256);
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} else {
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memcpy(&di_dev->ch1_horzcoef0,
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lan3coefftab32_left + ch1h_fir_coef_addr, 256);
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memcpy(&di_dev->ch1_horzcoef1,
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lan3coefftab32_right + ch1h_fir_coef_addr, 256);
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memcpy(&di_dev->ch1_vertcoef,
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lan2coefftab32 + ch1v_fir_coef_addr, 256);
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}
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if (out_type->alpha_en && (in_type->mod == DI_INTERLEAVED)) {
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memcpy(&di_dev->ch3_horzcoef0,
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bicubic8coefftab32_left + ch3h_fir_coef_addr, 256);
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memcpy(&di_dev->ch3_horzcoef1,
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bicubic8coefftab32_right + ch3h_fir_coef_addr, 256);
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memcpy(&di_dev->ch3_vertcoef,
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bicubic4coefftab32 + ch3v_fir_coef_addr, 256);
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}
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di_dev->frm_ctrl.bits.coef_rdy_en = 0x1;
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#else
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/* for single buffer */
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ch0h_fir_coef_addr = (ch0h_fir_coef_ofst<<5);
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ch0v_fir_coef_addr = (ch0v_fir_coef_ofst<<5);
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ch1h_fir_coef_addr = (ch0h_fir_coef_ofst<<5);
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ch1v_fir_coef_addr = (ch0v_fir_coef_ofst<<5);
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di_dev->frm_ctrl.bits.coef_access_ctrl = 1;
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while ((di_dev->status.bits.coef_access_status == 0) &&
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(loop_count < 40)) {
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loop_count++;
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}
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#if defined SCALE_NO_SUPPORT
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for (i = 0; i < 32; i++) {
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di_dev->ch0_horzcoef0[i].dwval = 0x00004000;
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di_dev->ch0_vertcoef[i].dwval = 0x00004000;
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di_dev->ch1_horzcoef0[i].dwval = 0x00004000;
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di_dev->ch1_vertcoef[i].dwval = 0x00004000;
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}
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#else
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memcpy(&di_dev->ch0_horzcoef0,
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lan2coefftab32 + ch0h_fir_coef_addr, 128);
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memcpy(&di_dev->ch0_vertcoef,
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lan2coefftab32 + ch0v_fir_coef_addr, 128);
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if ((out_type->fmt == DI_OUTUVCYUV420) ||
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(in_type->fmt == DI_INYUV420)) {
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memcpy(&di_dev->ch1_horzcoef0,
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bicubic4coefftab32 + ch1h_fir_coef_addr, 128);
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memcpy(&di_dev->ch1_vertcoef,
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bicubic4coefftab32 + ch1v_fir_coef_addr, 128);
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if (di_dev->ch1_horzcoef0[0].dwval != 0xfd0d290d) {
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pr_warn("DIDIDIDIDIDI wrong! di_dev->ch1_horzcoef0[0] = 0x%x.\n bicubic4coefftab32[64] = 0x%x, ch1h_fir_coef_addr = %d.\n",
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di_dev->ch1_horzcoef0[0].dwval,
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bicubic4coefftab32[64], ch1h_fir_coef_addr);
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}
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} else {
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memcpy(&di_dev->ch1_horzcoef0,
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lan2coefftab32 + ch1h_fir_coef_addr, 128);
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memcpy(&di_dev->ch1_vertcoef,
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lan2coefftab32 + ch1v_fir_coef_addr, 128);
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}
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#endif
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di_dev->frm_ctrl.bits.coef_access_ctrl = 0x0;
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#endif
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return 0;
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}
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__s32 DI_Set_Out_Format(__di_out_type_t *out_type)
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{
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di_dev->output_fmt.bits.data_fmt = out_type->fmt;
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di_dev->output_fmt.bits.data_ps = out_type->ps;
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return 0;
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}
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__s32 DI_Set_Out_Size(__di_out_size_t *out_size)
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{
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__u32 out_w1, out_h1, out_w0, out_h0;
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out_h0 = out_size->height;
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out_w0 = out_size->width;
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out_w1 = (out_size->width + 0x1) >> 1;
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out_h1 = (out_size->height + 0x1) >> 1;
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/* added no-zero limited */
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out_h0 = (out_h0 != 0) ? out_h0 : 1;
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out_h1 = (out_h1 != 0) ? out_h1 : 1;
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out_w0 = (out_w0 != 0) ? out_w0 : 1;
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out_w1 = (out_w1 != 0) ? out_w1 : 1;
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di_dev->ch0_outsize.bits.out_height = out_h0 - 1;
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di_dev->ch0_outsize.bits.out_width = out_w0 - 1;
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di_dev->ch1_outsize.bits.out_height = out_h1 - 1;
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di_dev->ch1_outsize.bits.out_width = out_w1 - 1;
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return 0;
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}
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__s32 DI_Set_Writeback_Addr(__di_buf_addr_t *addr)
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{
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di_dev->wb_addr0.dwval = addr->ch0_addr;
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di_dev->wb_addr1.dwval = addr->ch1_addr;
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di_dev->wb_addr2.dwval = addr->ch2_addr;
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return 0;
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}
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__s32 DI_Set_Writeback_Addr_ex(__di_buf_addr_t *addr, __di_out_size_t *size,
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__di_out_type_t *type)
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{
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__u32 image_w0, image_w1;
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image_w0 = size->fb_width;
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image_w1 = (image_w0 + 0x1)>>1;
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if (type->fmt == DI_OUTUVCYUV420) {
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di_dev->wb_linestrd0.dwval = image_w0;
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di_dev->wb_linestrd1.dwval = (image_w1<<1);
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di_dev->wb_linestrd2.dwval = 0;
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addr->ch0_addr = addr->ch0_addr;
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addr->ch1_addr = addr->ch1_addr;
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addr->ch2_addr = 0x0;
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DI_Set_Writeback_Addr(addr);
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}
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return 0;
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}
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__s32 DI_Set_Di_Ctrl(__u8 en, __u8 mode, __u8 diagintp_en, __u8 tempdiff_en)
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{
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di_dev->di_ctrl.bits.en = en;
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di_dev->di_ctrl.bits.flag_out_en = (mode == 3)?0:1;
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di_dev->di_ctrl.bits.mod = mode;
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di_dev->di_ctrl.bits.diagintp_en = diagintp_en;
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di_dev->di_ctrl.bits.tempdiff_en = tempdiff_en;
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#if defined CONFIG_ARCH_SUN9IW1
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di_dev->di_spatcomp.bits.th2 = 0;
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di_dev->di_lumath.bits.avglumashifter = 8;
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#else
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di_dev->di_lumath.bits.minlumath = 4;
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di_dev->di_spatcomp.bits.th2 = 5;
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di_dev->di_tempdiff.bits.ambiguity_th = 5;
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di_dev->di_diagintp.bits.th0 = 60;
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di_dev->di_diagintp.bits.th1 = 0;
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di_dev->di_diagintp.bits.th3 = 30;
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di_dev->di_chromadiff.bits.chroma_diff_th = 31;
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#endif
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return 0;
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}
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__s32 DI_Set_Di_PreFrame_Addr(__u32 luma_addr, __u32 chroma_addr)
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{
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di_dev->di_preluma.dwval = luma_addr;
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di_dev->di_prechroma.dwval = chroma_addr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
__s32 DI_Set_Di_MafFlag_Src(__u32 cur_addr, __u32 pre_addr, __u32 stride)
|
|
{
|
|
di_dev->di_tileflag0.dwval = pre_addr;
|
|
di_dev->di_tileflag1.dwval = cur_addr;
|
|
di_dev->di_flaglinestrd.dwval = stride;
|
|
|
|
return 0;
|
|
}
|
|
|
|
__s32 DI_Set_Di_Field(u32 field)
|
|
{
|
|
di_dev->field_ctrl.bits.field_cnt = (field & 0x1);
|
|
|
|
return 0;
|
|
}
|
|
__s32 DI_Set_Reg_Rdy(void)
|
|
{
|
|
di_dev->frm_ctrl.bits.reg_rdy_en = 0x1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
__s32 DI_Enable(void)
|
|
{
|
|
/* di_dev->modl_en.bits.en = 0x1; */
|
|
di_dev->frm_ctrl.bits.frm_start = 0x1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
__s32 DI_Module_Enable(void)
|
|
{
|
|
di_dev->modl_en.bits.en = 0x1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
__s32 DI_Set_Reset(void)
|
|
{
|
|
di_dev->frm_ctrl.bits.frm_start = 0x0;
|
|
di_dev->modl_en.bits.en = 0x0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
__s32 DI_Set_Irq_Enable(__u32 enable)
|
|
{
|
|
di_dev->int_en.bits.wb_en = (enable & 0x1);
|
|
return 0;
|
|
}
|
|
|
|
__s32 DI_Clear_irq(void)
|
|
{
|
|
di_dev->int_status.bits.wb_status = 0x1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
__s32 DI_Get_Irq_Status(void)
|
|
{
|
|
__u32 wb_finish;
|
|
__u32 wb_processing;
|
|
|
|
wb_finish = di_dev->int_status.bits.wb_status;
|
|
wb_processing = di_dev->status.bits.wb_status;
|
|
|
|
if (wb_processing)
|
|
return 2;
|
|
else if (wb_finish == 0 && wb_processing == 0)
|
|
return 1;
|
|
else if (wb_finish)
|
|
return 0;
|
|
else
|
|
return 3;
|
|
}
|
|
|
|
__s32 DI_Set_Writeback_Start(void)
|
|
{
|
|
di_dev->frm_ctrl.bits.wb_en = 0x1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined CONFIG_ARCH_SUN9IW1
|
|
__s32 DI_Internal_Set_Clk(__u32 enable)
|
|
{
|
|
__u32 reg_val, base;
|
|
|
|
base = 0xf3000000; /* FIXME */
|
|
|
|
if (enable) {
|
|
reg_val = readl(base + 0x0);
|
|
reg_val |= 0x1;
|
|
writel(reg_val, base + 0x0);
|
|
|
|
reg_val = readl(base + 0x4);
|
|
reg_val |= 0x1;
|
|
writel(reg_val, base + 0x4);
|
|
|
|
reg_val = readl(base + 0x8);
|
|
reg_val |= 0x1;
|
|
writel(reg_val, base + 0x8);
|
|
|
|
reg_val = readl(base + 0xc);
|
|
reg_val |= 0x1;
|
|
writel(reg_val, base + 0xc);
|
|
} else {
|
|
reg_val = readl(base + 0x0);
|
|
reg_val &= 0xfffffffe;
|
|
writel(reg_val, base + 0x0);
|
|
|
|
reg_val = readl(base + 0x4);
|
|
reg_val &= 0xfffffffe;
|
|
writel(reg_val, base + 0x4);
|
|
|
|
reg_val = readl(base + 0x8);
|
|
reg_val &= 0xfffffffe;
|
|
writel(reg_val, base + 0x8);
|
|
|
|
reg_val = readl(base + 0xc);
|
|
reg_val &= 0xfffffffe;
|
|
writel(reg_val, base + 0xc);
|
|
}
|
|
return 0;
|
|
}
|
|
#else
|
|
__s32 DI_Internal_Set_Clk(__u32 enable)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|