328 lines
11 KiB
C
Executable File
328 lines
11 KiB
C
Executable File
/*
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* sun6i_gmac.h: Allwinnertech Gigabit Ethernet u-boot driver
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* Copyright © 2006-2012, AllWinner Technology. Co., Ltd.
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* All Rights Resvered
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* Author: shuge <shuge@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, mail to service@allwinnertech.com.
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*/
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#ifndef __SUN6I_GMAC_H__
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#define __SUN6I_GMAC_H__
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#define DMA_DESC_TX 0x40000000
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#define DMA_DESC_RX (DMA_DESC_TX + sizeof(dma_desc_t))
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#define TX_BUF1_ADDR 0x44A00000
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#define TX_BUF2_ADDR 0x44A01000
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#define RX_BUF1_ADDR 0x44A02000
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#define RX_BUF2_ADDR 0x44A03000
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#define MAX_BUF_LEN 0x000007FF
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#define GMAC_BASE 0x01c30000 /* aw1633: 0x01c30000 aw1630: 0x01c50000 */
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#define GMAC_CONTROL (0x00) /* Configuration */
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#define GMAC_FRAME_FILTER (0x04) /* Frame Filter */
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#define GMAC_HASH_HIGH (0x08) /* Multicast Hash Table High */
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#define GMAC_HASH_LOW (0x0c) /* Multicast Hash Table Low */
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#define GMAC_GMII_ADDR (0x10) /* MII Address */
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#define GMAC_GMII_DATA (0x14) /* MII Data */
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#define GMAC_FLOW_CTRL (0x18) /* Flow Control */
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#define GMAC_INT_STATUS (0x38) /* Interrupt status register */
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#define GMAC_INT_MASK (0x3c) /* interrupt mask register */
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#define GMAC_ADDR_HI(reg) (0x40 + (reg<<3)) /* upper 16bits of MAC address */
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#define GMAC_ADDR_LO(reg) (0x44 + (reg<<3)) /* lower 32bits of MAC address */
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#define GMAC_RGMII_STATUS (0xD8) /* S/R-GMII status */
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/* GMAC_CONTROL value */
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#define GMAC_CTL_TC 0x01000000 /* Transmit Configuration in RGMII */
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#define GMAC_CTL_WD 0x00800000 /* Watchdog Disable */
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#define GMAC_CTL_JD 0x00400000 /* Jabber Disable */
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#define GMAC_CTL_BE 0x00200000 /* Frame Burst Enable (only Half) */
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#define GMAC_CTL_JE 0x00100000 /* Jumbo Frame Enable */
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#define GMAC_CTL_IFG 0x000E0000 /* Inter-Frame Gap */
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#define GMAC_CTL_DCRS 0x00010000 /* Disable Carrier Sense During Transmission (only Half) */
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#define GMAC_CTL_PS 0x00008000 /* Port Select 0:GMII, 1:MII */
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#define GMAC_CTL_FES 0x00004000 /* Indicates the speed in Fast Ethernet(MII) mode */
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#define GMAC_CTL_ROD 0x00002000 /* Receive own disable (only half-duplex) */
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#define GMAC_CTL_LM 0x00001000 /* Loopback mode */
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#define GMAC_CTL_DM 0x00000800 /* Duplex mode */
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#define GMAC_CTL_DR 0x00000200 /* Retry disable (only half-duplex) */
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#define GMAC_CTL_LUD 0x00000100 /* Link Up/Down (only RGMII/SGMII) */
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#define GMAC_CTL_ACS 0x00000080 /* Automatic Pad/CRC Stripping */
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#define GMAC_CTL_BL 0x00000060 /* Back-off limit.(only half-duplex) */
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#define GMAC_CTL_DC 0x00000010 /* Deferral Check.(only half-duplex) */
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#define GMAC_CTL_TE 0x00000008 /* Transmit Enable */
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#define GMAC_CTL_RE 0x00000004 /* Receiver Enalbe */
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/* GMAC_GMII_ADDR value */
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#define MII_BUSY 0x00000001
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#define MII_WRITE 0x00000002
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#define MII_PHY_MASK 0x0000FFC0
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#define MII_CR_MASK 0x0000001C
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#define GDMA_BASE (GMAC_BASE + 0x1000) /* GDMA Base */
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#define GDMA_BUS_MODE (0x00) /* Bus Mode Register */
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#define GDMA_XMT_POLL (0x04) /* Transmit Poll Demand */
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#define GDMA_RCV_POLL (0x08) /* Received Poll Demand */
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#define GDMA_RCV_LIST (0x0C) /* Receive List Base */
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#define GDMA_XMT_LIST (0x10) /* Transmit List Base */
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#define GDMA_STATUS (0x14) /* Status Register */
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#define GDMA_OP_MODE (0x18) /* DMA Operational Mode */
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#define GDMA_INTR_ENA (0x1c) /* Interrupt Enable */
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#define GDMA_MISSED_FRAME (0x20) /* Missed Frame and Buffer Overflow Counter */
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#define GDMA_CUR_TX_DESC (0x48) /* Current Host Transmit Descriptor */
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#define GDMA_CUR_RX_DESC (0x4C) /* Current Host Received Descriptor */
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#define GDMA_CUR_TX_BUF (0x50) /* Current Host Transmit Buffer Address */
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#define GDMA_CUR_RX_BUF (0x54) /* Current Host Received Buffer Address */
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/* GDMA_BUS_MODE value */
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#define SOFT_RESET 0x00000001 /* Software reset gdma */
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#define BUS_MODE_DA 0x00000002 /* DMA Arbitration */
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#define BUS_ADDR_ALIGN 0x02000000 /* Address-Aligned Beats */
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#define BUS_MODE_4PBL 0x01000000 /* 4xPBL Mode */
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#define BUS_MODE_USP 0x00800000
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#define BUS_MODE_RXPBL 0x007E0000
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#define BUS_MODE_PBL 0x00003F00
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#define BUS_MODE_FIXBUST 0x00010000
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#define BUS_MODE_DSL 0x0000007C /* Descriptor skip length */
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#define BUS_MODE_RTPR 0x00000C00 /* Rx TX priority ratio */
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/* GDMA_STATUS value */
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#define STATUS_TBUS 0x00000004
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#define STATUS_RBUS 0x00000080
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#define STATUS_TPS 0x00700000
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#define TPS_STOP 0x00000000
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#define TPS_FETCH_DESC 0x00100000
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#define TPS_WAIT_STAT 0x00200000
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#define TPS_READ_DATA 0x00300000
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#define TPS_SUSP 0x00600000
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#define TPS_CLOSE_DESC 0x00700000
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#define STATUS_RPS 0x000E0000
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#define RPS_STOP 0x00000000
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#define RPS_FETCH_DESC 0x00020000
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#define RPS_WAIT_STAT 0x00060000
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#define RPS_SUSP 0x00080000
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#define RPS_CLOSE_DESC 0x000A0000
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#define RPS_WRITE_HOST 0x000E0000
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/* GDMA_OP_MODE value */
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#define OP_MODE_RSF 0x02000000 /* Receive Store and Forward */
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#define OP_MODE_DFF 0x01000000 /* Disable Flushing of Received Frames */
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#define OP_MODE_RFA2 0x00800000 /* MSB of Threshold for Activating Flow Control */
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#define OP_MODE_RFD2 0x00400000 /* MSB of Threshold for Deactivating Flow Control */
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#define OP_MODE_TSF 0x00200000 /* Transmit Store and Forward */
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#define OP_MODE_FTF 0x00100000 /* Flush Transmit FIFO */
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#define OP_MODE_TTC 0x0001C000 /* Transmit Threshold Control */
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#define OP_MODE_ST 0x00002000 /* Start/Stop Transmission Command */
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#define OP_MODE_RFD 0x00001800 /* Threshold for deactivating flow control */
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#define OP_MODE_RFA 0x00000600 /* Threshold for activating flow control */
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#define OP_MODE_EFC 0x00000100 /* Enable HW flow control */
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#define OP_MODE_FEF 0x00000080 /* Forward Error Frames */
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#define OP_MODE_FUF 0x00000040 /* Forward Undersized Frames */
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#define OP_MODE_RTC 0x00000018 /* Receive Threshold Control */
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#define OP_MODE_OSF 0x00000004 /* Operate on Second Frame */
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#define OP_MODE_SR 0x00000002 /* Start/Stop Receive */
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/* pin configure for GMAC */
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#define GPIO_BASE 0x01C20800
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#define PA_CFG0 (GPIO_BASE + 0x00)
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#define PA_CFG1 (GPIO_BASE + 0x04)
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#define PA_CFG2 (GPIO_BASE + 0x08)
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#define PA_CFG3 (GPIO_BASE + 0x0C)
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/* Clk control */
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#define CCMU_BASE 0x01c20000
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#if GET_SYSCLK_SELF
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#define PLL1_CFG 0x00
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#define PLL6_CFG 0x28
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#define AXI_CFG (0x50)
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#define AXI_SRC_SEL 0x00030000
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#define AXI_SRC_LOSC 0x00000000
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#define AXI_SRC_OSC24M 0x00010000
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#define AXI_SRC_PLL1 0x00020000
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#define AXI_CLK_DIV 0x00000007
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#define AHB1_CFG (0x54)
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#define AHB1_SRC_SEL 0x00003000
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#define AHB1_SRC_LOSC 0x00000000
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#define AHB1_SRC_OSC24M 0x00001000
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#define AHB1_SRC_AXI 0x00002000
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#define AHB1_SRC_PLL6 0x00003000
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#define AHB1_PER_DIV 0x000000C0
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#define AHB1_CLK_DIV 0x00000030
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#endif
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#define AHB1_GATING (0x60)
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#define GMAC_AHB_BIT 0x00000200
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/* PHY address */
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#define PHY_ADDR 0x01
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#define PHY_DM 0x0010
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#define PHY_AUTO_NEG 0x0020
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#define PHY_POWERDOWN 0x0080
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#define PHY_NEG_EN 0x1000
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#define PHY_
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#define MII_CLK 0x00000008
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/* bits 4 3 2 | AHB1 Clock | MDC Clock
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* -------------------------------------------------------
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* 0 0 0 | 60 ~ 100 MHz | div-42
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* 0 0 1 | 100 ~ 150 MHz | div-62
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* 0 1 0 | 20 ~ 35 MHz | div-16
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* 0 1 1 | 35 ~ 60 MHz | div-26
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* 1 0 0 | 150 ~ 250 MHz | div-102
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* 1 0 1 | 250 ~ 300 MHz | div-124
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* 1 1 x | Reserved |
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*/
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/* Default tx descriptor */
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#define TX_SINGLE_DESC0 0x80000000
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#define TX_SINGLE_DESC1 0x63000000
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/* Default rx descriptor */
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#define RX_SINGLE_DESC0 0x80000000
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#define RX_SINGLE_DESC1 0x83000000
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#define GMAC_DEF_CONF ( \
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GMAC_CTL_WD | \
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GMAC_CTL_JD | \
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GMAC_CTL_JE | \
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GMAC_CTL_PS | \
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GMAC_CTL_DM | \
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GMAC_CTL_ACS | \
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GMAC_CTL_TE | \
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GMAC_CTL_RE | \
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((0<<17) & GMAC_CTL_IFG) \
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)
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#define GDMA_OP_CONF ( \
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OP_MODE_RSF | \
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OP_MODE_DFF | \
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OP_MODE_TSF | \
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((0<<17) & OP_MODE_TTC) | \
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((0<<11) & OP_MODE_RFD) | \
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((0<<9) & OP_MODE_RFA) | \
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OP_MODE_EFC | \
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OP_MODE_FEF | \
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OP_MODE_FUF | \
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((0<<3) & OP_MODE_RSF) \
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)
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enum rx_frame_status { /* IPC status */
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good_frame = 0,
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discard_frame = 1,
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csum_none = 2,
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llc_snap = 4,
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};
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typedef union {
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struct {
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/* TDES0 */
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u32 deferred:1; /* Deferred bit (only half-duplex) */
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u32 under_err:1; /* Underflow error */
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u32 ex_deferral:1; /* Excessive deferral */
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u32 coll_cnt:4; /* Collision count */
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u32 vlan_tag:1; /* VLAN Frame */
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u32 ex_coll:1; /* Excessive collision */
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u32 late_coll:1; /* Late collision */
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u32 no_carr:1; /* No carrier */
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u32 loss_carr:1; /* Loss of collision */
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u32 ipdat_err:1; /* IP payload error */
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u32 frm_flu:1; /* Frame flushed */
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u32 jab_timeout:1; /* Jabber timeout */
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u32 err_sum:1; /* Error summary */
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u32 iphead_err:1; /* IP header error */
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u32 ttss:1; /* Transmit time stamp status */
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u32 reserved0:13;
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u32 own:1; /* Own bit. CPU:0, DMA:1 */
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} tx;
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struct {
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/* RDES0 */
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u32 chsum_err:1; /* Payload checksum error */
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u32 crc_err:1; /* CRC error */
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u32 dribbling:1; /* Dribble bit error */
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u32 mii_err:1; /* Received error (bit3) */
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u32 recv_wt:1; /* Received watchdog timeout */
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u32 frm_type:1; /* Frame type */
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u32 late_coll:1; /* Late Collision */
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u32 ipch_err:1; /* IPv header checksum error (bit7) */
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u32 last_desc:1; /* Laset descriptor */
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u32 first_desc:1; /* First descriptor */
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u32 vlan_tag:1; /* VLAN Tag */
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u32 over_err:1; /* Overflow error (bit11) */
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u32 len_err:1; /* Length error */
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u32 sou_filter:1; /* Source address filter fail */
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u32 desc_err:1; /* Descriptor error */
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u32 err_sum:1; /* Error summary (bit15) */
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u32 frm_len:14; /* Frame length */
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u32 des_filter:1; /* Destination address filter fail */
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u32 own:1; /* Own bit. CPU:0, DMA:1 */
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#define RX_PKT_OK 0x7FFFB77C
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#define RX_LEN 0x3FFF0000
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} rx;
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u32 all;
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} desc0_u;
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typedef union {
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struct {
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/* TDES1 */
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u32 buf1_size:11; /* Transmit buffer1 size */
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u32 buf2_size:11; /* Transmit buffer2 size */
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u32 ttse:1; /* Transmit time stamp enable */
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u32 dis_pad:1; /* Disable pad (bit23) */
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u32 adr_chain:1; /* Second address chained */
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u32 end_ring:1; /* Transmit end of ring */
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u32 crc_dis:1; /* Disable CRC */
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u32 cic:2; /* Checksum insertion control (bit27:28) */
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u32 first_sg:1; /* First Segment */
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u32 last_seg:1; /* Last Segment */
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u32 interrupt:1; /* Interrupt on completion */
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} tx;
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struct {
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/* RDES1 */
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u32 buf1_size:11; /* Received buffer1 size */
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u32 buf2_size:11; /* Received buffer2 size */
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u32 reserved1:2;
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u32 adr_chain:1; /* Second address chained */
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u32 end_ring:1; /* Received end of ring */
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u32 reserved2:5;
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u32 dis_ic:1; /* Disable interrupt on completion */
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} rx;
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u32 all;
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} desc1_u;
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enum csum_insertion{
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cic_dis = 0,
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cic_ip = 1,
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cic_no_pse = 2,
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cic_full = 3,
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};
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typedef struct dma_desc {
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desc0_u desc0;
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desc1_u desc1;
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u32 *desc2;
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u32 *desc3;
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} __attribute__((packed)) dma_desc_t;
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int gmac_initialize(bd_t * bis);
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#endif /*_GMAC_REG_H_*/
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